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# frv testcase for bhilr $ICCi,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global bhilr
bhilr:
        set_spr_addr    ok1,lr
        set_icc         0x0 0
        bhilr           icc0,0
        fail
ok1:
        set_spr_addr    bad,lr
        set_icc         0x1 1
        bhilr           icc1,1
 
        set_spr_addr    ok3,lr
        set_icc         0x2 2
        bhilr           icc2,2
        fail
ok3:
        set_spr_addr    bad,lr
        set_icc         0x3 3
        bhilr           icc3,3
 
        set_spr_addr    bad,lr
        set_icc         0x4 0
        bhilr           icc0,0
 
        set_spr_addr    bad,lr
        set_icc         0x5 1
        bhilr           icc1,1
 
        set_spr_addr    bad,lr
        set_icc         0x6 2
        bhilr           icc2,2
 
        set_spr_addr    bad,lr
        set_icc         0x7 3
        bhilr           icc3,3
 
        set_spr_addr    ok9,lr
        set_icc         0x8 0
        bhilr           icc0,0
        fail
ok9:
        set_spr_addr    bad,lr
        set_icc         0x9 1
        bhilr           icc1,1
 
        set_spr_addr    okb,lr
        set_icc         0xa 2
        bhilr           icc2,2
        fail
okb:
        set_spr_addr    bad,lr
        set_icc         0xb 3
        bhilr           icc3,3
 
        set_spr_addr    bad,lr
        set_icc         0xc 0
        bhilr           icc0,0
 
        set_spr_addr    bad,lr
        set_icc         0xd 1
        bhilr           icc1,1
 
        set_spr_addr    bad,lr
        set_icc         0xe 2
        bhilr           icc2,2
 
        set_spr_addr    bad,lr
        set_icc         0xf 3
        bhilr           icc3,3
 
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for bhilr $ICCi,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global bhilr`
9			`bhilr:`
10			`set_spr_addr ok1,lr`
11			`set_icc 0x0 0`
12			`bhilr icc0,0`
13			`fail`
14			`ok1:`
15			`set_spr_addr bad,lr`
16			`set_icc 0x1 1`
17			`bhilr icc1,1`
18
19			`set_spr_addr ok3,lr`
20			`set_icc 0x2 2`
21			`bhilr icc2,2`
22			`fail`
23			`ok3:`
24			`set_spr_addr bad,lr`
25			`set_icc 0x3 3`
26			`bhilr icc3,3`
27
28			`set_spr_addr bad,lr`
29			`set_icc 0x4 0`
30			`bhilr icc0,0`
31
32			`set_spr_addr bad,lr`
33			`set_icc 0x5 1`
34			`bhilr icc1,1`
35
36			`set_spr_addr bad,lr`
37			`set_icc 0x6 2`
38			`bhilr icc2,2`
39
40			`set_spr_addr bad,lr`
41			`set_icc 0x7 3`
42			`bhilr icc3,3`
43
44			`set_spr_addr ok9,lr`
45			`set_icc 0x8 0`
46			`bhilr icc0,0`
47			`fail`
48			`ok9:`
49			`set_spr_addr bad,lr`
50			`set_icc 0x9 1`
51			`bhilr icc1,1`
52
53			`set_spr_addr okb,lr`
54			`set_icc 0xa 2`
55			`bhilr icc2,2`
56			`fail`
57			`okb:`
58			`set_spr_addr bad,lr`
59			`set_icc 0xb 3`
60			`bhilr icc3,3`
61
62			`set_spr_addr bad,lr`
63			`set_icc 0xc 0`
64			`bhilr icc0,0`
65
66			`set_spr_addr bad,lr`
67			`set_icc 0xd 1`
68			`bhilr icc1,1`
69
70			`set_spr_addr bad,lr`
71			`set_icc 0xe 2`
72			`bhilr icc2,2`
73
74			`set_spr_addr bad,lr`
75			`set_icc 0xf 3`
76			`bhilr icc3,3`
77
78			`pass`
79			`bad:`
80			`fail`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bhilr.cgs] - Blame information for rev 26