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# frv testcase for fbullr $FCCi,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fbullr
fbullr:
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fbullr          fcc0,0
 
        set_spr_addr    ok2,lr
        set_fcc         0x1 1
        fbullr          fcc1,1
        fail
ok2:
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fbullr          fcc2,2
 
        set_spr_addr    ok4,lr
        set_fcc         0x3 3
        fbullr          fcc3,3
        fail
ok4:
        set_spr_addr    ok5,lr
        set_fcc         0x4 0
        fbullr          fcc0,0
        fail
ok5:
        set_spr_addr    ok6,lr
        set_fcc         0x5 1
        fbullr          fcc1,1
        fail
ok6:
        set_spr_addr    ok7,lr
        set_fcc         0x6 2
        fbullr          fcc2,2
        fail
ok7:
        set_spr_addr    ok8,lr
        set_fcc         0x7 3
        fbullr          fcc3,3
        fail
ok8:
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fbullr          fcc0,0
 
        set_spr_addr    oka,lr
        set_fcc         0x9 1
        fbullr          fcc1,1
        fail
oka:
        set_spr_addr    bad,lr
        set_fcc         0xa 2
        fbullr          fcc2,2
 
        set_spr_addr    okc,lr
        set_fcc         0xb 3
        fbullr          fcc3,3
        fail
okc:
        set_spr_addr    okd,lr
        set_fcc         0xc 0
        fbullr          fcc0,0
        fail
okd:
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        fbullr          fcc1,1
        fail
oke:
        set_spr_addr    okf,lr
        set_fcc         0xe 2
        fbullr          fcc2,2
        fail
okf:
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        fbullr          fcc3,3
        fail
okg:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for fbullr $FCCi,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fbullr`
9			`fbullr:`
10			`set_spr_addr bad,lr`
11			`set_fcc 0x0 0`
12			`fbullr fcc0,0`
13
14			`set_spr_addr ok2,lr`
15			`set_fcc 0x1 1`
16			`fbullr fcc1,1`
17			`fail`
18			`ok2:`
19			`set_spr_addr bad,lr`
20			`set_fcc 0x2 2`
21			`fbullr fcc2,2`
22
23			`set_spr_addr ok4,lr`
24			`set_fcc 0x3 3`
25			`fbullr fcc3,3`
26			`fail`
27			`ok4:`
28			`set_spr_addr ok5,lr`
29			`set_fcc 0x4 0`
30			`fbullr fcc0,0`
31			`fail`
32			`ok5:`
33			`set_spr_addr ok6,lr`
34			`set_fcc 0x5 1`
35			`fbullr fcc1,1`
36			`fail`
37			`ok6:`
38			`set_spr_addr ok7,lr`
39			`set_fcc 0x6 2`
40			`fbullr fcc2,2`
41			`fail`
42			`ok7:`
43			`set_spr_addr ok8,lr`
44			`set_fcc 0x7 3`
45			`fbullr fcc3,3`
46			`fail`
47			`ok8:`
48			`set_spr_addr bad,lr`
49			`set_fcc 0x8 0`
50			`fbullr fcc0,0`
51
52			`set_spr_addr oka,lr`
53			`set_fcc 0x9 1`
54			`fbullr fcc1,1`
55			`fail`
56			`oka:`
57			`set_spr_addr bad,lr`
58			`set_fcc 0xa 2`
59			`fbullr fcc2,2`
60
61			`set_spr_addr okc,lr`
62			`set_fcc 0xb 3`
63			`fbullr fcc3,3`
64			`fail`
65			`okc:`
66			`set_spr_addr okd,lr`
67			`set_fcc 0xc 0`
68			`fbullr fcc0,0`
69			`fail`
70			`okd:`
71			`set_spr_addr oke,lr`
72			`set_fcc 0xd 1`
73			`fbullr fcc1,1`
74			`fail`
75			`oke:`
76			`set_spr_addr okf,lr`
77			`set_fcc 0xe 2`
78			`fbullr fcc2,2`
79			`fail`
80			`okf:`
81			`set_spr_addr okg,lr`
82			`set_fcc 0xf 3`
83			`fbullr fcc3,3`
84			`fail`
85			`okg:`
86			`pass`
87			`bad:`
88			`fail`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fbullr.cgs] - Blame information for rev 26