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# frv testcase for fcbnelr $FCCi,$ccond,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fcbnelr
fcbnelr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbnelr         fcc0,0,0
 
        set_spr_addr    ok2,lr
        set_fcc         0x1 1
        fcbnelr         fcc1,0,1
        fail
ok2:
        set_spr_addr    ok3,lr
        set_fcc         0x2 2
        fcbnelr         fcc2,0,2
        fail
ok3:
        set_spr_addr    ok4,lr
        set_fcc         0x3 3
        fcbnelr         fcc3,0,3
        fail
ok4:
        set_spr_addr    ok5,lr
        set_fcc         0x4 0
        fcbnelr         fcc0,0,0
        fail
ok5:
        set_spr_addr    ok6,lr
        set_fcc         0x5 1
        fcbnelr         fcc1,0,1
        fail
ok6:
        set_spr_addr    ok7,lr
        set_fcc         0x6 2
        fcbnelr         fcc2,0,2
        fail
ok7:
        set_spr_addr    ok8,lr
        set_fcc         0x7 3
        fcbnelr         fcc3,0,3
        fail
ok8:
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbnelr         fcc0,0,0
 
        set_spr_addr    oka,lr
        set_fcc         0x9 1
        fcbnelr         fcc1,0,1
        fail
oka:
        set_spr_addr    okb,lr
        set_fcc         0xa 2
        fcbnelr         fcc2,0,2
        fail
okb:
        set_spr_addr    okc,lr
        set_fcc         0xb 3
        fcbnelr         fcc3,0,3
        fail
okc:
        set_spr_addr    okd,lr
        set_fcc         0xc 0
        fcbnelr         fcc0,0,0
        fail
okd:
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        fcbnelr         fcc1,0,1
        fail
oke:
        set_spr_addr    okf,lr
        set_fcc         0xe 2
        fcbnelr         fcc2,0,2
        fail
okf:
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        fcbnelr         fcc3,0,3
        fail
okg:
 
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbnelr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    oki,lr
        set_fcc         0x1 1
        fcbnelr         fcc1,1,1
        fail
oki:
        set_spr_immed   1,lcr
        set_spr_addr    okj,lr
        set_fcc         0x2 2
        fcbnelr         fcc2,1,2
        fail
okj:
        set_spr_immed   1,lcr
        set_spr_addr    okk,lr
        set_fcc         0x3 3
        fcbnelr         fcc3,1,3
        fail
okk:
        set_spr_immed   1,lcr
        set_spr_addr    okl,lr
        set_fcc         0x4 0
        fcbnelr         fcc0,1,0
        fail
okl:
        set_spr_immed   1,lcr
        set_spr_addr    okm,lr
        set_fcc         0x5 1
        fcbnelr         fcc1,1,1
        fail
okm:
        set_spr_immed   1,lcr
        set_spr_addr    okn,lr
        set_fcc         0x6 2
        fcbnelr         fcc2,1,2
        fail
okn:
        set_spr_immed   1,lcr
        set_spr_addr    oko,lr
        set_fcc         0x7 3
        fcbnelr         fcc3,1,3
        fail
oko:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbnelr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    okq,lr
        set_fcc         0x9 1
        fcbnelr         fcc1,1,1
        fail
okq:
        set_spr_immed   1,lcr
        set_spr_addr    okr,lr
        set_fcc         0xa 2
        fcbnelr         fcc2,1,2
        fail
okr:
        set_spr_immed   1,lcr
        set_spr_addr    oks,lr
        set_fcc         0xb 3
        fcbnelr         fcc3,1,3
        fail
oks:
        set_spr_immed   1,lcr
        set_spr_addr    okt,lr
        set_fcc         0xc 0
        fcbnelr         fcc0,1,0
        fail
okt:
        set_spr_immed   1,lcr
        set_spr_addr    oku,lr
        set_fcc         0xd 1
        fcbnelr         fcc1,1,1
        fail
oku:
        set_spr_immed   1,lcr
        set_spr_addr    okv,lr
        set_fcc         0xe 2
        fcbnelr         fcc2,1,2
        fail
okv:
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_fcc         0xf 3
        fcbnelr         fcc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
 
        set_fcc         0x0 0
        fcbnelr fcc0,1,0
        set_fcc         0x1 1
        fcbnelr fcc1,1,1
        set_fcc         0x2 2
        fcbnelr fcc2,1,2
        set_fcc         0x3 3
        fcbnelr fcc3,1,3
        set_fcc         0x4 0
        fcbnelr fcc0,1,0
        set_fcc         0x5 1
        fcbnelr fcc1,1,1
        set_fcc         0x6 2
        fcbnelr fcc2,1,2
        set_fcc         0x7 3
        fcbnelr fcc3,1,3
        set_fcc         0x8 0
        fcbnelr fcc0,1,0
        set_fcc         0x9 1
        fcbnelr fcc1,1,1
        set_fcc         0xa 2
        fcbnelr fcc2,1,2
        set_fcc         0xb 3
        fcbnelr fcc3,1,3
        set_fcc         0xc 0
        fcbnelr fcc0,1,0
        set_fcc         0xd 1
        fcbnelr fcc1,1,1
        set_fcc         0xe 2
        fcbnelr fcc2,1,2
        set_fcc         0xf 3
        fcbnelr fcc3,1,3
 
        ; ccond is false
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        fcbnelr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        fcbnelr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        fcbnelr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        fcbnelr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        fcbnelr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        fcbnelr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        fcbnelr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        fcbnelr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        fcbnelr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        fcbnelr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        fcbnelr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        fcbnelr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        fcbnelr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        fcbnelr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        fcbnelr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        fcbnelr fcc3,0,3
 
        pass
bad:
        fail

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbnelr.cgs] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for fcbnelr $FCCi,$ccond,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fcbnelr`
9			`fcbnelr:`
10			`; ccond is true`
11			`set_spr_immed 128,lcr`
12			`set_spr_addr bad,lr`
13			`set_fcc 0x0 0`
14			`fcbnelr fcc0,0,0`
15
16			`set_spr_addr ok2,lr`
17			`set_fcc 0x1 1`
18			`fcbnelr fcc1,0,1`
19			`fail`
20			`ok2:`
21			`set_spr_addr ok3,lr`
22			`set_fcc 0x2 2`
23			`fcbnelr fcc2,0,2`
24			`fail`
25			`ok3:`
26			`set_spr_addr ok4,lr`
27			`set_fcc 0x3 3`
28			`fcbnelr fcc3,0,3`
29			`fail`
30			`ok4:`
31			`set_spr_addr ok5,lr`
32			`set_fcc 0x4 0`
33			`fcbnelr fcc0,0,0`
34			`fail`
35			`ok5:`
36			`set_spr_addr ok6,lr`
37			`set_fcc 0x5 1`
38			`fcbnelr fcc1,0,1`
39			`fail`
40			`ok6:`
41			`set_spr_addr ok7,lr`
42			`set_fcc 0x6 2`
43			`fcbnelr fcc2,0,2`
44			`fail`
45			`ok7:`
46			`set_spr_addr ok8,lr`
47			`set_fcc 0x7 3`
48			`fcbnelr fcc3,0,3`
49			`fail`
50			`ok8:`
51			`set_spr_addr bad,lr`
52			`set_fcc 0x8 0`
53			`fcbnelr fcc0,0,0`
54
55			`set_spr_addr oka,lr`
56			`set_fcc 0x9 1`
57			`fcbnelr fcc1,0,1`
58			`fail`
59			`oka:`
60			`set_spr_addr okb,lr`
61			`set_fcc 0xa 2`
62			`fcbnelr fcc2,0,2`
63			`fail`
64			`okb:`
65			`set_spr_addr okc,lr`
66			`set_fcc 0xb 3`
67			`fcbnelr fcc3,0,3`
68			`fail`
69			`okc:`
70			`set_spr_addr okd,lr`
71			`set_fcc 0xc 0`
72			`fcbnelr fcc0,0,0`
73			`fail`
74			`okd:`
75			`set_spr_addr oke,lr`
76			`set_fcc 0xd 1`
77			`fcbnelr fcc1,0,1`
78			`fail`
79			`oke:`
80			`set_spr_addr okf,lr`
81			`set_fcc 0xe 2`
82			`fcbnelr fcc2,0,2`
83			`fail`
84			`okf:`
85			`set_spr_addr okg,lr`
86			`set_fcc 0xf 3`
87			`fcbnelr fcc3,0,3`
88			`fail`
89			`okg:`
90
91			`; ccond is true`
92			`set_spr_immed 1,lcr`
93			`set_spr_addr bad,lr`
94			`set_fcc 0x0 0`
95			`fcbnelr fcc0,1,0`
96
97			`set_spr_immed 1,lcr`
98			`set_spr_addr oki,lr`
99			`set_fcc 0x1 1`
100			`fcbnelr fcc1,1,1`
101			`fail`
102			`oki:`
103			`set_spr_immed 1,lcr`
104			`set_spr_addr okj,lr`
105			`set_fcc 0x2 2`
106			`fcbnelr fcc2,1,2`
107			`fail`
108			`okj:`
109			`set_spr_immed 1,lcr`
110			`set_spr_addr okk,lr`
111			`set_fcc 0x3 3`
112			`fcbnelr fcc3,1,3`
113			`fail`
114			`okk:`
115			`set_spr_immed 1,lcr`
116			`set_spr_addr okl,lr`
117			`set_fcc 0x4 0`
118			`fcbnelr fcc0,1,0`
119			`fail`
120			`okl:`
121			`set_spr_immed 1,lcr`
122			`set_spr_addr okm,lr`
123			`set_fcc 0x5 1`
124			`fcbnelr fcc1,1,1`
125			`fail`
126			`okm:`
127			`set_spr_immed 1,lcr`
128			`set_spr_addr okn,lr`
129			`set_fcc 0x6 2`
130			`fcbnelr fcc2,1,2`
131			`fail`
132			`okn:`
133			`set_spr_immed 1,lcr`
134			`set_spr_addr oko,lr`
135			`set_fcc 0x7 3`
136			`fcbnelr fcc3,1,3`
137			`fail`
138			`oko:`
139			`set_spr_immed 1,lcr`
140			`set_spr_addr bad,lr`
141			`set_fcc 0x8 0`
142			`fcbnelr fcc0,1,0`
143
144			`set_spr_immed 1,lcr`
145			`set_spr_addr okq,lr`
146			`set_fcc 0x9 1`
147			`fcbnelr fcc1,1,1`
148			`fail`
149			`okq:`
150			`set_spr_immed 1,lcr`
151			`set_spr_addr okr,lr`
152			`set_fcc 0xa 2`
153			`fcbnelr fcc2,1,2`
154			`fail`
155			`okr:`
156			`set_spr_immed 1,lcr`
157			`set_spr_addr oks,lr`
158			`set_fcc 0xb 3`
159			`fcbnelr fcc3,1,3`
160			`fail`
161			`oks:`
162			`set_spr_immed 1,lcr`
163			`set_spr_addr okt,lr`
164			`set_fcc 0xc 0`
165			`fcbnelr fcc0,1,0`
166			`fail`
167			`okt:`
168			`set_spr_immed 1,lcr`
169			`set_spr_addr oku,lr`
170			`set_fcc 0xd 1`
171			`fcbnelr fcc1,1,1`
172			`fail`
173			`oku:`
174			`set_spr_immed 1,lcr`
175			`set_spr_addr okv,lr`
176			`set_fcc 0xe 2`
177			`fcbnelr fcc2,1,2`
178			`fail`
179			`okv:`
180			`set_spr_immed 1,lcr`
181			`set_spr_addr okw,lr`
182			`set_fcc 0xf 3`
183			`fcbnelr fcc3,1,3`
184			`fail`
185			`okw:`
186			`; ccond is false`
187			`set_spr_immed 128,lcr`
188
189			`set_fcc 0x0 0`
190			`fcbnelr fcc0,1,0`
191			`set_fcc 0x1 1`
192			`fcbnelr fcc1,1,1`
193			`set_fcc 0x2 2`
194			`fcbnelr fcc2,1,2`
195			`set_fcc 0x3 3`
196			`fcbnelr fcc3,1,3`
197			`set_fcc 0x4 0`
198			`fcbnelr fcc0,1,0`
199			`set_fcc 0x5 1`
200			`fcbnelr fcc1,1,1`
201			`set_fcc 0x6 2`
202			`fcbnelr fcc2,1,2`
203			`set_fcc 0x7 3`
204			`fcbnelr fcc3,1,3`
205			`set_fcc 0x8 0`
206			`fcbnelr fcc0,1,0`
207			`set_fcc 0x9 1`
208			`fcbnelr fcc1,1,1`
209			`set_fcc 0xa 2`
210			`fcbnelr fcc2,1,2`
211			`set_fcc 0xb 3`
212			`fcbnelr fcc3,1,3`
213			`set_fcc 0xc 0`
214			`fcbnelr fcc0,1,0`
215			`set_fcc 0xd 1`
216			`fcbnelr fcc1,1,1`
217			`set_fcc 0xe 2`
218			`fcbnelr fcc2,1,2`
219			`set_fcc 0xf 3`
220			`fcbnelr fcc3,1,3`
221
222			`; ccond is false`
223			`set_spr_immed 1,lcr`
224			`set_fcc 0x0 0`
225			`fcbnelr fcc0,0,0`
226			`set_spr_immed 1,lcr`
227			`set_fcc 0x1 1`
228			`fcbnelr fcc1,0,1`
229			`set_spr_immed 1,lcr`
230			`set_fcc 0x2 2`
231			`fcbnelr fcc2,0,2`
232			`set_spr_immed 1,lcr`
233			`set_fcc 0x3 3`
234			`fcbnelr fcc3,0,3`
235			`set_spr_immed 1,lcr`
236			`set_fcc 0x4 0`
237			`fcbnelr fcc0,0,0`
238			`set_spr_immed 1,lcr`
239			`set_fcc 0x5 1`
240			`fcbnelr fcc1,0,1`
241			`set_spr_immed 1,lcr`
242			`set_fcc 0x6 2`
243			`fcbnelr fcc2,0,2`
244			`set_spr_immed 1,lcr`
245			`set_fcc 0x7 3`
246			`fcbnelr fcc3,0,3`
247			`set_spr_immed 1,lcr`
248			`set_fcc 0x8 0`
249			`fcbnelr fcc0,0,0`
250			`set_spr_immed 1,lcr`
251			`set_fcc 0x9 1`
252			`fcbnelr fcc1,0,1`
253			`set_spr_immed 1,lcr`
254			`set_fcc 0xa 2`
255			`fcbnelr fcc2,0,2`
256			`set_spr_immed 1,lcr`
257			`set_fcc 0xb 3`
258			`fcbnelr fcc3,0,3`
259			`set_spr_immed 1,lcr`
260			`set_fcc 0xc 0`
261			`fcbnelr fcc0,0,0`
262			`set_spr_immed 1,lcr`
263			`set_fcc 0xd 1`
264			`fcbnelr fcc1,0,1`
265			`set_spr_immed 1,lcr`
266			`set_fcc 0xe 2`
267			`fcbnelr fcc2,0,2`
268			`set_spr_immed 1,lcr`
269			`set_fcc 0xf 3`
270			`fcbnelr fcc3,0,3`
271
272			`pass`
273			`bad:`
274			`fail`