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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr550/] [cmqsubhss.cgs] - Blame information for rev 26

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Line No. Rev Author Line
1 26 jlechner
# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
2
# mach: all
3
 
4
        .include "../testutils.inc"
5
 
6
        start
7
 
8
        .global msubhss
9
msubhss:
10
        set_spr_immed   0x1b1b,cccr
11
 
12
        set_fr_iimmed   0x0000,0x0000,fr10
13
        set_fr_iimmed   0xdead,0x0000,fr11
14
        set_fr_iimmed   0x0000,0x0000,fr12
15
        set_fr_iimmed   0x0000,0xbeef,fr13
16
        cmqsubhss       fr10,fr12,fr14,cc0,1
17
        test_fr_limmed  0x0000,0x0000,fr14
18
        test_fr_limmed  0xdead,0x4111,fr15
19
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
20
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
21
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
22
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
23
 
24
        set_fr_iimmed   0x0000,0xdead,fr10
25
        set_fr_iimmed   0x1234,0x5678,fr11
26
        set_fr_iimmed   0xbeef,0x0000,fr12
27
        set_fr_iimmed   0x1111,0x1111,fr13
28
        cmqsubhss       fr10,fr12,fr14,cc0,1
29
        test_fr_limmed  0x4111,0xdead,fr14
30
        test_fr_limmed  0x0123,0x4567,fr15
31
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
32
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
33
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
34
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
35
 
36
        set_spr_immed   0,msr0
37
        set_fr_iimmed   0x1234,0x5678,fr10
38
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
39
        set_fr_iimmed   0xffff,0xffff,fr12
40
        set_fr_iimmed   0xfffe,0xffff,fr13
41
        cmqsubhss       fr10,fr12,fr14,cc0,1
42
        test_fr_limmed  0x1235,0x5679,fr14
43
        test_fr_limmed  0x7fff,0x7fff,fr15
44
        test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
45
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
46
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
47
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
48
 
49
        set_spr_immed   0,msr0
50
        set_fr_iimmed   0x8001,0x8001,fr10
51
        set_fr_iimmed   0x8001,0x8001,fr11
52
        set_fr_iimmed   0x0001,0x0002,fr12
53
        set_fr_iimmed   0x0002,0x0001,fr13
54
        cmqsubhss       fr10,fr12,fr14,cc4,1
55
        test_fr_limmed  0x8000,0x8000,fr14
56
        test_fr_limmed  0x8000,0x8000,fr15
57
        test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
58
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
59
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
60
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
61
 
62
        set_spr_immed   0,msr0
63
        set_fr_iimmed   0x0001,0x0001,fr10
64
        set_fr_iimmed   0xffff,0xffff,fr11
65
        set_fr_iimmed   0x8000,0x8000,fr12
66
        set_fr_iimmed   0x8000,0x8000,fr13
67
        cmqsubhss.p     fr10,fr10,fr14,cc4,1
68
        cmqsubhss       fr12,fr10,fr16,cc4,1
69
        test_fr_limmed  0x0000,0x0000,fr14
70
        test_fr_limmed  0x0000,0x0000,fr15
71
        test_fr_limmed  0x8000,0x8000,fr16
72
        test_fr_limmed  0x8001,0x8001,fr17
73
        test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
74
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
75
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
76
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
77
 
78
        set_spr_immed   0,msr0
79
        set_fr_iimmed   0x0000,0x0000,fr10
80
        set_fr_iimmed   0xdead,0x0000,fr11
81
        set_fr_iimmed   0x0000,0x0000,fr12
82
        set_fr_iimmed   0x0000,0xbeef,fr13
83
        cmqsubhss       fr10,fr12,fr14,cc1,0
84
        test_fr_limmed  0x0000,0x0000,fr14
85
        test_fr_limmed  0xdead,0x4111,fr15
86
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
87
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
88
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
89
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
90
 
91
        set_fr_iimmed   0x0000,0xdead,fr10
92
        set_fr_iimmed   0x1234,0x5678,fr11
93
        set_fr_iimmed   0xbeef,0x0000,fr12
94
        set_fr_iimmed   0x1111,0x1111,fr13
95
        cmqsubhss       fr10,fr12,fr14,cc1,0
96
        test_fr_limmed  0x4111,0xdead,fr14
97
        test_fr_limmed  0x0123,0x4567,fr15
98
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
99
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
100
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
101
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
102
 
103
        set_spr_immed   0,msr0
104
        set_fr_iimmed   0x1234,0x5678,fr10
105
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
106
        set_fr_iimmed   0xffff,0xffff,fr12
107
        set_fr_iimmed   0xfffe,0xffff,fr13
108
        cmqsubhss       fr10,fr12,fr14,cc1,0
109
        test_fr_limmed  0x1235,0x5679,fr14
110
        test_fr_limmed  0x7fff,0x7fff,fr15
111
        test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
112
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
113
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
114
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
115
 
116
        set_spr_immed   0,msr0
117
        set_fr_iimmed   0x8001,0x8001,fr10
118
        set_fr_iimmed   0x8001,0x8001,fr11
119
        set_fr_iimmed   0x0001,0x0002,fr12
120
        set_fr_iimmed   0x0002,0x0001,fr13
121
        cmqsubhss       fr10,fr12,fr14,cc5,0
122
        test_fr_limmed  0x8000,0x8000,fr14
123
        test_fr_limmed  0x8000,0x8000,fr15
124
        test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
125
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
126
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
127
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
128
 
129
        set_spr_immed   0,msr0
130
        set_fr_iimmed   0x0001,0x0001,fr10
131
        set_fr_iimmed   0xffff,0xffff,fr11
132
        set_fr_iimmed   0x8000,0x8000,fr12
133
        set_fr_iimmed   0x8000,0x8000,fr13
134
        cmqsubhss.p     fr10,fr10,fr14,cc5,0
135
        cmqsubhss       fr12,fr10,fr16,cc5,0
136
        test_fr_limmed  0x0000,0x0000,fr14
137
        test_fr_limmed  0x0000,0x0000,fr15
138
        test_fr_limmed  0x8000,0x8000,fr16
139
        test_fr_limmed  0x8001,0x8001,fr17
140
        test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
141
        test_spr_bits   2,1,1,msr0              ; msr0.ovf not set
142
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
143
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
144
 
145
        set_fr_iimmed   0x1111,0x1111,fr14
146
        set_fr_iimmed   0x2222,0x2222,fr15
147
        set_spr_immed   0,msr0
148
        set_fr_iimmed   0x0000,0x0000,fr10
149
        set_fr_iimmed   0xdead,0x0000,fr11
150
        set_fr_iimmed   0x0000,0x0000,fr12
151
        set_fr_iimmed   0x0000,0xbeef,fr13
152
        cmqsubhss       fr10,fr12,fr14,cc0,0
153
        test_fr_limmed  0x1111,0x1111,fr14
154
        test_fr_limmed  0x2222,0x2222,fr15
155
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
156
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
157
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
158
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
159
 
160
        set_fr_iimmed   0x0000,0xdead,fr10
161
        set_fr_iimmed   0x1234,0x5678,fr11
162
        set_fr_iimmed   0xbeef,0x0000,fr12
163
        set_fr_iimmed   0x1111,0x1111,fr13
164
        cmqsubhss       fr10,fr12,fr14,cc0,0
165
        test_fr_limmed  0x1111,0x1111,fr14
166
        test_fr_limmed  0x2222,0x2222,fr15
167
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
168
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
169
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
170
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
171
 
172
        set_spr_immed   0,msr0
173
        set_fr_iimmed   0x1234,0x5678,fr10
174
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
175
        set_fr_iimmed   0xffff,0xffff,fr12
176
        set_fr_iimmed   0xfffe,0xffff,fr13
177
        cmqsubhss       fr10,fr12,fr14,cc0,0
178
        test_fr_limmed  0x1111,0x1111,fr14
179
        test_fr_limmed  0x2222,0x2222,fr15
180
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
181
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
182
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
183
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
184
 
185
        set_spr_immed   0,msr0
186
        set_fr_iimmed   0x8001,0x8001,fr10
187
        set_fr_iimmed   0x8001,0x8001,fr11
188
        set_fr_iimmed   0x0001,0x0002,fr12
189
        set_fr_iimmed   0x0002,0x0001,fr13
190
        cmqsubhss       fr10,fr12,fr14,cc4,0
191
        test_fr_limmed  0x1111,0x1111,fr14
192
        test_fr_limmed  0x2222,0x2222,fr15
193
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
194
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
195
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
196
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
197
 
198
        set_fr_iimmed   0x3333,0x3333,fr16
199
        set_fr_iimmed   0x4444,0x4444,fr17
200
        set_spr_immed   0,msr0
201
        set_fr_iimmed   0x0001,0x0001,fr10
202
        set_fr_iimmed   0xffff,0xffff,fr11
203
        set_fr_iimmed   0x8000,0x8000,fr12
204
        set_fr_iimmed   0x8000,0x8000,fr13
205
        cmqsubhss.p     fr10,fr10,fr14,cc4,0
206
        cmqsubhss       fr12,fr10,fr16,cc4,0
207
        test_fr_limmed  0x1111,0x1111,fr14
208
        test_fr_limmed  0x2222,0x2222,fr15
209
        test_fr_limmed  0x3333,0x3333,fr16
210
        test_fr_limmed  0x4444,0x4444,fr17
211
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
212
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
213
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
214
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
215
 
216
        set_fr_iimmed   0x1111,0x1111,fr14
217
        set_fr_iimmed   0x2222,0x2222,fr15
218
        set_spr_immed   0,msr0
219
        set_fr_iimmed   0x0000,0x0000,fr10
220
        set_fr_iimmed   0xdead,0x0000,fr11
221
        set_fr_iimmed   0x0000,0x0000,fr12
222
        set_fr_iimmed   0x0000,0xbeef,fr13
223
        cmqsubhss       fr10,fr12,fr14,cc1,1
224
        test_fr_limmed  0x1111,0x1111,fr14
225
        test_fr_limmed  0x2222,0x2222,fr15
226
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
227
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
228
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
229
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
230
 
231
        set_fr_iimmed   0x0000,0xdead,fr10
232
        set_fr_iimmed   0x1234,0x5678,fr11
233
        set_fr_iimmed   0xbeef,0x0000,fr12
234
        set_fr_iimmed   0x1111,0x1111,fr13
235
        cmqsubhss       fr10,fr12,fr14,cc1,1
236
        test_fr_limmed  0x1111,0x1111,fr14
237
        test_fr_limmed  0x2222,0x2222,fr15
238
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
239
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
240
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
241
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
242
 
243
        set_spr_immed   0,msr0
244
        set_fr_iimmed   0x1234,0x5678,fr10
245
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
246
        set_fr_iimmed   0xffff,0xffff,fr12
247
        set_fr_iimmed   0xfffe,0xffff,fr13
248
        cmqsubhss       fr10,fr12,fr14,cc1,1
249
        test_fr_limmed  0x1111,0x1111,fr14
250
        test_fr_limmed  0x2222,0x2222,fr15
251
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
252
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
253
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
254
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
255
 
256
        set_spr_immed   0,msr0
257
        set_fr_iimmed   0x8001,0x8001,fr10
258
        set_fr_iimmed   0x8001,0x8001,fr11
259
        set_fr_iimmed   0x0001,0x0002,fr12
260
        set_fr_iimmed   0x0002,0x0001,fr13
261
        cmqsubhss       fr10,fr12,fr14,cc5,1
262
        test_fr_limmed  0x1111,0x1111,fr14
263
        test_fr_limmed  0x2222,0x2222,fr15
264
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
265
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
266
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
267
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
268
 
269
        set_fr_iimmed   0x3333,0x3333,fr16
270
        set_fr_iimmed   0x4444,0x4444,fr17
271
        set_spr_immed   0,msr0
272
        set_fr_iimmed   0x0001,0x0001,fr10
273
        set_fr_iimmed   0xffff,0xffff,fr11
274
        set_fr_iimmed   0x8000,0x8000,fr12
275
        set_fr_iimmed   0x8000,0x8000,fr13
276
        cmqsubhss.p     fr10,fr10,fr14,cc5,1
277
        cmqsubhss       fr12,fr10,fr16,cc5,1
278
        test_fr_limmed  0x1111,0x1111,fr14
279
        test_fr_limmed  0x2222,0x2222,fr15
280
        test_fr_limmed  0x3333,0x3333,fr16
281
        test_fr_limmed  0x4444,0x4444,fr17
282
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
283
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
284
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
285
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
286
 
287
        set_fr_iimmed   0x1111,0x1111,fr14
288
        set_fr_iimmed   0x2222,0x2222,fr15
289
        set_spr_immed   0,msr0
290
        set_fr_iimmed   0x0000,0x0000,fr10
291
        set_fr_iimmed   0xdead,0x0000,fr11
292
        set_fr_iimmed   0x0000,0x0000,fr12
293
        set_fr_iimmed   0x0000,0xbeef,fr13
294
        cmqsubhss       fr10,fr12,fr14,cc2,1
295
        test_fr_limmed  0x1111,0x1111,fr14
296
        test_fr_limmed  0x2222,0x2222,fr15
297
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
298
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
299
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
300
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
301
 
302
        set_fr_iimmed   0x0000,0xdead,fr10
303
        set_fr_iimmed   0x1234,0x5678,fr11
304
        set_fr_iimmed   0xbeef,0x0000,fr12
305
        set_fr_iimmed   0x1111,0x1111,fr13
306
        cmqsubhss       fr10,fr12,fr14,cc2,0
307
        test_fr_limmed  0x1111,0x1111,fr14
308
        test_fr_limmed  0x2222,0x2222,fr15
309
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
310
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
311
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
312
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
313
 
314
        set_spr_immed   0,msr0
315
        set_fr_iimmed   0x1234,0x5678,fr10
316
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
317
        set_fr_iimmed   0xffff,0xffff,fr12
318
        set_fr_iimmed   0xfffe,0xffff,fr13
319
        cmqsubhss       fr10,fr12,fr14,cc2,1
320
        test_fr_limmed  0x1111,0x1111,fr14
321
        test_fr_limmed  0x2222,0x2222,fr15
322
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
323
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
324
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
325
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
326
 
327
        set_spr_immed   0,msr0
328
        set_fr_iimmed   0x8001,0x8001,fr10
329
        set_fr_iimmed   0x8001,0x8001,fr11
330
        set_fr_iimmed   0x0001,0x0002,fr12
331
        set_fr_iimmed   0x0002,0x0001,fr13
332
        cmqsubhss       fr10,fr12,fr14,cc6,0
333
        test_fr_limmed  0x1111,0x1111,fr14
334
        test_fr_limmed  0x2222,0x2222,fr15
335
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
336
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
337
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
338
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
339
 
340
        set_fr_iimmed   0x3333,0x3333,fr16
341
        set_fr_iimmed   0x4444,0x4444,fr17
342
        set_spr_immed   0,msr0
343
        set_fr_iimmed   0x0001,0x0001,fr10
344
        set_fr_iimmed   0xffff,0xffff,fr11
345
        set_fr_iimmed   0x8000,0x8000,fr12
346
        set_fr_iimmed   0x8000,0x8000,fr13
347
        cmqsubhss.p     fr10,fr10,fr14,cc6,1
348
        cmqsubhss       fr12,fr10,fr16,cc6,0
349
        test_fr_limmed  0x1111,0x1111,fr14
350
        test_fr_limmed  0x2222,0x2222,fr15
351
        test_fr_limmed  0x3333,0x3333,fr16
352
        test_fr_limmed  0x4444,0x4444,fr17
353
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is set
354
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
355
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
356
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
357
 
358
        set_fr_iimmed   0x1111,0x1111,fr14
359
        set_fr_iimmed   0x2222,0x2222,fr15
360
        set_spr_immed   0,msr0
361
        set_fr_iimmed   0x0000,0x0000,fr10
362
        set_fr_iimmed   0xdead,0x0000,fr11
363
        set_fr_iimmed   0x0000,0x0000,fr12
364
        set_fr_iimmed   0x0000,0xbeef,fr13
365
        cmqsubhss       fr10,fr12,fr14,cc3,1
366
        test_fr_limmed  0x1111,0x1111,fr14
367
        test_fr_limmed  0x2222,0x2222,fr15
368
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
369
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
370
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
371
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
372
 
373
        set_fr_iimmed   0x0000,0xdead,fr10
374
        set_fr_iimmed   0x1234,0x5678,fr11
375
        set_fr_iimmed   0xbeef,0x0000,fr12
376
        set_fr_iimmed   0x1111,0x1111,fr13
377
        cmqsubhss       fr10,fr12,fr14,cc3,0
378
        test_fr_limmed  0x1111,0x1111,fr14
379
        test_fr_limmed  0x2222,0x2222,fr15
380
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
381
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
382
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
383
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
384
 
385
        set_spr_immed   0,msr0
386
        set_fr_iimmed   0x1234,0x5678,fr10
387
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
388
        set_fr_iimmed   0xffff,0xffff,fr12
389
        set_fr_iimmed   0xfffe,0xffff,fr13
390
        cmqsubhss       fr10,fr12,fr14,cc3,1
391
        test_fr_limmed  0x1111,0x1111,fr14
392
        test_fr_limmed  0x2222,0x2222,fr15
393
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
394
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
395
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
396
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
397
 
398
        set_spr_immed   0,msr0
399
        set_fr_iimmed   0x8001,0x8001,fr10
400
        set_fr_iimmed   0x8001,0x8001,fr11
401
        set_fr_iimmed   0x0001,0x0002,fr12
402
        set_fr_iimmed   0x0002,0x0001,fr13
403
        cmqsubhss       fr10,fr12,fr14,cc7,0
404
        test_fr_limmed  0x1111,0x1111,fr14
405
        test_fr_limmed  0x2222,0x2222,fr15
406
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
407
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
408
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
409
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
410
 
411
        set_fr_iimmed   0x3333,0x3333,fr16
412
        set_fr_iimmed   0x4444,0x4444,fr17
413
        set_spr_immed   0,msr0
414
        set_fr_iimmed   0x0001,0x0001,fr10
415
        set_fr_iimmed   0xffff,0xffff,fr11
416
        set_fr_iimmed   0x8000,0x8000,fr12
417
        set_fr_iimmed   0x8000,0x8000,fr13
418
        cmqsubhss.p     fr10,fr10,fr14,cc7,1
419
        cmqsubhss       fr12,fr10,fr16,cc7,0
420
        test_fr_limmed  0x1111,0x1111,fr14
421
        test_fr_limmed  0x2222,0x2222,fr15
422
        test_fr_limmed  0x3333,0x3333,fr16
423
        test_fr_limmed  0x4444,0x4444,fr17
424
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is set
425
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
426
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
427
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
428
 
429
        pass

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