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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr550/] [mmachu.cgs] - Blame information for rev 26

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Line No. Rev Author Line
1 26 jlechner 
# frv testcase for mmachu $GRi,$GRj,$GRk
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# mach: all
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        .include "../testutils.inc"
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        start
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        .global mmachu
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mmachu:
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        set_fr_iimmed   3,2,fr7         ; multiply small numbers
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        set_fr_iimmed   2,3,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_immed  6,acc0
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        test_accg_immed         0,accg1
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        test_acc_immed  6,acc1
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        set_fr_iimmed   1,2,fr7         ; multiply by 1
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        set_fr_iimmed   2,1,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_immed  8,acc0
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        test_accg_immed         0,accg1
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        test_acc_immed  8,acc1
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        set_fr_iimmed   0,2,fr7         ; multiply by 0
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        set_fr_iimmed   2,0,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_immed  8,acc0
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        test_accg_immed         0,accg1
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        test_acc_immed  8,acc1
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        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
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        set_fr_iimmed   2,0x3fff,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_limmed 0x0000,0x8006,acc0
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        test_accg_immed         0,accg1
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        test_acc_limmed 0x0000,0x8006,acc1
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        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
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        set_fr_iimmed   2,0x4000,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_limmed 0x0001,0x0006,acc0
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        test_accg_immed         0,accg1
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        test_acc_limmed 0x0001,0x0006,acc1
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        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
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        set_fr_iimmed   2,0x8000,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_immed  0x00020006,acc0
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        test_accg_immed         0,accg1
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        test_acc_immed  0x00020006,acc1
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        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
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        set_fr_iimmed   0x7fff,0x7fff,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_immed  0x40010007,acc0
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        test_accg_immed         0,accg1
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        test_acc_immed  0x40010007,acc1
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        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
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        set_fr_iimmed   0x8000,0x8000,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         0,accg0
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        test_acc_limmed 0x8001,0x0007,acc0
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        test_accg_immed         0,accg1
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        test_acc_limmed 0x8001,0x0007,acc1
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        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
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        set_fr_iimmed   0xffff,0xffff,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        test_accg_immed         1,accg0
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        test_acc_limmed 0x7fff,0x0008,acc0
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        test_accg_immed         1,accg1
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        test_acc_limmed 0x7fff,0x0008,acc1
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        set_accg_immed  0xff,accg0              ; saturation
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        set_acc_immed   0xffffffff,acc0
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        set_accg_immed  0xff,accg1
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        set_acc_immed   0xffffffff,acc1
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        set_fr_iimmed   1,1,fr7
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        set_fr_iimmed   1,1,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
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        test_accg_immed         0xff,accg0
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        test_acc_limmed 0xffff,0xffff,acc0
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        test_accg_immed         0xff,accg1
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        test_acc_limmed 0xffff,0xffff,acc1
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        set_fr_iimmed   0xffff,0x0000,fr7
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        set_fr_iimmed   0xffff,0xffff,fr8
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        mmachu          fr7,fr8,acc0
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        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
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        test_accg_immed         0xff,accg0
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        test_acc_limmed 0xffff,0xffff,acc0
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        test_accg_immed         0xff,accg1
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        test_acc_limmed 0xffff,0xffff,acc1
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        pass

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