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# FRV testcase for icul $GRi
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global icul
icul:
        or_spr_immed    0xc8000000,hsr0 ; caches enabled -- copy-back mode
 
        ; preload and lock all the lines in set 0 of the insn cache
        set_gr_immed    0x70000,gr10
        set_bctrlr_0_0  gr10
        lock_insn_cache gr10
 
        inc_gr_immed    0x1000,gr10
        set_bctrlr_0_0  gr10
        lock_insn_cache gr10
 
        inc_gr_immed    0x1000,gr10
        set_bctrlr_0_0  gr10
        lock_insn_cache gr10
 
        inc_gr_immed    0x1000,gr10
        set_bctrlr_0_0  gr10
        lock_insn_cache gr10
 
        ; execute the pre-loaded insn
        set_gr_immed    0x70000,gr10
        calll           @(gr10,gr0)     ; should come right back
        inc_gr_immed    0x1000,gr10
        calll           @(gr10,gr0)     ; should come right back
        inc_gr_immed    0x1000,gr10
        calll           @(gr10,gr0)     ; should come right back
        inc_gr_immed    0x1000,gr10
        calll           @(gr10,gr0)     ; should come right back
 
        ; Now execute another insn which would have gone into set 0.
        inc_gr_immed    0x1000,gr10
        set_bctrlr_0_0  gr10
        set_spr_immed   128,lcr
        calll           @(gr10,gr0)     ; should come right back
 
        ; Now unlock one of the lines and do it again
        set_gr_immed    0x71000,gr10
        icul            gr10
        calll           @(gr10,gr0)     ; should come right back
 
        inc_gr_immed    0x3000,gr10
        calll           @(gr10,gr0)     ; should come right back
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# FRV testcase for icul $GRi`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global icul`
9			`icul:`
10			`or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode`
11
12			`; preload and lock all the lines in set 0 of the insn cache`
13			`set_gr_immed 0x70000,gr10`
14			`set_bctrlr_0_0 gr10`
15			`lock_insn_cache gr10`
16
17			`inc_gr_immed 0x1000,gr10`
18			`set_bctrlr_0_0 gr10`
19			`lock_insn_cache gr10`
20
21			`inc_gr_immed 0x1000,gr10`
22			`set_bctrlr_0_0 gr10`
23			`lock_insn_cache gr10`
24
25			`inc_gr_immed 0x1000,gr10`
26			`set_bctrlr_0_0 gr10`
27			`lock_insn_cache gr10`
28
29			`; execute the pre-loaded insn`
30			`set_gr_immed 0x70000,gr10`
31			`calll @(gr10,gr0) ; should come right back`
32			`inc_gr_immed 0x1000,gr10`
33			`calll @(gr10,gr0) ; should come right back`
34			`inc_gr_immed 0x1000,gr10`
35			`calll @(gr10,gr0) ; should come right back`
36			`inc_gr_immed 0x1000,gr10`
37			`calll @(gr10,gr0) ; should come right back`
38
39			`; Now execute another insn which would have gone into set 0.`
40			`inc_gr_immed 0x1000,gr10`
41			`set_bctrlr_0_0 gr10`
42			`set_spr_immed 128,lcr`
43			`calll @(gr10,gr0) ; should come right back`
44
45			`; Now unlock one of the lines and do it again`
46			`set_gr_immed 0x71000,gr10`
47			`icul gr10`
48			`calll @(gr10,gr0) ; should come right back`
49
50			`inc_gr_immed 0x3000,gr10`
51			`calll @(gr10,gr0) ; should come right back`
52
53			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [icul.cgs] - Blame information for rev 26