OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [stqf.pcgs] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jlechner 
# frv parallel testcase for stqf $GRk,@($GRi,$GRj)
2 
# mach: frv
3 
# as(frv): -mcpu=frv
4 
 
5 
        .include "testutils.inc"
6 
 
7 
        start
8 
 
9 
        .global stqf
10 
stqf:
11 
        set_mem_limmed  0xbeef,0xdead,sp
12 
        inc_gr_immed    -4,sp
13 
        set_mem_limmed  0xdead,0xbeef,sp
14 
        inc_gr_immed    -4,sp
15 
        set_mem_limmed  0xdead,0xdead,sp
16 
        inc_gr_immed    -4,sp
17 
        set_mem_limmed  0xbeef,0xbeef,sp
18 
        set_gr_immed    0,gr7
19 
        set_fr_iimmed   0xbeef,0xdead,fr8
20 
        set_fr_iimmed   0xdead,0xbeef,fr9
21 
        set_fr_iimmed   0xdead,0xdead,fr10
22 
        set_fr_iimmed   0xbeef,0xbeef,fr11
23 
        stqf            fr8,@(sp,gr7)           ; non-parallel
24 
        test_mem_limmed 0xbeef,0xdead,sp
25 
        inc_gr_immed    4,sp
26 
        test_mem_limmed 0xdead,0xbeef,sp
27 
        inc_gr_immed    4,sp
28 
        test_mem_limmed 0xdead,0xdead,sp
29 
        inc_gr_immed    4,sp
30 
        test_mem_limmed 0xbeef,0xbeef,sp
31 
 
32 
        set_mem_limmed  0xbeef,0xdead,sp
33 
        inc_gr_immed    -4,sp
34 
        set_mem_limmed  0xdead,0xbeef,sp
35 
        inc_gr_immed    -4,sp
36 
        set_mem_limmed  0xdead,0xdead,sp
37 
        inc_gr_immed    -4,sp
38 
        set_mem_limmed  0xbeef,0xbeef,sp
39 
        set_gr_immed    0,gr7
40 
        set_fr_iimmed   0xbeef,0xdead,fr8
41 
        set_fr_iimmed   0xdead,0xbeef,fr9
42 
        set_fr_iimmed   0xdead,0xdead,fr10
43 
        set_fr_iimmed   0xbeef,0xbeef,fr11
44 
        stqf.p          fr8,@(sp,gr7)           ; parallel
45 
        fnegs           fr8,fr8
46 
        ldqf            @(sp,gr7),fr12
47 
        test_mem_limmed 0xbeef,0xdead,sp        ; memory is set
48 
        inc_gr_immed    4,sp
49 
        test_mem_limmed 0xdead,0xbeef,sp
50 
        inc_gr_immed    4,sp
51 
        test_mem_limmed 0xdead,0xdead,sp
52 
        inc_gr_immed    4,sp
53 
        test_mem_limmed 0xbeef,0xbeef,sp
54 
        test_fr_iimmed  0xbeefdead,fr12
55 
        test_fr_iimmed  0xdeadbeef,fr13
56 
        test_fr_iimmed  0xdeaddead,fr14
57 
        test_fr_iimmed  0xbeefbeef,fr15
58 
 
59 
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.