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# frv testcase for tige $ICCi_2,$GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global tige
tige:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_psr_et      1
        set_spr_addr    ok0,lr
        set_icc         0x0 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok0:
        set_psr_et      1
        set_spr_addr    ok1,lr
        set_icc         0x1 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok1:
        set_spr_addr    bad,lr
        set_icc         0x2 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x3 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok4,lr
        set_icc         0x4 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok4:
        set_psr_et      1
        set_spr_addr    ok5,lr
        set_icc         0x5 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok5:
        set_psr_et      1
        set_spr_addr    bad,lr
        set_icc         0x6 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x7 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x8 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x9 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    oka,lr
        set_icc         0xa 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_psr_et      1
        set_spr_addr    okb,lr
        set_icc         0xb 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_spr_addr    bad,lr
        set_icc         0xc 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0xd 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    oke,lr
        set_icc         0xe 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oke:
        set_psr_et      1
        set_spr_addr    okf,lr
        set_icc         0xf 0
        tige            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for tige $ICCi_2,$GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global tige`
9			`tige:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_psr_et 1`
19			`set_spr_addr ok0,lr`
20			`set_icc 0x0 0`
21			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
22			`fail`
23			`ok0:`
24			`set_psr_et 1`
25			`set_spr_addr ok1,lr`
26			`set_icc 0x1 0`
27			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
28			`fail`
29			`ok1:`
30			`set_spr_addr bad,lr`
31			`set_icc 0x2 0`
32			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
33
34			`set_spr_addr bad,lr`
35			`set_icc 0x3 0`
36			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
37
38			`set_psr_et 1`
39			`set_spr_addr ok4,lr`
40			`set_icc 0x4 0`
41			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
42			`fail`
43			`ok4:`
44			`set_psr_et 1`
45			`set_spr_addr ok5,lr`
46			`set_icc 0x5 0`
47			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
48			`fail`
49			`ok5:`
50			`set_psr_et 1`
51			`set_spr_addr bad,lr`
52			`set_icc 0x6 0`
53			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
54
55			`set_spr_addr bad,lr`
56			`set_icc 0x7 0`
57			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
58
59			`set_spr_addr bad,lr`
60			`set_icc 0x8 0`
61			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
62
63			`set_spr_addr bad,lr`
64			`set_icc 0x9 0`
65			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
66
67			`set_psr_et 1`
68			`set_spr_addr oka,lr`
69			`set_icc 0xa 0`
70			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
71			`fail`
72			`oka:`
73			`set_psr_et 1`
74			`set_spr_addr okb,lr`
75			`set_icc 0xb 0`
76			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
77			`fail`
78			`okb:`
79			`set_spr_addr bad,lr`
80			`set_icc 0xc 0`
81			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
82
83			`set_spr_addr bad,lr`
84			`set_icc 0xd 0`
85			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
86
87			`set_psr_et 1`
88			`set_spr_addr oke,lr`
89			`set_icc 0xe 0`
90			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
91			`fail`
92			`oke:`
93			`set_psr_et 1`
94			`set_spr_addr okf,lr`
95			`set_icc 0xf 0`
96			`tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
97			`fail`
98			`okf:`
99			`pass`
100			`bad:`
101			`fail`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tige.cgs] - Blame information for rev 26