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# frv testcase for tira $GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global tira
tira:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_psr_et      1
        set_spr_addr    ok0,lr
        set_icc         0x0 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok0:
        set_psr_et      1
        set_spr_addr    ok1,lr
        set_icc         0x1 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok1:
        set_psr_et      1
        set_spr_addr    ok2,lr
        set_icc         0x2 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok2:
        set_psr_et      1
        set_spr_addr    ok3,lr
        set_icc         0x3 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok3:
        set_psr_et      1
        set_spr_addr    ok4,lr
        set_icc         0x4 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok4:
        set_psr_et      1
        set_spr_addr    ok5,lr
        set_icc         0x5 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok5:
        set_psr_et      1
        set_spr_addr    ok6,lr
        set_icc         0x6 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok6:
        set_psr_et      1
        set_spr_addr    ok7,lr
        set_icc         0x7 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok7:
        set_psr_et      1
        set_spr_addr    ok8,lr
        set_icc         0x8 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok8:
        set_psr_et      1
        set_spr_addr    ok9,lr
        set_icc         0x9 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
ok9:
        set_psr_et      1
        set_spr_addr    oka,lr
        set_icc         0xa 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_psr_et      1
        set_spr_addr    okb,lr
        set_icc         0xb 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_psr_et      1
        set_spr_addr    okc,lr
        set_icc         0xc 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
okc:
        set_psr_et      1
        set_spr_addr    okd,lr
        set_icc         0xd 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
okd:
        set_psr_et      1
        set_spr_addr    oke,lr
        set_icc         0xe 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
oke:
        set_psr_et      1
        set_spr_addr    okf,lr
        set_icc         0xf 0
        tira            gr7,4   ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for tira $GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global tira`
9			`tira:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_psr_et 1`
19			`set_spr_addr ok0,lr`
20			`set_icc 0x0 0`
21			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
22			`fail`
23			`ok0:`
24			`set_psr_et 1`
25			`set_spr_addr ok1,lr`
26			`set_icc 0x1 0`
27			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
28			`fail`
29			`ok1:`
30			`set_psr_et 1`
31			`set_spr_addr ok2,lr`
32			`set_icc 0x2 0`
33			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
34			`fail`
35			`ok2:`
36			`set_psr_et 1`
37			`set_spr_addr ok3,lr`
38			`set_icc 0x3 0`
39			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
40			`fail`
41			`ok3:`
42			`set_psr_et 1`
43			`set_spr_addr ok4,lr`
44			`set_icc 0x4 0`
45			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
46			`fail`
47			`ok4:`
48			`set_psr_et 1`
49			`set_spr_addr ok5,lr`
50			`set_icc 0x5 0`
51			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
52			`fail`
53			`ok5:`
54			`set_psr_et 1`
55			`set_spr_addr ok6,lr`
56			`set_icc 0x6 0`
57			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
58			`fail`
59			`ok6:`
60			`set_psr_et 1`
61			`set_spr_addr ok7,lr`
62			`set_icc 0x7 0`
63			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
64			`fail`
65			`ok7:`
66			`set_psr_et 1`
67			`set_spr_addr ok8,lr`
68			`set_icc 0x8 0`
69			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
70			`fail`
71			`ok8:`
72			`set_psr_et 1`
73			`set_spr_addr ok9,lr`
74			`set_icc 0x9 0`
75			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
76			`fail`
77			`ok9:`
78			`set_psr_et 1`
79			`set_spr_addr oka,lr`
80			`set_icc 0xa 0`
81			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
82			`fail`
83			`oka:`
84			`set_psr_et 1`
85			`set_spr_addr okb,lr`
86			`set_icc 0xb 0`
87			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
88			`fail`
89			`okb:`
90			`set_psr_et 1`
91			`set_spr_addr okc,lr`
92			`set_icc 0xc 0`
93			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
94			`fail`
95			`okc:`
96			`set_psr_et 1`
97			`set_spr_addr okd,lr`
98			`set_icc 0xd 0`
99			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
100			`fail`
101			`okd:`
102			`set_psr_et 1`
103			`set_spr_addr oke,lr`
104			`set_icc 0xe 0`
105			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
106			`fail`
107			`oke:`
108			`set_psr_et 1`
109			`set_spr_addr okf,lr`
110			`set_icc 0xf 0`
111			`tira gr7,4 ; should branch to tbr + (128 + 4)*16`
112			`fail`
113			`okf:`
114			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tira.cgs] - Blame information for rev 26