OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tls.cgs] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jlechner
# frv testcase for tls $ICCi_2,$GRi,$GRj
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global tls
9
tls:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_gr_immed    0,gr7
17
        set_gr_immed    4,gr8
18
 
19
        set_spr_addr    bad,lr
20
        set_icc         0x0 0
21
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
22
 
23
        set_psr_et      1
24
        set_spr_addr    ok1,lr
25
        set_icc         0x1 0
26
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
27
        fail
28
ok1:
29
        set_spr_addr    bad,lr
30
        set_icc         0x2 0
31
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
32
 
33
        set_psr_et      1
34
        set_spr_addr    ok3,lr
35
        set_icc         0x3 0
36
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
37
        fail
38
ok3:
39
        set_psr_et      1
40
        set_spr_addr    ok4,lr
41
        set_icc         0x4 0
42
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
43
        fail
44
ok4:
45
        set_psr_et      1
46
        set_spr_addr    ok5,lr
47
        set_icc         0x5 0
48
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
49
        fail
50
ok5:
51
        set_psr_et      1
52
        set_spr_addr    ok6,lr
53
        set_icc         0x6 0
54
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
55
        fail
56
ok6:
57
        set_psr_et      1
58
        set_spr_addr    ok7,lr
59
        set_icc         0x7 0
60
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
61
        fail
62
ok7:
63
        set_spr_addr    bad,lr
64
        set_icc         0x8 0
65
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
66
 
67
        set_psr_et      1
68
        set_spr_addr    ok9,lr
69
        set_icc         0x9 0
70
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
71
        fail
72
ok9:
73
        set_spr_addr    bad,lr
74
        set_icc         0xa 0
75
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
76
 
77
        set_psr_et      1
78
        set_spr_addr    okb,lr
79
        set_icc         0xb 0
80
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
81
        fail
82
okb:
83
        set_psr_et      1
84
        set_spr_addr    okc,lr
85
        set_icc         0xc 0
86
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
87
        fail
88
okc:
89
        set_psr_et      1
90
        set_spr_addr    okd,lr
91
        set_icc         0xd 0
92
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
93
        fail
94
okd:
95
        set_psr_et      1
96
        set_spr_addr    oke,lr
97
        set_icc         0xe 0
98
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
99
        fail
100
oke:
101
        set_psr_et      1
102
        set_spr_addr    okf,lr
103
        set_icc         0xf 0
104
        tls             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
105
        fail
106
okf:
107
        pass
108
bad:
109
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.