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# Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        # Instructions tested:
        # and.b #xx:8, rd       ;                     e rd   xxxxxxxx
        # and.b #xx:8, @erd     ;         7 d rd ???? e ???? xxxxxxxx
        # and.b #xx:8, @erd+    ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
        # and.b #xx:8, @erd-    ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
        # and.b #xx:8, @+erd    ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
        # and.b #xx:8, @-erd    ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
        # and.b rs, rd          ;                     1 6 rs rd
        # and.b reg8, @erd      ;         7 d rd ???? 1 6 rs ????
        # and.b reg8, @erd+     ;         0 1 7     9 8 rd 6 rs
        # and.b reg8, @erd-     ;         0 1 7     9 a rd 6 rs
        # and.b reg8, @+erd     ;         0 1 7     9 9 rd 6 rs
        # and.b reg8, @-erd     ;         0 1 7     9 b rd 6 rs
        #
        # andc #xx:8, ccr       ;         0 6 xxxxxxxx
        # andc #xx:8, exr       ; 0 1 4 1 0 6 xxxxxxxx
 
        # Coming soon:
        # ...
 
.data
pre_byte:       .byte 0
byte_dest:      .byte 0xa5
post_byte:      .byte 0
 
        start
 
and_b_imm8_reg8:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  and.b #xx:8,Rd
        and.b   #0xaa, r0l      ; Immediate 8-bit operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr16 0xa5a0 r0   ; and result:   a5 & aa
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
        test_h_gr32 0xa5a5a5a0 er0      ; and result:    a5 & aa
.endif
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8sx)
and_b_imm8_rdind:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b #xx:8,@eRd
        mov     #byte_dest, er0
        and.b   #0xaa:8, @er0   ; Immediate 8-bit src, reg indirect dst
;;;     .word   0x7d00
;;;     .word   0xe0aa
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 byte_dest, er0      ; er0 still contains address
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa0, r0l
        beq     .L1
        fail
.L1:
 
and_b_imm8_rdpostinc:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b #xx:8,@eRd+
        mov     #byte_dest, er0
        and.b   #0x55:8, @er0+  ; Immediate 8-bit src, reg post-incr dest
;;;     .word   0x0174
;;;     .word   0x6c08
;;;     .word   0xe055
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 post_byte, er0      ; er0 contains address plus one
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x05, r0l
        beq     .L2
        fail
.L2:
 
and_b_imm8_rdpostdec:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b #xx:8,@eRd-
        mov     #byte_dest, er0
        and.b   #0xaa:8, @er0-  ; Immediate 8-bit src, reg post-decr dest
;;;     .word   0x0176
;;;     .word   0x6c08
;;;     .word   0xe0aa
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 pre_byte, er0       ; er0 contains address minus one
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa0, r0l
        beq     .L3
        fail
.L3:
 
and_b_imm8_rdpreinc:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b #xx:8,@+eRd
        mov     #pre_byte, er0
        and.b   #0x55:8, @+er0  ; Immediate 8-bit src, reg pre-incr dest
;;;     .word   0x0175
;;;     .word   0x6c08
;;;     .word   0xe055
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 byte_dest, er0      ; er0 contains destination address 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x05, r0l
        beq     .L4
        fail
.L4:
 
and_b_imm8_rdpredec:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b #xx:8,@-eRd
        mov     #post_byte, er0
        and.b   #0xaa:8, @-er0  ; Immediate 8-bit src, reg pre-decr dest
;;;     .word   0x0177
;;;     .word   0x6c08
;;;     .word   0xe0aa
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 byte_dest, er0      ; er0 contains destination address 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa0, r0l
        beq     .L5
        fail
.L5:
 
.endif                          ; h8sx
 
and_b_reg8_reg8:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  and.b Rs,Rd
        mov.b   #0xaa, r0h
        and.b   r0h, r0l        ; Register operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr16 0xaaa0 r0   ; and result:   a5 & aa
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
        test_h_gr32 0xa5a5aaa0 er0      ; and result:   a5 & aa
.endif
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8sx)
and_b_reg8_rdind:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b rs8,@eRd      ; And to register indirect
        mov     #byte_dest, er0
        mov     #0x55, r1l
        and.b   r1l, @er0       ; reg8 src, reg indirect dest
;;;     .word   0x7d00
;;;     .word   0x1690
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 byte_dest er0       ; er0 still contains address
        test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x05, r0l
        beq     .L6
        fail
.L6:
 
and_b_reg8_rdpostinc:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b rs8,@eRd+     ; And to register post-incr
        mov     #byte_dest, er0
        mov     #0xaa, r1l
        and.b   r1l, @er0+      ; reg8 src, reg post-incr dest
;;;     .word   0x0179
;;;     .word   0x8069
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 post_byte er0       ; er0 contains address plus one
        test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa0, r0l
        beq     .L7
        fail
.L7:
 
and_b_reg8_rdpostdec:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b rs8,@eRd-     ; And to register post-decr
        mov     #byte_dest, er0
        mov     #0x55, r1l
        and.b   r1l, @er0-      ; reg8 src, reg post-decr dest
;;;     .word   0x0179
;;;     .word   0xa069
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 pre_byte er0        ; er0 contains address minus one
        test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x05, r0l
        beq     .L8
        fail
.L8:
 
and_b_reg8_rdpreinc:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b rs8,@+eRd     ; And to register post-incr
        mov     #pre_byte, er0
        mov     #0xaa, r1l
        and.b   r1l, @+er0      ; reg8 src, reg post-incr dest
;;;     .word   0x0179
;;;     .word   0x9069
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 byte_dest er0       ; er0 contains destination address 
        test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa0, r0l
        beq     .L9
        fail
.L9:
 
and_b_reg8_rdpredec:
        mov     #byte_dest, er0
        mov.b   #0xa5, r1l
        mov.b   r1l, @er0
 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  and.b rs8,@-eRd     ; And to register post-decr
        mov     #post_byte, er0
        mov     #0x55, r1l
        and.b   r1l, @-er0      ; reg8 src, reg post-decr dest
;;;     .word   0x0179
;;;     .word   0xb069
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 byte_dest er0       ; er0 contains destination address 
        test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the and to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x05, r0l
        beq     .L10
        fail
.L10:
.endif                          ; h8sx
 
andc_imm8_ccr:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  andc #xx:8,ccr
        set_ccr 0xff
 
        test_neg_set
        andc    #0xf7, ccr      ; Immediate 8-bit operand (neg flag)
        test_neg_clear
 
        test_zero_set
        andc    #0xfb, ccr      ; Immediate 8-bit operand (zero flag)
        test_zero_clear
 
        test_ovf_set
        andc    #0xfd, ccr      ; Immediate 8-bit operand (overflow flag)
        test_ovf_clear
 
        test_carry_set
        andc    #0xfe, ccr      ; Immediate 8-bit operand (carry flag)
        test_carry_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
andc_imm8_exr:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
 
        ldc     #0xff, exr
        stc     exr, r0l
        test_h_gr8 0x87, r0l
 
        ;;  andc #xx:8,exr
        set_ccr_zero
        andc    #0x7f, exr
        test_cc_clear
        stc     exr, r0l
        test_h_gr8 0x7, r0l
 
        andc    #0x3, exr
        stc     exr, r0l
        test_h_gr8 0x3, r0l
 
        andc    #0x1, exr
        stc     exr, r0l
        test_h_gr8 0x1, r0l
 
        andc    #0x0, exr
        stc     exr, r0l
        test_h_gr8 0x0, r0l
 
        test_h_gr32  0xa5a5a500 er0
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
.endif                          ; not h8300 or h8300h
 
        pass
 
        exit 0

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [andb.s] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jlechner	`# Hitachi H8 testcase 'and.b'`
2			`# mach(): all`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`# Instructions tested:`
14			`# and.b #xx:8, rd ; e rd xxxxxxxx`
15			`# and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx`
16			`# and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx`
17			`# and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx`
18			`# and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx`
19			`# and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx`
20			`# and.b rs, rd ; 1 6 rs rd`
21			`# and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????`
22			`# and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs`
23			`# and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs`
24			`# and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs`
25			`# and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs`
26			`#`
27			`# andc #xx:8, ccr ; 0 6 xxxxxxxx`
28			`# andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx`
29
30			`# Coming soon:`
31			`# ...`
32
33			`.data`
34			`pre_byte: .byte 0`
35			`byte_dest: .byte 0xa5`
36			`post_byte: .byte 0`
37
38			`start`
39
40			`and_b_imm8_reg8:`
41			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
42			`;; fixme set ccr`
43
44			`;; and.b #xx:8,Rd`
45			`and.b #0xaa, r0l ; Immediate 8-bit operand`
46
47			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
48			`test_h_gr16 0xa5a0 r0 ; and result: a5 & aa`
49			`.if (sim_cpu) ; non-zero means h8300h, s, or sx`
50			`test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa`
51			`.endif`
52			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
53			`test_gr_a5a5 2`
54			`test_gr_a5a5 3`
55			`test_gr_a5a5 4`
56			`test_gr_a5a5 5`
57			`test_gr_a5a5 6`
58			`test_gr_a5a5 7`
59
60			`.if (sim_cpu == h8sx)`
61			`and_b_imm8_rdind:`
62			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
63			`set_ccr_zero`
64
65			`;; and.b #xx:8,@eRd`
66			`mov #byte_dest, er0`
67			`and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst`
68			`;;; .word 0x7d00`
69			`;;; .word 0xe0aa`
70
71			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
72			`test_ovf_clear`
73			`test_zero_clear`
74			`test_neg_set`
75
76			`test_h_gr32 byte_dest, er0 ; er0 still contains address`
77			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
78			`test_gr_a5a5 2`
79			`test_gr_a5a5 3`
80			`test_gr_a5a5 4`
81			`test_gr_a5a5 5`
82			`test_gr_a5a5 6`
83			`test_gr_a5a5 7`
84
85			`;; Now check the result of the and to memory.`
86			`sub.b r0l, r0l`
87			`mov.b @byte_dest, r0l`
88			`cmp.b #0xa0, r0l`
89			`beq .L1`
90			`fail`
91			`.L1:`
92
93			`and_b_imm8_rdpostinc:`
94			`mov #byte_dest, er0`
95			`mov.b #0xa5, r1l`
96			`mov.b r1l, @er0`
97
98			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
99			`set_ccr_zero`
100
101			`;; and.b #xx:8,@eRd+`
102			`mov #byte_dest, er0`
103			`and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest`
104			`;;; .word 0x0174`
105			`;;; .word 0x6c08`
106			`;;; .word 0xe055`
107
108			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
109			`test_ovf_clear`
110			`test_zero_clear`
111			`test_neg_clear`
112
113			`test_h_gr32 post_byte, er0 ; er0 contains address plus one`
114			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
115			`test_gr_a5a5 2`
116			`test_gr_a5a5 3`
117			`test_gr_a5a5 4`
118			`test_gr_a5a5 5`
119			`test_gr_a5a5 6`
120			`test_gr_a5a5 7`
121
122			`;; Now check the result of the and to memory.`
123			`sub.b r0l, r0l`
124			`mov.b @byte_dest, r0l`
125			`cmp.b #0x05, r0l`
126			`beq .L2`
127			`fail`
128			`.L2:`
129
130			`and_b_imm8_rdpostdec:`
131			`mov #byte_dest, er0`
132			`mov.b #0xa5, r1l`
133			`mov.b r1l, @er0`
134
135			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
136			`set_ccr_zero`
137
138			`;; and.b #xx:8,@eRd-`
139			`mov #byte_dest, er0`
140			`and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest`
141			`;;; .word 0x0176`
142			`;;; .word 0x6c08`
143			`;;; .word 0xe0aa`
144
145			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
146			`test_ovf_clear`
147			`test_zero_clear`
148			`test_neg_set`
149
150			`test_h_gr32 pre_byte, er0 ; er0 contains address minus one`
151			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
152			`test_gr_a5a5 2`
153			`test_gr_a5a5 3`
154			`test_gr_a5a5 4`
155			`test_gr_a5a5 5`
156			`test_gr_a5a5 6`
157			`test_gr_a5a5 7`
158
159			`;; Now check the result of the and to memory.`
160			`sub.b r0l, r0l`
161			`mov.b @byte_dest, r0l`
162			`cmp.b #0xa0, r0l`
163			`beq .L3`
164			`fail`
165			`.L3:`
166
167			`and_b_imm8_rdpreinc:`
168			`mov #byte_dest, er0`
169			`mov.b #0xa5, r1l`
170			`mov.b r1l, @er0`
171
172			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
173			`set_ccr_zero`
174
175			`;; and.b #xx:8,@+eRd`
176			`mov #pre_byte, er0`
177			`and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest`
178			`;;; .word 0x0175`
179			`;;; .word 0x6c08`
180			`;;; .word 0xe055`
181
182			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
183			`test_ovf_clear`
184			`test_zero_clear`
185			`test_neg_clear`
186
187			`test_h_gr32 byte_dest, er0 ; er0 contains destination address`
188			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
189			`test_gr_a5a5 2`
190			`test_gr_a5a5 3`
191			`test_gr_a5a5 4`
192			`test_gr_a5a5 5`
193			`test_gr_a5a5 6`
194			`test_gr_a5a5 7`
195
196			`;; Now check the result of the and to memory.`
197			`sub.b r0l, r0l`
198			`mov.b @byte_dest, r0l`
199			`cmp.b #0x05, r0l`
200			`beq .L4`
201			`fail`
202			`.L4:`
203
204			`and_b_imm8_rdpredec:`
205			`mov #byte_dest, er0`
206			`mov.b #0xa5, r1l`
207			`mov.b r1l, @er0`
208
209			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
210			`set_ccr_zero`
211
212			`;; and.b #xx:8,@-eRd`
213			`mov #post_byte, er0`
214			`and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest`
215			`;;; .word 0x0177`
216			`;;; .word 0x6c08`
217			`;;; .word 0xe0aa`
218
219			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
220			`test_ovf_clear`
221			`test_zero_clear`
222			`test_neg_set`
223
224			`test_h_gr32 byte_dest, er0 ; er0 contains destination address`
225			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
226			`test_gr_a5a5 2`
227			`test_gr_a5a5 3`
228			`test_gr_a5a5 4`
229			`test_gr_a5a5 5`
230			`test_gr_a5a5 6`
231			`test_gr_a5a5 7`
232
233			`;; Now check the result of the and to memory.`
234			`sub.b r0l, r0l`
235			`mov.b @byte_dest, r0l`
236			`cmp.b #0xa0, r0l`
237			`beq .L5`
238			`fail`
239			`.L5:`
240
241			`.endif ; h8sx`
242
243			`and_b_reg8_reg8:`
244			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
245			`;; fixme set ccr`
246
247			`;; and.b Rs,Rd`
248			`mov.b #0xaa, r0h`
249			`and.b r0h, r0l ; Register operand`
250
251			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
252			`test_h_gr16 0xaaa0 r0 ; and result: a5 & aa`
253			`.if (sim_cpu) ; non-zero means h8300h, s, or sx`
254			`test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa`
255			`.endif`
256			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
257			`test_gr_a5a5 2`
258			`test_gr_a5a5 3`
259			`test_gr_a5a5 4`
260			`test_gr_a5a5 5`
261			`test_gr_a5a5 6`
262			`test_gr_a5a5 7`
263
264			`.if (sim_cpu == h8sx)`
265			`and_b_reg8_rdind:`
266			`mov #byte_dest, er0`
267			`mov.b #0xa5, r1l`
268			`mov.b r1l, @er0`
269
270			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
271			`set_ccr_zero`
272
273			`;; and.b rs8,@eRd ; And to register indirect`
274			`mov #byte_dest, er0`
275			`mov #0x55, r1l`
276			`and.b r1l, @er0 ; reg8 src, reg indirect dest`
277			`;;; .word 0x7d00`
278			`;;; .word 0x1690`
279
280			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
281			`test_ovf_clear`
282			`test_zero_clear`
283			`test_neg_clear`
284
285			`test_h_gr32 byte_dest er0 ; er0 still contains address`
286			`test_h_gr32 0xa5a5a555 er1 ; er1 has the test load`
287
288			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
289			`test_gr_a5a5 3`
290			`test_gr_a5a5 4`
291			`test_gr_a5a5 5`
292			`test_gr_a5a5 6`
293			`test_gr_a5a5 7`
294
295			`;; Now check the result of the and to memory.`
296			`sub.b r0l, r0l`
297			`mov.b @byte_dest, r0l`
298			`cmp.b #0x05, r0l`
299			`beq .L6`
300			`fail`
301			`.L6:`
302
303			`and_b_reg8_rdpostinc:`
304			`mov #byte_dest, er0`
305			`mov.b #0xa5, r1l`
306			`mov.b r1l, @er0`
307
308			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
309			`set_ccr_zero`
310
311			`;; and.b rs8,@eRd+ ; And to register post-incr`
312			`mov #byte_dest, er0`
313			`mov #0xaa, r1l`
314			`and.b r1l, @er0+ ; reg8 src, reg post-incr dest`
315			`;;; .word 0x0179`
316			`;;; .word 0x8069`
317
318			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
319			`test_ovf_clear`
320			`test_zero_clear`
321			`test_neg_set`
322
323			`test_h_gr32 post_byte er0 ; er0 contains address plus one`
324			`test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load`
325
326			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
327			`test_gr_a5a5 3`
328			`test_gr_a5a5 4`
329			`test_gr_a5a5 5`
330			`test_gr_a5a5 6`
331			`test_gr_a5a5 7`
332
333			`;; Now check the result of the and to memory.`
334			`sub.b r0l, r0l`
335			`mov.b @byte_dest, r0l`
336			`cmp.b #0xa0, r0l`
337			`beq .L7`
338			`fail`
339			`.L7:`
340
341			`and_b_reg8_rdpostdec:`
342			`mov #byte_dest, er0`
343			`mov.b #0xa5, r1l`
344			`mov.b r1l, @er0`
345
346			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
347			`set_ccr_zero`
348
349			`;; and.b rs8,@eRd- ; And to register post-decr`
350			`mov #byte_dest, er0`
351			`mov #0x55, r1l`
352			`and.b r1l, @er0- ; reg8 src, reg post-decr dest`
353			`;;; .word 0x0179`
354			`;;; .word 0xa069`
355
356			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
357			`test_ovf_clear`
358			`test_zero_clear`
359			`test_neg_clear`
360
361			`test_h_gr32 pre_byte er0 ; er0 contains address minus one`
362			`test_h_gr32 0xa5a5a555 er1 ; er1 has the test load`
363
364			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
365			`test_gr_a5a5 3`
366			`test_gr_a5a5 4`
367			`test_gr_a5a5 5`
368			`test_gr_a5a5 6`
369			`test_gr_a5a5 7`
370
371			`;; Now check the result of the and to memory.`
372			`sub.b r0l, r0l`
373			`mov.b @byte_dest, r0l`
374			`cmp.b #0x05, r0l`
375			`beq .L8`
376			`fail`
377			`.L8:`
378
379			`and_b_reg8_rdpreinc:`
380			`mov #byte_dest, er0`
381			`mov.b #0xa5, r1l`
382			`mov.b r1l, @er0`
383
384			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
385			`set_ccr_zero`
386
387			`;; and.b rs8,@+eRd ; And to register post-incr`
388			`mov #pre_byte, er0`
389			`mov #0xaa, r1l`
390			`and.b r1l, @+er0 ; reg8 src, reg post-incr dest`
391			`;;; .word 0x0179`
392			`;;; .word 0x9069`
393
394			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
395			`test_ovf_clear`
396			`test_zero_clear`
397			`test_neg_set`
398
399			`test_h_gr32 byte_dest er0 ; er0 contains destination address`
400			`test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load`
401
402			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
403			`test_gr_a5a5 3`
404			`test_gr_a5a5 4`
405			`test_gr_a5a5 5`
406			`test_gr_a5a5 6`
407			`test_gr_a5a5 7`
408
409			`;; Now check the result of the and to memory.`
410			`sub.b r0l, r0l`
411			`mov.b @byte_dest, r0l`
412			`cmp.b #0xa0, r0l`
413			`beq .L9`
414			`fail`
415			`.L9:`
416
417			`and_b_reg8_rdpredec:`
418			`mov #byte_dest, er0`
419			`mov.b #0xa5, r1l`
420			`mov.b r1l, @er0`
421
422			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
423			`set_ccr_zero`
424
425			`;; and.b rs8,@-eRd ; And to register post-decr`
426			`mov #post_byte, er0`
427			`mov #0x55, r1l`
428			`and.b r1l, @-er0 ; reg8 src, reg post-decr dest`
429			`;;; .word 0x0179`
430			`;;; .word 0xb069`
431
432			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
433			`test_ovf_clear`
434			`test_zero_clear`
435			`test_neg_clear`
436
437			`test_h_gr32 byte_dest er0 ; er0 contains destination address`
438			`test_h_gr32 0xa5a5a555 er1 ; er1 has the test load`
439
440			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
441			`test_gr_a5a5 3`
442			`test_gr_a5a5 4`
443			`test_gr_a5a5 5`
444			`test_gr_a5a5 6`
445			`test_gr_a5a5 7`
446
447			`;; Now check the result of the and to memory.`
448			`sub.b r0l, r0l`
449			`mov.b @byte_dest, r0l`
450			`cmp.b #0x05, r0l`
451			`beq .L10`
452			`fail`
453			`.L10:`
454			`.endif ; h8sx`
455
456			`andc_imm8_ccr:`
457			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
458			`set_ccr_zero`
459
460			`;; andc #xx:8,ccr`
461			`set_ccr 0xff`
462
463			`test_neg_set`
464			`andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)`
465			`test_neg_clear`
466
467			`test_zero_set`
468			`andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)`
469			`test_zero_clear`
470
471			`test_ovf_set`
472			`andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)`
473			`test_ovf_clear`
474
475			`test_carry_set`
476			`andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)`
477			`test_carry_clear`
478
479			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
480			`test_gr_a5a5 1`
481			`test_gr_a5a5 2`
482			`test_gr_a5a5 3`
483			`test_gr_a5a5 4`
484			`test_gr_a5a5 5`
485			`test_gr_a5a5 6`
486			`test_gr_a5a5 7`
487
488			`.if (sim_cpu == h8300s \|\| sim_cpu == h8sx) ; Earlier versions, no exr`
489			`andc_imm8_exr:`
490			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
491
492			`ldc #0xff, exr`
493			`stc exr, r0l`
494			`test_h_gr8 0x87, r0l`
495
496			`;; andc #xx:8,exr`
497			`set_ccr_zero`
498			`andc #0x7f, exr`
499			`test_cc_clear`
500			`stc exr, r0l`
501			`test_h_gr8 0x7, r0l`
502
503			`andc #0x3, exr`
504			`stc exr, r0l`
505			`test_h_gr8 0x3, r0l`
506
507			`andc #0x1, exr`
508			`stc exr, r0l`
509			`test_h_gr8 0x1, r0l`
510
511			`andc #0x0, exr`
512			`stc exr, r0l`
513			`test_h_gr8 0x0, r0l`
514
515			`test_h_gr32 0xa5a5a500 er0`
516			`test_gr_a5a5 1`
517			`test_gr_a5a5 2`
518			`test_gr_a5a5 3`
519			`test_gr_a5a5 4`
520			`test_gr_a5a5 5`
521			`test_gr_a5a5 6`
522			`test_gr_a5a5 7`
523			`.endif ; not h8300 or h8300h`
524
525			`pass`
526
527			`exit 0`