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# Hitachi H8 testcase 'ldm', 'stm'
# mach(): all
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
        .data
        .align 4
_stack: .long   0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0
        .long   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
        .long   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
        .long   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
_stack_top:
 
        start
 
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
stm_2reg:
        set_grs_a5a5
        mov     #_stack_top, er7
        mov     #2, er2
        mov     #3, er3
 
        set_ccr_zero
        stm     er2-er3, @-sp
        test_cc_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_h_gr32  2  er2
        test_h_gr32  3  er3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_h_gr32  _stack_top-8, er7
 
        mov     @_stack_top-4, er0
        cmp     #2, er0
        bne     fail1
 
        mov     @_stack_top-8, er0
        cmp     #3, er0
        bne     fail1
 
        mov     @_stack_top-12, er0
        cmp     #0, er0
        bne     fail1
 
stm_3reg:
        set_grs_a5a5
        mov     #_stack_top, er7
        mov     #4, er4
        mov     #5, er5
        mov     #6, er6
 
        set_ccr_zero
        stm     er4-er6, @-sp
        test_cc_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_h_gr32  4  er4
        test_h_gr32  5  er5
        test_h_gr32  6  er6
        test_h_gr32  _stack_top-12, er7
 
        mov     @_stack_top-4, er0
        cmp     #4, er0
        bne     fail1
 
        mov     @_stack_top-8, er0
        cmp     #5, er0
        bne     fail1
 
        mov     @_stack_top-12, er0
        cmp     #6, er0
        bne     fail1
 
        mov     @_stack_top-16, er0
        cmp     #0, er0
        bne     fail1
 
stm_4reg:
        set_grs_a5a5
        mov     #_stack_top, er7
        mov     #1, er0
        mov     #2, er1
        mov     #3, er2
        mov     #4, er3
 
        set_ccr_zero
        stm     er0-er3, @-sp
        test_cc_clear
 
        test_h_gr32  1  er0
        test_h_gr32  2  er1
        test_h_gr32  3  er2
        test_h_gr32  4  er3
        test_gr_a5a5 4          ; Make sure other general regs not disturbed
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_h_gr32  _stack_top-16, er7
 
        mov     @_stack_top-4, er0
        cmp     #1, er0
        bne     fail1
 
        mov     @_stack_top-8, er0
        cmp     #2, er0
        bne     fail1
 
        mov     @_stack_top-12, er0
        cmp     #3, er0
        bne     fail1
 
        mov     @_stack_top-16, er0
        cmp     #4, er0
        bne     fail1
 
        mov     @_stack_top-20, er0
        cmp     #0, er0
        bne     fail1
 
ldm_2reg:
        set_grs_a5a5
        mov     #_stack, er7
 
        set_ccr_zero
        ldm     @sp+, er2-er3
        test_cc_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_h_gr32  1  er2
        test_h_gr32  0   er3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_h_gr32  _stack+8, er7
 
ldm_3reg:
        set_grs_a5a5
        mov     #_stack+4, er7
 
        set_ccr_zero
        ldm     @sp+, er4-er6
        test_cc_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_h_gr32  3  er4
        test_h_gr32  2  er5
        test_h_gr32  1  er6
        test_h_gr32  _stack+16, er7
 
ldm_4reg:
        set_grs_a5a5
        mov     #_stack+4, er7
 
        set_ccr_zero
        ldm     @sp+, er0-er3
        test_cc_clear
 
        test_h_gr32  4  er0
        test_h_gr32  3  er1
        test_h_gr32  2  er2
        test_h_gr32  1  er3
        test_gr_a5a5 4          ; Make sure other general regs not disturbed
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_h_gr32  _stack+20, er7
.endif
 
pushpop:
        set_grs_a5a5
.if (sim_cpu == h8300)
        mov     #_stack_top, r7
        mov     #12, r1
        mov     #34, r2
        mov     #56, r3
        push    r1
        push    r2
        push    r3
        pop     r4
        pop     r5
        pop     r6
 
        test_gr_a5a5 0           ; Make sure other general _reg_ not disturbed
        test_h_gr16  12 r1
        test_h_gr16  34 r2
        test_h_gr16  56 r3
        test_h_gr16  56 r4
        test_h_gr16  34 r5
        test_h_gr16  12 r6
        mov     #_stack_top, r0
        cmp.w   r0, r7
        bne     fail1
.else
        mov     #_stack_top, er7
        mov     #12, er1
        mov     #34, er2
        mov     #56, er3
        push    er1
        push    er2
        push    er3
        pop     er4
        pop     er5
        pop     er6
 
        test_gr_a5a5 0           ; Make sure other general _reg_ not disturbed
        test_h_gr32  12 er1
        test_h_gr32  34 er2
        test_h_gr32  56 er3
        test_h_gr32  56 er4
        test_h_gr32  34 er5
        test_h_gr32  12 er6
        test_h_gr32  _stack_top, er7
.endif
 
        pass
 
        exit 0
 
fail1:  fail

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [ldm.s] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jlechner	`# Hitachi H8 testcase 'ldm', 'stm'`
2			`# mach(): all`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12			`.data`
13			`.align 4`
14			`_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0`
15			`.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0`
16			`.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0`
17			`.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0`
18			`_stack_top:`
19
20			`start`
21
22			`.if (sim_cpu == h8300s \|\| sim_cpu == h8sx) ; Earlier versions, no exr`
23			`stm_2reg:`
24			`set_grs_a5a5`
25			`mov #_stack_top, er7`
26			`mov #2, er2`
27			`mov #3, er3`
28
29			`set_ccr_zero`
30			`stm er2-er3, @-sp`
31			`test_cc_clear`
32
33			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
34			`test_gr_a5a5 1`
35			`test_h_gr32 2 er2`
36			`test_h_gr32 3 er3`
37			`test_gr_a5a5 4`
38			`test_gr_a5a5 5`
39			`test_gr_a5a5 6`
40			`test_h_gr32 _stack_top-8, er7`
41
42			`mov @_stack_top-4, er0`
43			`cmp #2, er0`
44			`bne fail1`
45
46			`mov @_stack_top-8, er0`
47			`cmp #3, er0`
48			`bne fail1`
49
50			`mov @_stack_top-12, er0`
51			`cmp #0, er0`
52			`bne fail1`
53
54			`stm_3reg:`
55			`set_grs_a5a5`
56			`mov #_stack_top, er7`
57			`mov #4, er4`
58			`mov #5, er5`
59			`mov #6, er6`
60
61			`set_ccr_zero`
62			`stm er4-er6, @-sp`
63			`test_cc_clear`
64
65			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
66			`test_gr_a5a5 1`
67			`test_gr_a5a5 2`
68			`test_gr_a5a5 3`
69			`test_h_gr32 4 er4`
70			`test_h_gr32 5 er5`
71			`test_h_gr32 6 er6`
72			`test_h_gr32 _stack_top-12, er7`
73
74			`mov @_stack_top-4, er0`
75			`cmp #4, er0`
76			`bne fail1`
77
78			`mov @_stack_top-8, er0`
79			`cmp #5, er0`
80			`bne fail1`
81
82			`mov @_stack_top-12, er0`
83			`cmp #6, er0`
84			`bne fail1`
85
86			`mov @_stack_top-16, er0`
87			`cmp #0, er0`
88			`bne fail1`
89
90			`stm_4reg:`
91			`set_grs_a5a5`
92			`mov #_stack_top, er7`
93			`mov #1, er0`
94			`mov #2, er1`
95			`mov #3, er2`
96			`mov #4, er3`
97
98			`set_ccr_zero`
99			`stm er0-er3, @-sp`
100			`test_cc_clear`
101
102			`test_h_gr32 1 er0`
103			`test_h_gr32 2 er1`
104			`test_h_gr32 3 er2`
105			`test_h_gr32 4 er3`
106			`test_gr_a5a5 4 ; Make sure other general regs not disturbed`
107			`test_gr_a5a5 5`
108			`test_gr_a5a5 6`
109			`test_h_gr32 _stack_top-16, er7`
110
111			`mov @_stack_top-4, er0`
112			`cmp #1, er0`
113			`bne fail1`
114
115			`mov @_stack_top-8, er0`
116			`cmp #2, er0`
117			`bne fail1`
118
119			`mov @_stack_top-12, er0`
120			`cmp #3, er0`
121			`bne fail1`
122
123			`mov @_stack_top-16, er0`
124			`cmp #4, er0`
125			`bne fail1`
126
127			`mov @_stack_top-20, er0`
128			`cmp #0, er0`
129			`bne fail1`
130
131			`ldm_2reg:`
132			`set_grs_a5a5`
133			`mov #_stack, er7`
134
135			`set_ccr_zero`
136			`ldm @sp+, er2-er3`
137			`test_cc_clear`
138
139			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
140			`test_gr_a5a5 1`
141			`test_h_gr32 1 er2`
142			`test_h_gr32 0 er3`
143			`test_gr_a5a5 4`
144			`test_gr_a5a5 5`
145			`test_gr_a5a5 6`
146			`test_h_gr32 _stack+8, er7`
147
148			`ldm_3reg:`
149			`set_grs_a5a5`
150			`mov #_stack+4, er7`
151
152			`set_ccr_zero`
153			`ldm @sp+, er4-er6`
154			`test_cc_clear`
155
156			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
157			`test_gr_a5a5 1`
158			`test_gr_a5a5 2`
159			`test_gr_a5a5 3`
160			`test_h_gr32 3 er4`
161			`test_h_gr32 2 er5`
162			`test_h_gr32 1 er6`
163			`test_h_gr32 _stack+16, er7`
164
165			`ldm_4reg:`
166			`set_grs_a5a5`
167			`mov #_stack+4, er7`
168
169			`set_ccr_zero`
170			`ldm @sp+, er0-er3`
171			`test_cc_clear`
172
173			`test_h_gr32 4 er0`
174			`test_h_gr32 3 er1`
175			`test_h_gr32 2 er2`
176			`test_h_gr32 1 er3`
177			`test_gr_a5a5 4 ; Make sure other general regs not disturbed`
178			`test_gr_a5a5 5`
179			`test_gr_a5a5 6`
180			`test_h_gr32 _stack+20, er7`
181			`.endif`
182
183			`pushpop:`
184			`set_grs_a5a5`
185			`.if (sim_cpu == h8300)`
186			`mov #_stack_top, r7`
187			`mov #12, r1`
188			`mov #34, r2`
189			`mov #56, r3`
190			`push r1`
191			`push r2`
192			`push r3`
193			`pop r4`
194			`pop r5`
195			`pop r6`
196
197			`test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed`
198			`test_h_gr16 12 r1`
199			`test_h_gr16 34 r2`
200			`test_h_gr16 56 r3`
201			`test_h_gr16 56 r4`
202			`test_h_gr16 34 r5`
203			`test_h_gr16 12 r6`
204			`mov #_stack_top, r0`
205			`cmp.w r0, r7`
206			`bne fail1`
207			`.else`
208			`mov #_stack_top, er7`
209			`mov #12, er1`
210			`mov #34, er2`
211			`mov #56, er3`
212			`push er1`
213			`push er2`
214			`push er3`
215			`pop er4`
216			`pop er5`
217			`pop er6`
218
219			`test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed`
220			`test_h_gr32 12 er1`
221			`test_h_gr32 34 er2`
222			`test_h_gr32 56 er3`
223			`test_h_gr32 56 er4`
224			`test_h_gr32 34 er5`
225			`test_h_gr32 12 er6`
226			`test_h_gr32 _stack_top, er7`
227			`.endif`
228
229			`pass`
230
231			`exit 0`
232
233			`fail1: fail`