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# sh testcase for fdiv
# mach: sh
# as(sh):       -defsym sim_cpu=0
 
        .include "testutils.inc"
 
        start
fdiv_single:
        # Single test
        set_grs_a5a5
        set_fprs_a5a5
        single_prec
        # 1.0 / 0.0 should be INF
        # (and not crash the sim).
        fldi0   fr0
        fldi1   fr1
        fdiv    fr0, fr1
        assert_fpreg_x  0x7f800000, fr1
 
        # 0.0 / 1.0 == 0.0.
        fldi0   fr0
        fldi1   fr1
        fdiv    fr1, fr0
        assert_fpreg_x  0, fr0
 
        # 2.0 / 1.0 == 2.0.
        fldi1   fr1
        fldi1   fr2
        fadd    fr2, fr2
        fdiv    fr1, fr2
        assert_fpreg_i  2, fr2
 
        # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
        fldi1   fr1
        fldi1   fr2
        fadd    fr2, fr2
        fdiv    fr2, fr1
        # fr1 should contain 0.5.
        fadd    fr1, fr1
        assert_fpreg_i  1, fr1
        test_grs_a5a5
        assert_fpreg_i  2, fr2
        test_fpr_a5a5   fr3
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
fdiv_double:
        # Double test
        set_grs_a5a5
        set_fprs_a5a5
        # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
        fldi1   fr1
        fldi1   fr2
        # This add must be in single precision.  The rest must be in double.
        fadd    fr2, fr2
        double_prec
        _s2d    fr1, dr0
        _s2d    fr2, dr2
        fdiv    dr2, dr0
        # dr0 should contain 0.5.
        # double it, expect 1.0.
        fadd    dr0, dr0
        assert_dpreg_i  1, dr0
        assert_dpreg_i  2, dr2
        test_grs_a5a5
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
        pass
        exit 0
 

Line No.	Rev	Author	Line
1	26	jlechner	`# sh testcase for fdiv`
2			`# mach: sh`
3			`# as(sh): -defsym sim_cpu=0`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`fdiv_single:`
9			`# Single test`
10			`set_grs_a5a5`
11			`set_fprs_a5a5`
12			`single_prec`
13			`# 1.0 / 0.0 should be INF`
14			`# (and not crash the sim).`
15			`fldi0 fr0`
16			`fldi1 fr1`
17			`fdiv fr0, fr1`
18			`assert_fpreg_x 0x7f800000, fr1`
19
20			`# 0.0 / 1.0 == 0.0.`
21			`fldi0 fr0`
22			`fldi1 fr1`
23			`fdiv fr1, fr0`
24			`assert_fpreg_x 0, fr0`
25
26			`# 2.0 / 1.0 == 2.0.`
27			`fldi1 fr1`
28			`fldi1 fr2`
29			`fadd fr2, fr2`
30			`fdiv fr1, fr2`
31			`assert_fpreg_i 2, fr2`
32
33			`# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.`
34			`fldi1 fr1`
35			`fldi1 fr2`
36			`fadd fr2, fr2`
37			`fdiv fr2, fr1`
38			`# fr1 should contain 0.5.`
39			`fadd fr1, fr1`
40			`assert_fpreg_i 1, fr1`
41			`test_grs_a5a5`
42			`assert_fpreg_i 2, fr2`
43			`test_fpr_a5a5 fr3`
44			`test_fpr_a5a5 fr4`
45			`test_fpr_a5a5 fr5`
46			`test_fpr_a5a5 fr6`
47			`test_fpr_a5a5 fr7`
48			`test_fpr_a5a5 fr8`
49			`test_fpr_a5a5 fr9`
50			`test_fpr_a5a5 fr10`
51			`test_fpr_a5a5 fr11`
52			`test_fpr_a5a5 fr12`
53			`test_fpr_a5a5 fr13`
54			`test_fpr_a5a5 fr14`
55			`test_fpr_a5a5 fr15`
56
57			`fdiv_double:`
58			`# Double test`
59			`set_grs_a5a5`
60			`set_fprs_a5a5`
61			`# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.`
62			`fldi1 fr1`
63			`fldi1 fr2`
64			`# This add must be in single precision. The rest must be in double.`
65			`fadd fr2, fr2`
66			`double_prec`
67			`_s2d fr1, dr0`
68			`_s2d fr2, dr2`
69			`fdiv dr2, dr0`
70			`# dr0 should contain 0.5.`
71			`# double it, expect 1.0.`
72			`fadd dr0, dr0`
73			`assert_dpreg_i 1, dr0`
74			`assert_dpreg_i 2, dr2`
75			`test_grs_a5a5`
76			`test_fpr_a5a5 fr4`
77			`test_fpr_a5a5 fr5`
78			`test_fpr_a5a5 fr6`
79			`test_fpr_a5a5 fr7`
80			`test_fpr_a5a5 fr8`
81			`test_fpr_a5a5 fr9`
82			`test_fpr_a5a5 fr10`
83			`test_fpr_a5a5 fr11`
84			`test_fpr_a5a5 fr12`
85			`test_fpr_a5a5 fr13`
86			`test_fpr_a5a5 fr14`
87			`test_fpr_a5a5 fr15`
88
89			`pass`
90			`exit 0`
91

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fdiv.s] - Blame information for rev 26