OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [shll2.s] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jlechner 
# sh testcase for shll2
2 
# mach: all
3 
# as(sh):       -defsym sim_cpu=0
4 
# as(shdsp):    -defsym sim_cpu=1 -dsp
5 
 
6 
        .include "testutils.inc"
7 
 
8 
        start
9 
 
10 
shll2:
11 
        set_grs_a5a5
12 
        mov #1, r1
13 
        shll2 r1
14 
        assertreg 4, r1
15 
        shll2 r1
16 
        assertreg 16, r1
17 
        shll2 r1
18 
        assertreg 64, r1
19 
        shll2 r1
20 
        assertreg 0x100, r1
21 
        shll2 r1
22 
        assertreg 0x400, r1
23 
        shll2 r1
24 
        assertreg 0x1000, r1
25 
        shll2 r1
26 
        assertreg 0x4000, r1
27 
        shll2 r1
28 
        assertreg 0x10000, r1
29 
        shll2 r1
30 
        assertreg 0x40000, r1
31 
        shll2 r1
32 
        assertreg 0x100000, r1
33 
        shll2 r1
34 
        assertreg 0x400000, r1
35 
        shll2 r1
36 
        assertreg 0x1000000, r1
37 
        shll2 r1
38 
        assertreg 0x4000000, r1
39 
        shll2 r1
40 
        assertreg 0x10000000, r1
41 
        shll2 r1
42 
        assertreg 0x40000000, r1
43 
        shll2 r1
44 
        assertreg 0, r1
45 
 
46 
        set_greg 0xa5a5a5a5, r1
47 
        test_grs_a5a5
48 
 
49 
        pass
50 
        exit 0
51 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.