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# v850 divh
# mach: all
 
        .include "testutils.inc"
 
# Regular division - check signs
 
        seti    6, r1
        seti    45, r2
        divh    r1, r2
 
        flags   0
        reg     r1, 6
        reg     r2, 7
 
        seti    -6, r1
        seti    45, r2
        divh    r1, r2
 
        flags   s
        reg     r1, -6
        reg     r2, -7
 
        seti    6, r1
        seti    -45, r2
        divh    r1, r2
 
        flags   s
        reg     r1, 6
        reg     r2, -7
 
        seti    -6, r1
        seti    -45, r2
        divh    r1, r2
 
        flags   0
        reg     r1, -6
        reg     r2, 7
 
# Only the lower half of the dividend is used
 
        seti    0x0000fffa, r1
        seti    -45, r2
        divh    r1, r2
 
        flags   0
        reg     r1, 0x0000fffa
        reg     r2, 7
 
# If the data is divhided by zero, OV=1 and the quotient is undefined.
# According to NEC, the S and Z flags, and the output registers, are
# unchanged.
 
        noflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        divh    r1, r2
 
        flags   v
        reg     r2, 45
 
        allflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        divh    r1, r2
 
        flags   sat + c + v + s + z
        reg     r2, 45
 
# Zero / (N!=0) => normal
 
        noflags
        seti    45, r1
        seti    0, r2
        seti    67, r3
        divh    r1, r2
 
        flags   z
        reg     r1, 45
        reg     r2, 0
 
# Test for regular overflow
 
        noflags
        seti    -1, r1
        seti    0x80000000, r2
        divh    r1, r2
 
        flags   v + s
        reg     r1, -1
        reg     r2, 0x80000000
 
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# v850 divh`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`# Regular division - check signs`
7
8			`seti 6, r1`
9			`seti 45, r2`
10			`divh r1, r2`
11
12			`flags 0`
13			`reg r1, 6`
14			`reg r2, 7`
15
16			`seti -6, r1`
17			`seti 45, r2`
18			`divh r1, r2`
19
20			`flags s`
21			`reg r1, -6`
22			`reg r2, -7`
23
24			`seti 6, r1`
25			`seti -45, r2`
26			`divh r1, r2`
27
28			`flags s`
29			`reg r1, 6`
30			`reg r2, -7`
31
32			`seti -6, r1`
33			`seti -45, r2`
34			`divh r1, r2`
35
36			`flags 0`
37			`reg r1, -6`
38			`reg r2, 7`
39
40			`# Only the lower half of the dividend is used`
41
42			`seti 0x0000fffa, r1`
43			`seti -45, r2`
44			`divh r1, r2`
45
46			`flags 0`
47			`reg r1, 0x0000fffa`
48			`reg r2, 7`
49
50			`# If the data is divhided by zero, OV=1 and the quotient is undefined.`
51			`# According to NEC, the S and Z flags, and the output registers, are`
52			`# unchanged.`
53
54			`noflags`
55			`seti 0, r1`
56			`seti 45, r2`
57			`seti 67, r3`
58			`divh r1, r2`
59
60			`flags v`
61			`reg r2, 45`
62
63			`allflags`
64			`seti 0, r1`
65			`seti 45, r2`
66			`seti 67, r3`
67			`divh r1, r2`
68
69			`flags sat + c + v + s + z`
70			`reg r2, 45`
71
72			`# Zero / (N!=0) => normal`
73
74			`noflags`
75			`seti 45, r1`
76			`seti 0, r2`
77			`seti 67, r3`
78			`divh r1, r2`
79
80			`flags z`
81			`reg r1, 45`
82			`reg r2, 0`
83
84			`# Test for regular overflow`
85
86			`noflags`
87			`seti -1, r1`
88			`seti 0x80000000, r2`
89			`divh r1, r2`
90
91			`flags v + s`
92			`reg r1, -1`
93			`reg r2, 0x80000000`
94
95
96			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [v850/] [divh.cgs] - Blame information for rev 26