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# v850 divu
# mach: v850e
# as(v850e): -mv850e
 
        .include "testutils.inc"
 
        seti    6, r1
        seti    45, r2
        divu    r1, r2, r3
 
        flags   0
        reg     r1, 6
        reg     r2, 7
        reg     r3, 3
 
        seti    4, r1
        seti    0x40000000, r2
        divu    r1, r2, r3
 
        flags   0
        reg     r1, 4
        reg     r2, 0x10000000
        reg     r3, 0
 
# Only the lower half of the dividend is used
 
        seti    0x00010006, r1
        seti    45, r2
        divhu   r1, r2, r3
 
        flags   0
        reg     r1, 0x00010006
        reg     r2, 7
        reg     r3, 3
 
# If the data is divided by zero, OV=1 and the quotient is undefined.
# According to NEC, the S and Z flags, and the output registers, are
# unchanged.
 
        noflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        divu    r1, r2, r3
 
        flags   v
        reg     r2, 45
        reg     r3, 67
 
        allflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        divu    r1, r2, r3
 
        flags   sat + c + v + s + z
        reg     r2, 45
        reg     r3, 67
 
# Zero / (N!=0) => normal
 
        noflags
        seti    45, r1
        seti    0, r2
        seti    67, r3
        divu    r1, r2, r3
 
        flags   z
        reg     r1, 45
        reg     r2, 0
        reg     r3, 0
 
# The Z flag is based on the quotient, not the remainder
 
        noflags
        seti    45, r1
        seti    16, r2
        divu    r1, r2, r3
 
        flags   z
        reg     r2, 0
        reg     r3, 16
 
# If the quot and rem registers are the same, the remainder is stored.
 
        seti    6, r1
        seti    45, r2
        divu    r1, r2, r2
 
        flags   0
        reg     r1, 6
        reg     r2, 3
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# v850 divu`
2			`# mach: v850e`
3			`# as(v850e): -mv850e`
4
5			`.include "testutils.inc"`
6
7			`seti 6, r1`
8			`seti 45, r2`
9			`divu r1, r2, r3`
10
11			`flags 0`
12			`reg r1, 6`
13			`reg r2, 7`
14			`reg r3, 3`
15
16			`seti 4, r1`
17			`seti 0x40000000, r2`
18			`divu r1, r2, r3`
19
20			`flags 0`
21			`reg r1, 4`
22			`reg r2, 0x10000000`
23			`reg r3, 0`
24
25			`# Only the lower half of the dividend is used`
26
27			`seti 0x00010006, r1`
28			`seti 45, r2`
29			`divhu r1, r2, r3`
30
31			`flags 0`
32			`reg r1, 0x00010006`
33			`reg r2, 7`
34			`reg r3, 3`
35
36			`# If the data is divided by zero, OV=1 and the quotient is undefined.`
37			`# According to NEC, the S and Z flags, and the output registers, are`
38			`# unchanged.`
39
40			`noflags`
41			`seti 0, r1`
42			`seti 45, r2`
43			`seti 67, r3`
44			`divu r1, r2, r3`
45
46			`flags v`
47			`reg r2, 45`
48			`reg r3, 67`
49
50			`allflags`
51			`seti 0, r1`
52			`seti 45, r2`
53			`seti 67, r3`
54			`divu r1, r2, r3`
55
56			`flags sat + c + v + s + z`
57			`reg r2, 45`
58			`reg r3, 67`
59
60			`# Zero / (N!=0) => normal`
61
62			`noflags`
63			`seti 45, r1`
64			`seti 0, r2`
65			`seti 67, r3`
66			`divu r1, r2, r3`
67
68			`flags z`
69			`reg r1, 45`
70			`reg r2, 0`
71			`reg r3, 0`
72
73			`# The Z flag is based on the quotient, not the remainder`
74
75			`noflags`
76			`seti 45, r1`
77			`seti 16, r2`
78			`divu r1, r2, r3`
79
80			`flags z`
81			`reg r2, 0`
82			`reg r3, 16`
83
84			`# If the quot and rem registers are the same, the remainder is stored.`
85
86			`seti 6, r1`
87			`seti 45, r2`
88			`divu r1, r2, r2`
89
90			`flags 0`
91			`reg r1, 6`
92			`reg r2, 3`
93
94			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [v850/] [divhu.cgs] - Blame information for rev 26