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[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [edge_detect_tb.sv] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// WISHBONE SD Card Controller IP Core                          ////
////                                                              ////
//// edge_detect_tb.sv                                            ////
////                                                              ////
//// This file is part of the WISHBONE SD Card                    ////
//// Controller IP Core project                                   ////
//// http://opencores.org/project,sd_card_controller              ////
////                                                              ////
//// Description                                                  ////
//// testbench for edge_detect module                             ////
////                                                              ////
//// Author(s):                                                   ////
////     - Marek Czerski, ma.czerski@gmail.com                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module edge_detect_tb();
 
parameter TCLK = 20; // 50 MHz -> timescale 1ns
 
reg rst;
reg clk;
reg sig;
wire rise;
wire fall;
 
edge_detect edge_detect_dut(
    .rst(rst),
    .clk(clk),
    .sig(sig),
    .rise(rise),
    .fall(fall)
);
 
// Generating clk clock
always
begin
    clk=0;
    forever #(TCLK/2) clk = ~clk;
end
 
initial
begin
    rst = 1;
    sig = 0;
 
    #(3.2*TCLK);
    rst = 0;
 
    $display("edge_detect_tb start ...");
 
    //one cycle sig
    sig = 1;
    #TCLK;
    assert(rise == 1);
    assert(fall == 0);
 
    sig = 0;
    #TCLK;
    assert(rise == 0);
    assert(fall == 1);
 
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
 
    //multiple cycles sig
    sig = 1;
    #TCLK;
    assert(rise == 1);
    assert(fall == 0);
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
 
    sig = 0;
    #TCLK;
    assert(rise == 0);
    assert(fall == 1);
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
    #TCLK;
    assert(rise == 0);
    assert(fall == 0);
 
    #(10*TCLK) $display("edge_detect_tb finish ...");
    $finish;
 
end
 
endmodule

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE SD Card Controller IP Core ////`
4			`//// ////`
5			`//// edge_detect_tb.sv ////`
6			`//// ////`
7			`//// This file is part of the WISHBONE SD Card ////`
8			`//// Controller IP Core project ////`
9	8	rozpruwacz	`//// http://opencores.org/project,sd_card_controller ////`
10	3	rozpruwacz	`//// ////`
11			`//// Description ////`
12			`//// testbench for edge_detect module ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Marek Czerski, ma.czerski@gmail.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2013 Authors ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`module edge_detect_tb();`
45
46			`parameter TCLK = 20; // 50 MHz -> timescale 1ns`
47
48			`reg rst;`
49			`reg clk;`
50			`reg sig;`
51			`wire rise;`
52			`wire fall;`
53
54			`edge_detect edge_detect_dut(`
55			`.rst(rst),`
56			`.clk(clk),`
57			`.sig(sig),`
58			`.rise(rise),`
59			`.fall(fall)`
60			`);`
61
62			`// Generating clk clock`
63			`always`
64			`begin`
65			`clk=0;`
66			`forever #(TCLK/2) clk = ~clk;`
67			`end`
68
69			`initial`
70			`begin`
71			`rst = 1;`
72			`sig = 0;`
73
74			`#(3.2*TCLK);`
75			`rst = 0;`
76
77			`$display("edge_detect_tb start ...");`
78
79			`//one cycle sig`
80			`sig = 1;`
81			`#TCLK;`
82			`assert(rise == 1);`
83			`assert(fall == 0);`
84
85			`sig = 0;`
86			`#TCLK;`
87			`assert(rise == 0);`
88			`assert(fall == 1);`
89
90			`#TCLK;`
91			`assert(rise == 0);`
92			`assert(fall == 0);`
93			`#TCLK;`
94			`assert(rise == 0);`
95			`assert(fall == 0);`
96
97			`//multiple cycles sig`
98			`sig = 1;`
99			`#TCLK;`
100			`assert(rise == 1);`
101			`assert(fall == 0);`
102			`#TCLK;`
103			`assert(rise == 0);`
104			`assert(fall == 0);`
105			`#TCLK;`
106			`assert(rise == 0);`
107			`assert(fall == 0);`
108
109			`sig = 0;`
110			`#TCLK;`
111			`assert(rise == 0);`
112			`assert(fall == 1);`
113			`#TCLK;`
114			`assert(rise == 0);`
115			`assert(fall == 0);`
116			`#TCLK;`
117			`assert(rise == 0);`
118			`assert(fall == 0);`
119
120			`#(10*TCLK) $display("edge_detect_tb finish ...");`
121			`$finish;`
122
123			`end`
124
125			`endmodule`

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[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [edge_detect_tb.sv] - Blame information for rev 8