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[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [sd_cmd_master_tb.sv] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// WISHBONE SD Card Controller IP Core                          ////
////                                                              ////
//// sd_cmd_master_tb.sv                                          ////
////                                                              ////
//// This file is part of the WISHBONE SD Card                    ////
//// Controller IP Core project                                   ////
//// http://www.opencores.org/cores/xxx/                          ////
////                                                              ////
//// Description                                                  ////
//// testbench for sd_cmd_master module                           ////
////                                                              ////
//// Author(s):                                                   ////
////     - Marek Czerski, ma.czerski@gmail.com                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "sd_defines.h"
 
module sd_cmd_master_tb();
 
parameter SD_TCLK = 20; // 50 MHz -> timescale 1ns
 
reg sd_clk;
reg rst;
reg start_i;
reg int_status_rst_i;
wire [1:0] setting_o;
reg start_xfr_o;
wire go_idle_o;
wire [39:0] cmd_o;
reg [119:0] response_i;
reg crc_ok_i;
reg index_ok_i;
reg finish_i;
reg busy_i;
reg [31:0] argument_i;
reg [13:0] command_i;
reg [15:0] timeout_i;
wire [`INT_CMD_SIZE-1:0] int_status_o;
wire [31:0] response_0_o;
wire [31:0] response_1_o;
wire [31:0] response_2_o;
wire [31:0] response_3_o;
 
sd_cmd_master sd_cmd_master_dut(
           .sd_clk(sd_clk),
           .rst(rst),
           .start_i(start_i),
           .int_status_rst_i(int_status_rst_i),
           .setting_o(setting_o),
           .start_xfr_o(start_xfr_o),
           .go_idle_o(go_idle_o),
           .cmd_o(cmd_o),
           .response_i(response_i),
           .crc_ok_i(crc_ok_i),
           .index_ok_i(index_ok_i),
           .finish_i(finish_i),
           .busy_i(busy_i),
           //input card_detect,
           .argument_i(argument_i),
           .command_i(command_i),
           .timeout_i(timeout_i),
           .int_status_o(int_status_o),
           .response_0_o(response_0_o),
           .response_1_o(response_1_o),
           .response_2_o(response_2_o),
           .response_3_o(response_3_o)
       );
 
// Generating WB_CLK_I clock
always
begin
    sd_clk=0;
    forever #(SD_TCLK/2) sd_clk = ~sd_clk;
end
 
initial
begin
    rst = 1;
    start_i = 0;
    int_status_rst_i = 0;
    response_i = 0;
    crc_ok_i = 0;
    index_ok_i = 0;
    finish_i = 0;
    busy_i = 0;
    argument_i = 0;
    command_i = 0;
    timeout_i = 0;
 
    $display("sd_cmd_master_tb start ...");
 
    #(3*SD_TCLK);
    rst = 0;
    assert(setting_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 0);
    #(3*SD_TCLK);
    assert(setting_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 0);
 
    //test every response type with
    //without response
    start_i = 1;
    argument_i = 32'h01234567;
    command_i = 16'h0100; //CMD1
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    argument_i = 0;
    command_i = 0;
    timeout_i = 0;
    assert(start_xfr_o == 1);
    assert(setting_o == 2'b00);
    assert(go_idle_o == 0);
    assert(cmd_o == 40'h4101234567);
    #(10*SD_TCLK);
    finish_i = 1;
    #SD_TCLK;
    finish_i = 0;
    assert(start_xfr_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 1);
 
    int_status_rst_i = 1;
    #SD_TCLK;
    int_status_rst_i = 0;
    assert(int_status_o == 0);
 
    //with response
    start_i = 1;
    argument_i = 32'hdeadbeef;
    command_i = 16'h0501; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    argument_i = 0;
    command_i = 0;
    timeout_i = 0;
    assert(start_xfr_o == 1);
    assert(setting_o == 2'b01);
    assert(go_idle_o == 0);
    assert(cmd_o == 40'h45deadbeef);
    #(10*SD_TCLK);
    finish_i = 1;
    response_i = 120'h0102030405060708090a0b0c0d0e0f;
    #SD_TCLK;
    finish_i = 0;
    response_i = 0;
    assert(start_xfr_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 1);
    assert(response_0_o == 32'h01020304);
    assert(response_1_o == 32'h05060708);
    assert(response_2_o == 32'h090a0b0c);
    assert(response_3_o == 32'h0d0e0f00);
    #SD_TCLK;
 
    //with long response
    start_i = 1;
    argument_i = 32'hbad0dad0;
    command_i = 16'h1503; //CMD13
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    argument_i = 0;
    command_i = 0;
    timeout_i = 0;
    assert(int_status_o == 0); //status should be reset by ne command
    assert(start_xfr_o == 1);
    assert(setting_o == 2'b11);
    assert(go_idle_o == 0);
    assert(cmd_o == 40'h55bad0dad0);
    #(10*SD_TCLK);
    finish_i = 1;
    response_i = 120'h1112131415161718191a1b1c1d1e1f;
    #SD_TCLK;
    finish_i = 0;
    response_i = 0;
    assert(start_xfr_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 1);
    assert(response_0_o == 32'h11121314);
    assert(response_1_o == 32'h15161718);
    assert(response_2_o == 32'h191a1b1c);
    assert(response_3_o == 32'h1d1e1f00);
 
    int_status_rst_i = 1;
    #SD_TCLK;
    int_status_rst_i = 0;
    assert(int_status_o == 0);
 
    //test crc and index checks
    //default setup
    argument_i = 0;
    timeout_i = 100;
    response_i = 120'h0;
 
    //with crc check - no error
    start_i = 1;
    command_i = 16'h2509; //CMD5
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    crc_ok_i = 1;
    #SD_TCLK;
    finish_i = 0;
    crc_ok_i = 0;
    assert(int_status_o == 1);
    #SD_TCLK;
 
    //with crc check - error
    start_i = 1;
    command_i = 16'h2509; //CMD5
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    #SD_TCLK;
    finish_i = 0;
    response_i = 0;
    assert(int_status_o == 5'b01011);
    #SD_TCLK;
 
    //with index check - no error
    start_i = 1;
    command_i = 16'h2511; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    index_ok_i = 1;
    #SD_TCLK;
    finish_i = 0;
    index_ok_i = 0;
    assert(int_status_o == 1);
    #SD_TCLK;
 
    //with index check - error
    start_i = 1;
    command_i = 16'h2511; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    #SD_TCLK;
    finish_i = 0;
    assert(int_status_o == 5'b10011);
    #SD_TCLK;
 
    //with index and crc check - no error
    start_i = 1;
    command_i = 16'h2519; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    crc_ok_i = 1;
    index_ok_i = 1;
    #SD_TCLK;
    finish_i = 0;
    crc_ok_i = 0;
    index_ok_i = 0;
    assert(int_status_o == 1);
    #SD_TCLK;
 
    //with index check - error
    start_i = 1;
    command_i = 16'h2519; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    #(10*SD_TCLK);
    finish_i = 1;
    #SD_TCLK;
    finish_i = 0;
    assert(int_status_o == 5'b11011);
    #SD_TCLK;
 
    //test timeout
    start_i = 1;
    command_i = 16'h2519; //CMD5
    timeout_i = 10;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    wait(go_idle_o == 1);
    #(3*SD_TCLK/2);
    assert(int_status_o == 5'b00110);
    assert(start_xfr_o == 0);
    #(2*SD_TCLK);
    assert(go_idle_o == 0);
 
    //check if can perform normal xfer after timeout
    start_i = 1;
    argument_i = 32'hdeadbeef;
    command_i = 16'h0501; //CMD5
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    argument_i = 0;
    command_i = 0;
    timeout_i = 0;
    assert(start_xfr_o == 1);
    assert(setting_o == 2'b01);
    assert(go_idle_o == 0);
    assert(cmd_o == 40'h45deadbeef);
    #(10*SD_TCLK);
    finish_i = 1;
    response_i = 120'h0102030405060708090a0b0c0d0e0f;
    #SD_TCLK;
    finish_i = 0;
    response_i = 0;
    assert(start_xfr_o == 0);
    assert(go_idle_o == 0);
    assert(int_status_o == 1);
    assert(response_0_o == 32'h01020304);
    assert(response_1_o == 32'h05060708);
    assert(response_2_o == 32'h090a0b0c);
    assert(response_3_o == 32'h0d0e0f00);
    #SD_TCLK;
 
    //test with busy check
    start_i = 1;
    command_i = 16'h7505;
    timeout_i = 100;
    #SD_TCLK;
    start_i = 0;
    command_i = 0;
    timeout_i = 0;
    #(10*SD_TCLK);
    busy_i = 1;
    finish_i = 1;
    crc_ok_i = 1;
    #SD_TCLK;
    finish_i = 0;
    crc_ok_i = 0;
    assert(int_status_o == 0);
    #(5*SD_TCLK)
    assert(int_status_o == 0);
    busy_i = 0;
    #SD_TCLK;
    assert(int_status_o == 1);
    #SD_TCLK;
 
    #(10*SD_TCLK) $display("sd_cmd_master_tb finish ...");
    $finish;
 
end
 
endmodule

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Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [sd_cmd_master_tb.sv] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE SD Card Controller IP Core ////`
4			`//// ////`
5			`//// sd_cmd_master_tb.sv ////`
6			`//// ////`
7			`//// This file is part of the WISHBONE SD Card ////`
8			`//// Controller IP Core project ////`
9			`//// http://www.opencores.org/cores/xxx/ ////`
10			`//// ////`
11			`//// Description ////`
12			`//// testbench for sd_cmd_master module ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Marek Czerski, ma.czerski@gmail.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2013 Authors ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`include "sd_defines.h"
45
46			`module sd_cmd_master_tb();`
47
48			`parameter SD_TCLK = 20; // 50 MHz -> timescale 1ns`
49
50			`reg sd_clk;`
51			`reg rst;`
52			`reg start_i;`
53			`reg int_status_rst_i;`
54			`wire [1:0] setting_o;`
55			`reg start_xfr_o;`
56			`wire go_idle_o;`
57			`wire [39:0] cmd_o;`
58			`reg [119:0] response_i;`
59			`reg crc_ok_i;`
60			`reg index_ok_i;`
61			`reg finish_i;`
62			`reg busy_i;`
63			`reg [31:0] argument_i;`
64			`reg [13:0] command_i;`
65			`reg [15:0] timeout_i;`
66			wire [`INT_CMD_SIZE-1:0] int_status_o;
67			`wire [31:0] response_0_o;`
68			`wire [31:0] response_1_o;`
69			`wire [31:0] response_2_o;`
70			`wire [31:0] response_3_o;`
71
72			`sd_cmd_master sd_cmd_master_dut(`
73			`.sd_clk(sd_clk),`
74			`.rst(rst),`
75			`.start_i(start_i),`
76			`.int_status_rst_i(int_status_rst_i),`
77			`.setting_o(setting_o),`
78			`.start_xfr_o(start_xfr_o),`
79			`.go_idle_o(go_idle_o),`
80			`.cmd_o(cmd_o),`
81			`.response_i(response_i),`
82			`.crc_ok_i(crc_ok_i),`
83			`.index_ok_i(index_ok_i),`
84			`.finish_i(finish_i),`
85			`.busy_i(busy_i),`
86			`//input card_detect,`
87			`.argument_i(argument_i),`
88			`.command_i(command_i),`
89			`.timeout_i(timeout_i),`
90			`.int_status_o(int_status_o),`
91			`.response_0_o(response_0_o),`
92			`.response_1_o(response_1_o),`
93			`.response_2_o(response_2_o),`
94			`.response_3_o(response_3_o)`
95			`);`
96
97			`// Generating WB_CLK_I clock`
98			`always`
99			`begin`
100			`sd_clk=0;`
101			`forever #(SD_TCLK/2) sd_clk = ~sd_clk;`
102			`end`
103
104			`initial`
105			`begin`
106			`rst = 1;`
107			`start_i = 0;`
108			`int_status_rst_i = 0;`
109			`response_i = 0;`
110			`crc_ok_i = 0;`
111			`index_ok_i = 0;`
112			`finish_i = 0;`
113			`busy_i = 0;`
114			`argument_i = 0;`
115			`command_i = 0;`
116			`timeout_i = 0;`
117
118			`$display("sd_cmd_master_tb start ...");`
119
120			`#(3*SD_TCLK);`
121			`rst = 0;`
122			`assert(setting_o == 0);`
123			`assert(go_idle_o == 0);`
124			`assert(int_status_o == 0);`
125			`#(3*SD_TCLK);`
126			`assert(setting_o == 0);`
127			`assert(go_idle_o == 0);`
128			`assert(int_status_o == 0);`
129
130			`//test every response type with`
131			`//without response`
132			`start_i = 1;`
133			`argument_i = 32'h01234567;`
134			`command_i = 16'h0100; //CMD1`
135			`timeout_i = 100;`
136			`#SD_TCLK;`
137			`start_i = 0;`
138			`argument_i = 0;`
139			`command_i = 0;`
140			`timeout_i = 0;`
141			`assert(start_xfr_o == 1);`
142			`assert(setting_o == 2'b00);`
143			`assert(go_idle_o == 0);`
144			`assert(cmd_o == 40'h4101234567);`
145			`#(10*SD_TCLK);`
146			`finish_i = 1;`
147			`#SD_TCLK;`
148			`finish_i = 0;`
149			`assert(start_xfr_o == 0);`
150			`assert(go_idle_o == 0);`
151			`assert(int_status_o == 1);`
152
153			`int_status_rst_i = 1;`
154			`#SD_TCLK;`
155			`int_status_rst_i = 0;`
156			`assert(int_status_o == 0);`
157
158			`//with response`
159			`start_i = 1;`
160			`argument_i = 32'hdeadbeef;`
161			`command_i = 16'h0501; //CMD5`
162			`timeout_i = 100;`
163			`#SD_TCLK;`
164			`start_i = 0;`
165			`argument_i = 0;`
166			`command_i = 0;`
167			`timeout_i = 0;`
168			`assert(start_xfr_o == 1);`
169			`assert(setting_o == 2'b01);`
170			`assert(go_idle_o == 0);`
171			`assert(cmd_o == 40'h45deadbeef);`
172			`#(10*SD_TCLK);`
173			`finish_i = 1;`
174			`response_i = 120'h0102030405060708090a0b0c0d0e0f;`
175			`#SD_TCLK;`
176			`finish_i = 0;`
177			`response_i = 0;`
178			`assert(start_xfr_o == 0);`
179			`assert(go_idle_o == 0);`
180			`assert(int_status_o == 1);`
181			`assert(response_0_o == 32'h01020304);`
182			`assert(response_1_o == 32'h05060708);`
183			`assert(response_2_o == 32'h090a0b0c);`
184			`assert(response_3_o == 32'h0d0e0f00);`
185			`#SD_TCLK;`
186
187			`//with long response`
188			`start_i = 1;`
189			`argument_i = 32'hbad0dad0;`
190			`command_i = 16'h1503; //CMD13`
191			`timeout_i = 100;`
192			`#SD_TCLK;`
193			`start_i = 0;`
194			`argument_i = 0;`
195			`command_i = 0;`
196			`timeout_i = 0;`
197			`assert(int_status_o == 0); //status should be reset by ne command`
198			`assert(start_xfr_o == 1);`
199			`assert(setting_o == 2'b11);`
200			`assert(go_idle_o == 0);`
201			`assert(cmd_o == 40'h55bad0dad0);`
202			`#(10*SD_TCLK);`
203			`finish_i = 1;`
204			`response_i = 120'h1112131415161718191a1b1c1d1e1f;`
205			`#SD_TCLK;`
206			`finish_i = 0;`
207			`response_i = 0;`
208			`assert(start_xfr_o == 0);`
209			`assert(go_idle_o == 0);`
210			`assert(int_status_o == 1);`
211			`assert(response_0_o == 32'h11121314);`
212			`assert(response_1_o == 32'h15161718);`
213			`assert(response_2_o == 32'h191a1b1c);`
214			`assert(response_3_o == 32'h1d1e1f00);`
215
216			`int_status_rst_i = 1;`
217			`#SD_TCLK;`
218			`int_status_rst_i = 0;`
219			`assert(int_status_o == 0);`
220
221			`//test crc and index checks`
222			`//default setup`
223			`argument_i = 0;`
224			`timeout_i = 100;`
225			`response_i = 120'h0;`
226
227			`//with crc check - no error`
228			`start_i = 1;`
229			`command_i = 16'h2509; //CMD5`
230			`#SD_TCLK;`
231			`start_i = 0;`
232			`command_i = 0;`
233			`#(10*SD_TCLK);`
234			`finish_i = 1;`
235			`crc_ok_i = 1;`
236			`#SD_TCLK;`
237			`finish_i = 0;`
238			`crc_ok_i = 0;`
239			`assert(int_status_o == 1);`
240			`#SD_TCLK;`
241
242			`//with crc check - error`
243			`start_i = 1;`
244			`command_i = 16'h2509; //CMD5`
245			`#SD_TCLK;`
246			`start_i = 0;`
247			`command_i = 0;`
248			`#(10*SD_TCLK);`
249			`finish_i = 1;`
250			`#SD_TCLK;`
251			`finish_i = 0;`
252			`response_i = 0;`
253			`assert(int_status_o == 5'b01011);`
254			`#SD_TCLK;`
255
256			`//with index check - no error`
257			`start_i = 1;`
258			`command_i = 16'h2511; //CMD5`
259			`timeout_i = 100;`
260			`#SD_TCLK;`
261			`start_i = 0;`
262			`command_i = 0;`
263			`#(10*SD_TCLK);`
264			`finish_i = 1;`
265			`index_ok_i = 1;`
266			`#SD_TCLK;`
267			`finish_i = 0;`
268			`index_ok_i = 0;`
269			`assert(int_status_o == 1);`
270			`#SD_TCLK;`
271
272			`//with index check - error`
273			`start_i = 1;`
274			`command_i = 16'h2511; //CMD5`
275			`timeout_i = 100;`
276			`#SD_TCLK;`
277			`start_i = 0;`
278			`command_i = 0;`
279			`#(10*SD_TCLK);`
280			`finish_i = 1;`
281			`#SD_TCLK;`
282			`finish_i = 0;`
283			`assert(int_status_o == 5'b10011);`
284			`#SD_TCLK;`
285
286			`//with index and crc check - no error`
287			`start_i = 1;`
288			`command_i = 16'h2519; //CMD5`
289			`timeout_i = 100;`
290			`#SD_TCLK;`
291			`start_i = 0;`
292			`command_i = 0;`
293			`#(10*SD_TCLK);`
294			`finish_i = 1;`
295			`crc_ok_i = 1;`
296			`index_ok_i = 1;`
297			`#SD_TCLK;`
298			`finish_i = 0;`
299			`crc_ok_i = 0;`
300			`index_ok_i = 0;`
301			`assert(int_status_o == 1);`
302			`#SD_TCLK;`
303
304			`//with index check - error`
305			`start_i = 1;`
306			`command_i = 16'h2519; //CMD5`
307			`timeout_i = 100;`
308			`#SD_TCLK;`
309			`start_i = 0;`
310			`command_i = 0;`
311			`#(10*SD_TCLK);`
312			`finish_i = 1;`
313			`#SD_TCLK;`
314			`finish_i = 0;`
315			`assert(int_status_o == 5'b11011);`
316			`#SD_TCLK;`
317
318			`//test timeout`
319			`start_i = 1;`
320			`command_i = 16'h2519; //CMD5`
321			`timeout_i = 10;`
322			`#SD_TCLK;`
323			`start_i = 0;`
324			`command_i = 0;`
325			`wait(go_idle_o == 1);`
326			`#(3*SD_TCLK/2);`
327			`assert(int_status_o == 5'b00110);`
328			`assert(start_xfr_o == 0);`
329			`#(2*SD_TCLK);`
330			`assert(go_idle_o == 0);`
331
332			`//check if can perform normal xfer after timeout`
333			`start_i = 1;`
334			`argument_i = 32'hdeadbeef;`
335			`command_i = 16'h0501; //CMD5`
336			`timeout_i = 100;`
337			`#SD_TCLK;`
338			`start_i = 0;`
339			`argument_i = 0;`
340			`command_i = 0;`
341			`timeout_i = 0;`
342			`assert(start_xfr_o == 1);`
343			`assert(setting_o == 2'b01);`
344			`assert(go_idle_o == 0);`
345			`assert(cmd_o == 40'h45deadbeef);`
346			`#(10*SD_TCLK);`
347			`finish_i = 1;`
348			`response_i = 120'h0102030405060708090a0b0c0d0e0f;`
349			`#SD_TCLK;`
350			`finish_i = 0;`
351			`response_i = 0;`
352			`assert(start_xfr_o == 0);`
353			`assert(go_idle_o == 0);`
354			`assert(int_status_o == 1);`
355			`assert(response_0_o == 32'h01020304);`
356			`assert(response_1_o == 32'h05060708);`
357			`assert(response_2_o == 32'h090a0b0c);`
358			`assert(response_3_o == 32'h0d0e0f00);`
359			`#SD_TCLK;`
360
361			`//test with busy check`
362			`start_i = 1;`
363			`command_i = 16'h7505;`
364			`timeout_i = 100;`
365			`#SD_TCLK;`
366			`start_i = 0;`
367			`command_i = 0;`
368			`timeout_i = 0;`
369			`#(10*SD_TCLK);`
370			`busy_i = 1;`
371			`finish_i = 1;`
372			`crc_ok_i = 1;`
373			`#SD_TCLK;`
374			`finish_i = 0;`
375			`crc_ok_i = 0;`
376			`assert(int_status_o == 0);`
377			`#(5*SD_TCLK)`
378			`assert(int_status_o == 0);`
379			`busy_i = 0;`
380			`#SD_TCLK;`
381			`assert(int_status_o == 1);`
382			`#SD_TCLK;`
383
384			`#(10*SD_TCLK) $display("sd_cmd_master_tb finish ...");`
385			`$finish;`
386
387			`end`
388
389			`endmodule`