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[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [sd_data_xfer_trig_tb.sv] - Blame information for rev 3

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1 3 rozpruwacz 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// WISHBONE SD Card Controller IP Core                          ////
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////                                                              ////
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//// sd_data_xfer_trig_tb.sv                                      ////
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////                                                              ////
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//// This file is part of the WISHBONE SD Card                    ////
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//// Controller IP Core project                                   ////
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//// http://www.opencores.org/cores/xxx/                          ////
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////                                                              ////
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//// Description                                                  ////
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//// testbench for sd_data_xfer_trig module                       ////
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////                                                              ////
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//// Author(s):                                                   ////
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////     - Marek Czerski, ma.czerski@gmail.com                    ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2013 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "sd_defines.h"
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module sd_data_xfer_trig_tb();
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parameter SD_TCLK = 20; // 50 MHz -> timescale 1ns
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//---------------Input ports---------------
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reg sd_clk;
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reg rst;
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reg cmd_with_data_start_i;
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reg r_w_i;
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reg [`INT_CMD_SIZE-1:0] cmd_int_status_i;
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//---------------Output ports---------------
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wire start_tx_o;
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wire start_rx_o;
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sd_data_xfer_trig sd_data_xfer_trig_dut(
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    .sd_clk                (sd_clk),
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    .rst                   (rst),
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    .cmd_with_data_start_i (cmd_with_data_start_i),
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    .r_w_i                 (r_w_i),
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    .cmd_int_status_i      (cmd_int_status_i),
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    .start_tx_o            (start_tx_o),
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    .start_rx_o            (start_rx_o)
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    );
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// Generating SD_CLK clock
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always
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begin
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    sd_clk = 0;
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    forever #(SD_TCLK/2) sd_clk = ~sd_clk;
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end
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initial
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begin
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    rst = 1;
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    cmd_with_data_start_i = 0;
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    r_w_i = 0;
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    cmd_int_status_i = 0;
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    $display("sd_data_xfer_trig_tb start ...");
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    #(3*SD_TCLK);
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    rst = 0;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //succesful cmd xfer test - read
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    cmd_with_data_start_i = 1;
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    r_w_i = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 1);
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    cmd_with_data_start_i = 0;
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    r_w_i = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_CC] = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_CC] = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //reset
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    rst = 1;
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    #(3*SD_TCLK);
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    rst = 0;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //succesful cmd xfer test - write
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    cmd_with_data_start_i = 1;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_with_data_start_i = 0;
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    #(3*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_CC] = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 1);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_CC] = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //reset
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    rst = 1;
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    #(3*SD_TCLK);
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    rst = 0;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //unsuccesful cmd xfer test - read
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    cmd_with_data_start_i = 1;
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    r_w_i = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 1);
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    cmd_with_data_start_i = 0;
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    r_w_i = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_EI] = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_EI] = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //reset
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    rst = 1;
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    #(3*SD_TCLK);
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    rst = 0;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    //unsuccesful cmd xfer test - write
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    cmd_with_data_start_i = 1;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_with_data_start_i = 0;
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    #(3*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_EI] = 1;
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    #(2*SD_TCLK);
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    cmd_int_status_i[`INT_CMD_EI] = 0;
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    #SD_TCLK;
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    assert(start_tx_o == 0);
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    assert(start_rx_o == 0);
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    #(10*SD_TCLK) $display("sd_data_xfer_trig_tb finish ...");
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    $finish;
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end
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endmodule

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