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[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/10/09 13:16:51  tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
//
// Revision 1.2  2002/09/13 12:29:14  mohor
// Headers changed.
//
// Revision 1.1  2002/09/13 11:57:20  mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "wb_model_defines.h"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                    ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    check_CTI,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input                           check_CTI ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I)
begin
    if (RST_I !== 1'b0)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O !== 1'b0)
        begin
            message_out("CYC_O active under reset") ;
        end
 
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active under reset") ;
        end
 
        if (ACK_I !== 1'b0)
            message_out("ACK_I active under reset") ;
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active under reset") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active under reset") ;
        end
 
    end // reset
    else
    if (CYC_O !== 1'b1)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active without CYC_O being active") ;
        end
 
        if (ACK_I !== 1'b0)
        begin
            message_out("ACK_I active without CYC_O being active") ;
        end
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active without CYC_O being active") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active without CYC_O being active") ;
        end
 
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
reg                     previous_stb ;
reg                     previous_ack ;
reg                     previous_err ;
reg                     previous_rty ;
reg                     previous_cyc ;
reg                     previous_we  ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        previous_stb        <= 1'b0 ;
        previous_ack        <= 1'b0 ;
        previous_err        <= 1'b0 ;
        previous_rty        <= 1'b0 ;
        previous_cyc        <= 1'b0 ;
        previous_tag        <= 'd0  ;
        previous_we         <= 1'b0 ;
        previous_data_o     <= 0    ;
        previous_data_i     <= 0    ;
        previous_address    <= 0    ;
        previous_sel        <= 0    ;
    end
    else
    begin
        previous_stb        <= STB_O    ;
        previous_ack        <= ACK_I    ;
        previous_err        <= ERR_I    ;
        previous_rty        <= RTY_I    ;
        previous_cyc        <= CYC_O    ;
        previous_tag        <= TAG_O    ;
        previous_we         <= WE_O     ;
        previous_data_o     <= DAT_O    ;
        previous_data_i     <= DAT_I    ;
        previous_address    <= ADDR_O   ;
        previous_sel        <= SEL_O    ;
    end
end
 
// cycle monitor
always@(posedge CLK_I)
begin:cycle_monitor_blk
    reg master_can_change ;
    reg slave_can_change  ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
    begin
        // check for two control signals active at same edge
        if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
        begin
            message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
        end
 
        if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if (previous_cyc === 1'b1)
        begin
            if (previous_stb === 1'b1)
            begin
                if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
                    master_can_change = 1'b1 ;
                else
                    master_can_change = 1'b0 ;
            end
            else
            begin
                master_can_change = 1'b1 ;
            end
 
            if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
            begin
                if (previous_stb === 1'b1)
                    slave_can_change = 1'b1 ;
                else
                    slave_can_change = 1'b0 ;
            end
            else
            begin
                slave_can_change = 1'b1 ;
            end
        end
        else
        begin
            master_can_change = 1'b1 ;
            slave_can_change  = 1'b1 ;
        end
    end
    else
    begin
        master_can_change = 1'b1 ;
        slave_can_change  = 1'b1 ;
    end
 
    if (master_can_change !== 1'b1)
    begin
        if (CYC_O !== previous_cyc)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
        end
 
        if (STB_O !== previous_stb)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
        end
 
        if (TAG_O !== previous_tag)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
        end
 
        if (ADDR_O !== previous_address)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
        end
 
        if (SEL_O !== previous_sel)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
        end
 
        if (WE_O !== previous_we)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
        end
 
        if (WE_O !== 1'b0)
        begin
            if (DAT_O !== previous_data_o)
            begin
                message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
            end
        end
    end
 
    if (slave_can_change !== 1'b1)
    begin
        if (previous_ack !== ACK_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
        end
 
        if (previous_rty !== RTY_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
        end
 
        if (previous_err !== ERR_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
        end
 
        if (previous_data_i !== DAT_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
        end
    end
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("CAB_O value changed during cycle") ;
            $fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
        end
    end
end // CAB_O monitor
 
// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
reg [2:0] first_cti_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
        first_cti_val <= 3'b000 ;
    // logging for burst cycle
    else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
    begin
        message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
        $display("CTI_O didn't change to '111' when end of burst") ;
        $fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
        first_cti_val <= 3'b000 ;
    end
    else if (CYC_O === 0)
        first_cti_val <= 3'b000 ;
    else
    begin
        if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b001 ;
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b010 ;
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b011 ;
        else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b010 ;
        // logging for clasic cycles
        else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
        begin
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
            $display("CTI_O change during CYC_O when clasic cycle") ;
            $fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
        end
        // logging for end of burs cycle
        else if (check_CTI && (first_cti_val == 3'b010))
        begin
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
            $display("CTI_O change to '111' before end of burst") ;
            $fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
        end
    end
end
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("WE_O value changed during CAB cycle") ;
            $fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
            begin
                address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
                    message_out("Consecutive address burst address incrementing incorrect") ;
                end
                else
                    address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin:data_monitor_blk
    reg                       last_valid_we     ;
    reg [`WB_SEL_WIDTH - 1:0] last_valid_sel    ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
    begin
        if (STB_O !== 1'b0)
        begin
            last_valid_we   = WE_O  ;
            last_valid_sel  = SEL_O ;
 
            if ( (ADDR_O ^ ADDR_O) !== 0 )
            begin
                message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
            end
 
            if ( (SEL_O ^ SEL_O) !== 0 )
            begin
                message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
            end
 
            if ( WE_O )
            begin
                if (
                    ( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
                    ( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
                    ( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
                    ( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
                   )
                begin
                    message_out("Master provided invalid data during write and qualified it with STB_O") ;
                    $display("Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                    $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                end
            end
 
            if ((TAG_O ^ TAG_O) !== 0)
            begin
                message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
            end
        end
 
        if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
        begin
            if (
                ( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
                ( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
                ( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
                ( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
               )
            begin
                message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
            end
        end
    end
    else
    begin
        last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
        last_valid_we  = 1'bx ;
    end
end
 
task message_out ;
    input [7999:0] message_i ;
begin
    $display("Time: %t", $time) ;
    $display("%m, %0s", message_i) ;
    $fdisplay(log_file_desc, "Time: %t", $time) ;
    $fdisplay(log_file_desc, "%m, %0s", message_i) ;
end
endtask // display message
 
endmodule // BUS_MON

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Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.3 2002/10/09 13:16:51 tadejm`
47			`// Just back-up; not completed testbench and some testcases are not`
48			`// wotking properly yet.`
49			`//`
50			`// Revision 1.2 2002/09/13 12:29:14 mohor`
51			`// Headers changed.`
52			`//`
53			`// Revision 1.1 2002/09/13 11:57:20 mohor`
54			`// New testbench. Thanks to Tadej M - "The Spammer".`
55			`//`
56			`// Revision 1.1 2002/02/01 13:39:43 mihad`
57			`// Initial testbench import. Still under development`
58			`//`
59			`// Revision 1.1 2001/08/06 18:12:58 mihad`
60			`// Pocasi delamo kompletno zadevo`
61			`//`
62			`//`
63
64			`include "wb_model_defines.h"
65			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
66			`// monitors for any illegal combinations appearing on the bus.`
67			`module WB_BUS_MON(`
68			`CLK_I,`
69			`RST_I,`
70			`ACK_I,`
71			`ADDR_O,`
72			`CYC_O,`
73			`DAT_I,`
74			`DAT_O,`
75			`ERR_I,`
76			`RTY_I,`
77			`SEL_O,`
78			`STB_O,`
79			`WE_O,`
80			`TAG_I,`
81			`TAG_O,`
82			`CAB_O,`
83			`check_CTI,`
84			`log_file_desc`
85			`) ;`
86
87			`input CLK_I ;`
88			`input RST_I ;`
89			`input ACK_I ;`
90			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
91			`input CYC_O ;`
92			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
93			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
94			`input ERR_I ;`
95			`input RTY_I ;`
96			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
97			`input STB_O ;`
98			`input WE_O ;`
99			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
100			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
101			`input CAB_O ;`
102			`input check_CTI ;`
103			`input [31:0] log_file_desc ;`
104
105			`always@(posedge CLK_I)`
106			`begin`
107			`if (RST_I !== 1'b0)`
108			`begin`
109			`// when reset is applied, all control signals must be low`
110			`if (CYC_O !== 1'b0)`
111			`begin`
112			`message_out("CYC_O active under reset") ;`
113			`end`
114
115			`if (STB_O !== 1'b0)`
116			`begin`
117			`message_out("STB_O active under reset") ;`
118			`end`
119
120			`if (ACK_I !== 1'b0)`
121			`message_out("ACK_I active under reset") ;`
122
123			`if (ERR_I !== 1'b0)`
124			`begin`
125			`message_out("ERR_I active under reset") ;`
126			`end`
127
128			`if (RTY_I !== 1'b0)`
129			`begin`
130			`message_out("RTY_I active under reset") ;`
131			`end`
132
133			`end // reset`
134			`else`
135			`if (CYC_O !== 1'b1)`
136			`begin`
137			`// when cycle indicator is low, all control signals must be low`
138			`if (STB_O !== 1'b0)`
139			`begin`
140			`message_out("STB_O active without CYC_O being active") ;`
141			`end`
142
143			`if (ACK_I !== 1'b0)`
144			`begin`
145			`message_out("ACK_I active without CYC_O being active") ;`
146			`end`
147
148			`if (ERR_I !== 1'b0)`
149			`begin`
150			`message_out("ERR_I active without CYC_O being active") ;`
151			`end`
152
153			`if (RTY_I !== 1'b0)`
154			`begin`
155			`message_out("RTY_I active without CYC_O being active") ;`
156			`end`
157
158			`end // ~CYC_O`
159			`end`
160
161			reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
162			reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
163			reg [`WB_ADDR_WIDTH-1:0] previous_address ;
164			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
165			reg [`WB_TAG_WIDTH-1:0] previous_tag ;
166			`reg previous_stb ;`
167			`reg previous_ack ;`
168			`reg previous_err ;`
169			`reg previous_rty ;`
170			`reg previous_cyc ;`
171			`reg previous_we ;`
172
173			`always@(posedge CLK_I or posedge RST_I)`
174			`begin`
175			`if (RST_I)`
176			`begin`
177			`previous_stb <= 1'b0 ;`
178			`previous_ack <= 1'b0 ;`
179			`previous_err <= 1'b0 ;`
180			`previous_rty <= 1'b0 ;`
181			`previous_cyc <= 1'b0 ;`
182			`previous_tag <= 'd0 ;`
183			`previous_we <= 1'b0 ;`
184			`previous_data_o <= 0 ;`
185			`previous_data_i <= 0 ;`
186			`previous_address <= 0 ;`
187			`previous_sel <= 0 ;`
188			`end`
189			`else`
190			`begin`
191			`previous_stb <= STB_O ;`
192			`previous_ack <= ACK_I ;`
193			`previous_err <= ERR_I ;`
194			`previous_rty <= RTY_I ;`
195			`previous_cyc <= CYC_O ;`
196			`previous_tag <= TAG_O ;`
197			`previous_we <= WE_O ;`
198			`previous_data_o <= DAT_O ;`
199			`previous_data_i <= DAT_I ;`
200			`previous_address <= ADDR_O ;`
201			`previous_sel <= SEL_O ;`
202			`end`
203			`end`
204
205			`// cycle monitor`
206			`always@(posedge CLK_I)`
207			`begin:cycle_monitor_blk`
208			`reg master_can_change ;`
209			`reg slave_can_change ;`
210
211			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress`
212			`begin`
213			`// check for two control signals active at same edge`
214			`if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )`
215			`begin`
216			`message_out("ACK_I and RTY_I asserted at the same time during cycle") ;`
217			`end`
218
219			`if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )`
220			`begin`
221			`message_out("ACK_I and ERR_I asserted at the same time during cycle") ;`
222			`end`
223
224			`if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )`
225			`begin`
226			`message_out("RTY_I and ERR_I asserted at the same time during cycle") ;`
227			`end`
228
229			`if (previous_cyc === 1'b1)`
230			`begin`
231			`if (previous_stb === 1'b1)`
232			`begin`
233			`if ((previous_ack === 1'b1) \| (previous_rty === 1'b1) \| (previous_err === 1'b1))`
234			`master_can_change = 1'b1 ;`
235			`else`
236			`master_can_change = 1'b0 ;`
237			`end`
238			`else`
239			`begin`
240			`master_can_change = 1'b1 ;`
241			`end`
242
243			`if ((previous_ack === 1'b1) \| (previous_err === 1'b1) \| (previous_rty === 1'b1))`
244			`begin`
245			`if (previous_stb === 1'b1)`
246			`slave_can_change = 1'b1 ;`
247			`else`
248			`slave_can_change = 1'b0 ;`
249			`end`
250			`else`
251			`begin`
252			`slave_can_change = 1'b1 ;`
253			`end`
254			`end`
255			`else`
256			`begin`
257			`master_can_change = 1'b1 ;`
258			`slave_can_change = 1'b1 ;`
259			`end`
260			`end`
261			`else`
262			`begin`
263			`master_can_change = 1'b1 ;`
264			`slave_can_change = 1'b1 ;`
265			`end`
266
267			`if (master_can_change !== 1'b1)`
268			`begin`
269			`if (CYC_O !== previous_cyc)`
270			`begin`
271			`message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;`
272			`end`
273
274			`if (STB_O !== previous_stb)`
275			`begin`
276			`message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;`
277			`end`
278
279			`if (TAG_O !== previous_tag)`
280			`begin`
281			`message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;`
282			`end`
283
284			`if (ADDR_O !== previous_address)`
285			`begin`
286			`message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;`
287			`end`
288
289			`if (SEL_O !== previous_sel)`
290			`begin`
291			`message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;`
292			`end`
293
294			`if (WE_O !== previous_we)`
295			`begin`
296			`message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;`
297			`end`
298
299			`if (WE_O !== 1'b0)`
300			`begin`
301			`if (DAT_O !== previous_data_o)`
302			`begin`
303			`message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
304			`end`
305			`end`
306			`end`
307
308			`if (slave_can_change !== 1'b1)`
309			`begin`
310			`if (previous_ack !== ACK_I)`
311			`begin`
312			`message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;`
313			`end`
314
315			`if (previous_rty !== RTY_I)`
316			`begin`
317			`message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;`
318			`end`
319
320			`if (previous_err !== ERR_I)`
321			`begin`
322			`message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;`
323			`end`
324
325			`if (previous_data_i !== DAT_I)`
326			`begin`
327			`message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
328			`end`
329			`end`
330			`end // cycle monitor`
331
332			`// CAB_O monitor - CAB_O musn't change during one cycle`
333			`reg [1:0] first_cab_val ;`
334			`always@(posedge CLK_I or RST_I)`
335			`begin`
336			`if ((CYC_O === 0) \|\| RST_I)`
337			`first_cab_val <= 2'b00 ;`
338			`else`
339			`begin`
340			`// cycle in progress - is this first clock edge in a cycle ?`
341			`if (first_cab_val[1] === 1'b0)`
342			`first_cab_val <= {1'b1, CAB_O} ;`
343			`else if ( first_cab_val[0] !== CAB_O )`
344			`begin`
345			`$display("CAB_O value changed during cycle") ;`
346			`$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;`
347			`end`
348			`end`
349			`end // CAB_O monitor`
350
351			`// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts`
352			`reg [2:0] first_cti_val ;`
353			`always@(posedge CLK_I or posedge RST_I)`
354			`begin`
355			`if (RST_I)`
356			`first_cti_val <= 3'b000 ;`
357			`// logging for burst cycle`
358			`else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty \|\| previous_err)))`
359			`begin`
360			`message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;`
361			`$display("CTI_O didn't change to '111' when end of burst") ;`
362			`$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;`
363			`first_cti_val <= 3'b000 ;`
364			`end`
365			`else if (CYC_O === 0)`
366			`first_cti_val <= 3'b000 ;`
367			`else`
368			`begin`
369			`if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I \|\| ERR_I \|\| RTY_I))`
370			`first_cti_val <= 3'b001 ;`
371			`else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I \|\| ERR_I \|\| RTY_I))`
372			`first_cti_val <= 3'b010 ;`
373			`else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I \|\| ERR_I \|\| RTY_I))`
374			`first_cti_val <= 3'b011 ;`
375			`else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I \|\| ERR_I \|\| RTY_I))`
376			`first_cti_val <= 3'b010 ;`
377			`// logging for clasic cycles`
378			`else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))`
379			`begin`
380			`message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;`
381			`$display("CTI_O change during CYC_O when clasic cycle") ;`
382			`$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;`
383			`end`
384			`// logging for end of burs cycle`
385			`else if (check_CTI && (first_cti_val == 3'b010))`
386			`begin`
387			`message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;`
388			`$display("CTI_O change to '111' before end of burst") ;`
389			`$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;`
390			`end`
391			`end`
392			`end`
393
394			`// WE_O monitor for consecutive address bursts`
395			`reg [1:0] first_we_val ;`
396			`always@(posedge CLK_I or posedge RST_I)`
397			`begin`
398			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
399			`first_we_val <= 2'b00 ;`
400			`else`
401			`if (STB_O)`
402			`begin`
403			`// cycle in progress - is this first clock edge in a cycle ?`
404			`if (first_we_val[1] == 1'b0)`
405			`first_we_val <= {1'b1, WE_O} ;`
406			`else if ( first_we_val[0] != WE_O )`
407			`begin`
408			`$display("WE_O value changed during CAB cycle") ;`
409			`$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;`
410			`end`
411			`end`
412			`end // CAB_O monitor`
413
414			`// address monitor for consecutive address bursts`
415			reg [`WB_ADDR_WIDTH:0] address ;
416			`always@(posedge CLK_I or posedge RST_I)`
417			`begin`
418			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
419			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
420			`else`
421			`begin`
422			`if (STB_O && ACK_I)`
423			`begin`
424			if (address[`WB_ADDR_WIDTH] == 1'b0)
425			`begin`
426			address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
427			`end`
428			`else`
429			`begin`
430			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
431			`begin`
432			$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
433			`message_out("Consecutive address burst address incrementing incorrect") ;`
434			`end`
435			`else`
436			address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
437			`end`
438			`end`
439			`end`
440			`end // address monitor`
441
442			`// data monitor`
443			`always@(posedge CLK_I or posedge RST_I)`
444			`begin:data_monitor_blk`
445			`reg last_valid_we ;`
446			reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
447
448			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))`
449			`begin`
450			`if (STB_O !== 1'b0)`
451			`begin`
452			`last_valid_we = WE_O ;`
453			`last_valid_sel = SEL_O ;`
454
455			`if ( (ADDR_O ^ ADDR_O) !== 0 )`
456			`begin`
457			`message_out("Master provided invalid ADR_O and qualified it with STB_O") ;`
458			`end`
459
460			`if ( (SEL_O ^ SEL_O) !== 0 )`
461			`begin`
462			`message_out("Master provided invalid SEL_O and qualified it with STB_O") ;`
463			`end`
464
465			`if ( WE_O )`
466			`begin`
467			`if (`
468			`( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) \|`
469			`( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) \|`
470			`( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) \|`
471			`( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )`
472			`)`
473			`begin`
474			`message_out("Master provided invalid data during write and qualified it with STB_O") ;`
475			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
476			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
477			`end`
478			`end`
479
480			`if ((TAG_O ^ TAG_O) !== 0)`
481			`begin`
482			`message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;`
483			`end`
484			`end`
485
486			`if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))`
487			`begin`
488			`if (`
489			`( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) \|`
490			`( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) \|`
491			`( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) \|`
492			`( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )`
493			`)`
494			`begin`
495			`message_out("Slave provided invalid data during read and qualified it with ACK_I") ;`
496			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
497			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
498			`end`
499			`end`
500			`end`
501			`else`
502			`begin`
503			last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
504			`last_valid_we = 1'bx ;`
505			`end`
506			`end`
507
508			`task message_out ;`
509			`input [7999:0] message_i ;`
510			`begin`
511			`$display("Time: %t", $time) ;`
512			`$display("%m, %0s", message_i) ;`
513			`$fdisplay(log_file_desc, "Time: %t", $time) ;`
514			`$fdisplay(log_file_desc, "%m, %0s", message_i) ;`
515			`end`
516			`endtask // display message`
517
518			`endmodule // BUS_MON`