URL https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk

Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 3

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_master_behavioral.v"                          ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002  Authors                                  ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/09/13 11:57:20  mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
// Revision 1.1  2002/07/29 11:25:20  mihad
// Adding test bench for memory interface
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
 
`include "wb_model_defines.h"
module WB_MASTER_BEHAVIORAL
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);
 
    input                    CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O;
 
// instantiate low level master module
WB_MASTER32 wbm_low_level
(
    .CLK_I(CLK_I),
    .RST_I(RST_I),
    .TAG_I(TAG_I),
    .TAG_O(TAG_O),
    .ACK_I(ACK_I),
    .ADR_O(ADR_O),
    .CYC_O(CYC_O),
    .DAT_I(DAT_I),
    .DAT_O(DAT_O),
    .ERR_I(ERR_I),
    .RTY_I(RTY_I),
    .SEL_O(SEL_O),
    .STB_O(STB_O),
    .WE_O(WE_O),
    .CAB_O(CAB_O)
) ;
 
// block read and write buffers definition
// single write buffer
reg `WRITE_STIM_TYPE  blk_write_data    [0:(`MAX_BLK_SIZE - 1)] ;
// read stimulus buffer - addresses, tags, selects etc.
reg `READ_STIM_TYPE   blk_read_data_in  [0:(`MAX_BLK_SIZE - 1)] ;
// read return buffer - data and tags received while performing block reads
reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
 
// single write task
task wb_single_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b1, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_write
 
task wb_single_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_read
 
task wb_RMW_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        if (retry === 1)
            wbm_low_level.end_cycle ;
        else
            wbm_low_level.modify_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_read
 
task wb_RMW_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        //@(posedge CLK_I) ;
        ok = 1 ;
        if (rty_count !== 0)
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
 
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_write
 
task wb_block_write ;
    input  `WB_TRANSFER_FLAGS write_flags ;
    inout  `WRITE_RETURN_TYPE return ;
 
    reg in_use ;
    reg `WRITE_STIM_TYPE  current_write ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = write_flags`WB_TRANSFER_CAB ;
    wbm_low_level.start_cycle(cab, 1'b1, ok) ;
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = write_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
        wbm_low_level.wbm_write(current_write, return) ;
 
        // check result of write operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = write_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_write
 
task wb_block_read ;
    input  `WB_TRANSFER_FLAGS      read_flags ;
    inout `READ_RETURN_TYPE       return ;
 
    reg in_use ;
    reg `READ_STIM_TYPE  current_read ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
    integer transfered ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    transfered = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = read_flags`WB_TRANSFER_CAB ;
 
    wbm_low_level.start_cycle(cab, 1'b0, ok) ;
 
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = read_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
 
        wbm_low_level.wbm_read(current_read, return) ;
 
        if ( transfered !== return`CYC_ACTUAL_TRANSFER )
        begin
            blk_read_data_out[transfered] = return ;
            transfered = return`CYC_ACTUAL_TRANSFER ;
        end
 
        // check result of read operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = read_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b0, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_read
 
endmodule
 

Browse

Tools

Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_master_behavioral.v" ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is available in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2002/09/13 11:57:20 mohor`
45			`// New testbench. Thanks to Tadej M - "The Spammer".`
46			`//`
47			`// Revision 1.1 2002/07/29 11:25:20 mihad`
48			`// Adding test bench for memory interface`
49			`//`
50			`// Revision 1.1 2002/02/01 13:39:43 mihad`
51			`// Initial testbench import. Still under development`
52			`//`
53
54			`include "wb_model_defines.h"
55			`module WB_MASTER_BEHAVIORAL`
56			`(`
57			`CLK_I,`
58			`RST_I,`
59			`TAG_I,`
60			`TAG_O,`
61			`ACK_I,`
62			`ADR_O,`
63			`CYC_O,`
64			`DAT_I,`
65			`DAT_O,`
66			`ERR_I,`
67			`RTY_I,`
68			`SEL_O,`
69			`STB_O,`
70			`WE_O,`
71			`CAB_O`
72			`);`
73
74			`input CLK_I;`
75			`input RST_I;`
76			input `WB_TAG_TYPE TAG_I;
77			output `WB_TAG_TYPE TAG_O;
78			`input ACK_I;`
79			output `WB_ADDR_TYPE ADR_O;
80			`output CYC_O;`
81			input `WB_DATA_TYPE DAT_I;
82			output `WB_DATA_TYPE DAT_O;
83			`input ERR_I;`
84			`input RTY_I;`
85			output `WB_SEL_TYPE SEL_O;
86			`output STB_O;`
87			`output WE_O;`
88			`output CAB_O;`
89
90			`// instantiate low level master module`
91			`WB_MASTER32 wbm_low_level`
92			`(`
93			`.CLK_I(CLK_I),`
94			`.RST_I(RST_I),`
95			`.TAG_I(TAG_I),`
96			`.TAG_O(TAG_O),`
97			`.ACK_I(ACK_I),`
98			`.ADR_O(ADR_O),`
99			`.CYC_O(CYC_O),`
100			`.DAT_I(DAT_I),`
101			`.DAT_O(DAT_O),`
102			`.ERR_I(ERR_I),`
103			`.RTY_I(RTY_I),`
104			`.SEL_O(SEL_O),`
105			`.STB_O(STB_O),`
106			`.WE_O(WE_O),`
107			`.CAB_O(CAB_O)`
108			`) ;`
109
110			`// block read and write buffers definition`
111			`// single write buffer`
112			reg `WRITE_STIM_TYPE blk_write_data [0:(`MAX_BLK_SIZE - 1)] ;
113			`// read stimulus buffer - addresses, tags, selects etc.`
114			reg `READ_STIM_TYPE blk_read_data_in [0:(`MAX_BLK_SIZE - 1)] ;
115			`// read return buffer - data and tags received while performing block reads`
116			reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
117
118			`// single write task`
119			`task wb_single_write ;`
120			input `WRITE_STIM_TYPE write_data ;
121			input `WB_TRANSFER_FLAGS write_flags ;
122			inout `WRITE_RETURN_TYPE return ;
123			`reg in_use ;`
124			`reg cab ;`
125			`reg ok ;`
126			`integer cyc_count ;`
127			`integer rty_count ;`
128			`reg retry ;`
129			`begin:main`
130
131			return`TB_ERROR_BIT = 1'b0 ;
132			`cab = 0 ;`
133			return`CYC_ACTUAL_TRANSFER = 0 ;
134			`rty_count = 0 ;`
135
136			`// check if task was called before previous call finished`
137			`if ( in_use === 1 )`
138			`begin`
139			`$display("*E, wb_single_write routine re-entered! Time %t ", $time) ;`
140			return`TB_ERROR_BIT = 1'b1 ;
141			`disable main ;`
142			`end`
143
144			`in_use = 1 ;`
145
146			`retry = 1 ;`
147
148			`while (retry === 1)`
149			`begin`
150			`// synchronize operation to clock`
151			`@(posedge CLK_I) ;`
152
153			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
154			`if ( ok !== 1 )`
155			`begin`
156			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
157			return`TB_ERROR_BIT = 1'b1 ;
158			`disable main ;`
159			`end`
160
161			`// first insert initial wait states`
162			cyc_count = write_flags`INIT_WAITS ;
163			`while ( cyc_count > 0 )`
164			`begin`
165			`@(posedge CLK_I) ;`
166			`cyc_count = cyc_count - 1 ;`
167			`end`
168
169			`wbm_low_level.wbm_write(write_data, return) ;`
170
171			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
172			`begin`
173			if ( rty_count === `WB_TB_MAX_RTY )
174			`begin`
175			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
176			`retry = 0 ;`
177			`end`
178			`else`
179			`begin`
180			`retry = 1 ;`
181			`rty_count = rty_count + 1 ;`
182			`end`
183			`end`
184			`else`
185			`retry = 0 ;`
186
187			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
188			if ( return`TB_ERROR_BIT !== 0 )
189			`begin`
190			`@(posedge CLK_I) ;`
191			`wbm_low_level.end_cycle ;`
192			`disable main ;`
193			`end`
194
195			cyc_count = write_flags`SUBSEQ_WAITS ;
196			`while ( cyc_count > 0 )`
197			`begin`
198			`@(posedge CLK_I) ;`
199			`cyc_count = cyc_count - 1 ;`
200			`end`
201
202			`wbm_low_level.end_cycle ;`
203			`end`
204
205			`in_use = 0 ;`
206
207			`end //main`
208			`endtask // wb_single_write`
209
210			`task wb_single_read ;`
211			input `READ_STIM_TYPE read_data ;
212			input `WB_TRANSFER_FLAGS read_flags ;
213			inout `READ_RETURN_TYPE return ;
214			`reg in_use ;`
215			`reg cab ;`
216			`reg ok ;`
217			`integer cyc_count ;`
218			`integer rty_count ;`
219			`reg retry ;`
220			`begin:main`
221
222			return`TB_ERROR_BIT = 1'b0 ;
223			`cab = 0 ;`
224			`rty_count = 0 ;`
225			return`CYC_ACTUAL_TRANSFER = 0 ;
226
227			`// check if task was called before previous call finished`
228			`if ( in_use === 1 )`
229			`begin`
230			`$display("*E, wb_single_read routine re-entered! Time %t ", $time) ;`
231			return`TB_ERROR_BIT = 1'b1 ;
232			`disable main ;`
233			`end`
234
235			`in_use = 1 ;`
236
237			`retry = 1 ;`
238
239			`while (retry === 1)`
240			`begin`
241			`// synchronize operation to clock`
242			`@(posedge CLK_I) ;`
243
244			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
245			`if ( ok !== 1 )`
246			`begin`
247			`$display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;`
248			return`TB_ERROR_BIT = 1'b1 ;
249			`disable main ;`
250			`end`
251
252			`// first insert initial wait states`
253			cyc_count = read_flags`INIT_WAITS ;
254			`while ( cyc_count > 0 )`
255			`begin`
256			`@(posedge CLK_I) ;`
257			`cyc_count = cyc_count - 1 ;`
258			`end`
259
260			`wbm_low_level.wbm_read(read_data, return) ;`
261
262			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
263			`begin`
264			if ( rty_count === `WB_TB_MAX_RTY )
265			`begin`
266			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;`
267			`retry = 0 ;`
268			`end`
269			`else`
270			`begin`
271			`retry = 1 ;`
272			`rty_count = rty_count + 1 ;`
273			`end`
274			`end`
275			`else`
276			`begin`
277			`retry = 0 ;`
278			`end`
279
280			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
281			if ( return`TB_ERROR_BIT !== 0 )
282			`begin`
283			`@(posedge CLK_I) ;`
284			`wbm_low_level.end_cycle ;`
285			`disable main ;`
286			`end`
287
288			cyc_count = read_flags`SUBSEQ_WAITS ;
289			`while ( cyc_count > 0 )`
290			`begin`
291			`@(posedge CLK_I) ;`
292			`cyc_count = cyc_count - 1 ;`
293			`end`
294
295			`wbm_low_level.end_cycle ;`
296			`end`
297
298			`in_use = 0 ;`
299
300			`end //main`
301			`endtask // wb_single_read`
302
303			`task wb_RMW_read ;`
304			input `READ_STIM_TYPE read_data ;
305			input `WB_TRANSFER_FLAGS read_flags ;
306			inout `READ_RETURN_TYPE return ;
307			`reg in_use ;`
308			`reg cab ;`
309			`reg ok ;`
310			`integer cyc_count ;`
311			`integer rty_count ;`
312			`reg retry ;`
313			`begin:main`
314
315			return`TB_ERROR_BIT = 1'b0 ;
316			`cab = 0 ;`
317			`rty_count = 0 ;`
318			return`CYC_ACTUAL_TRANSFER = 0 ;
319
320			`// check if task was called before previous call finished`
321			`if ( in_use === 1 )`
322			`begin`
323			`$display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;`
324			return`TB_ERROR_BIT = 1'b1 ;
325			`disable main ;`
326			`end`
327
328			`in_use = 1 ;`
329
330			`retry = 1 ;`
331
332			`while (retry === 1)`
333			`begin`
334			`// synchronize operation to clock`
335			`@(posedge CLK_I) ;`
336
337			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
338			`if ( ok !== 1 )`
339			`begin`
340			`$display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;`
341			return`TB_ERROR_BIT = 1'b1 ;
342			`disable main ;`
343			`end`
344
345			`// first insert initial wait states`
346			cyc_count = read_flags`INIT_WAITS ;
347			`while ( cyc_count > 0 )`
348			`begin`
349			`@(posedge CLK_I) ;`
350			`cyc_count = cyc_count - 1 ;`
351			`end`
352
353			`wbm_low_level.wbm_read(read_data, return) ;`
354
355			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
356			`begin`
357			if ( rty_count === `WB_TB_MAX_RTY )
358			`begin`
359			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;`
360			`retry = 0 ;`
361			`end`
362			`else`
363			`begin`
364			`retry = 1 ;`
365			`rty_count = rty_count + 1 ;`
366			`end`
367			`end`
368			`else`
369			`begin`
370			`retry = 0 ;`
371			`end`
372
373			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
374			if ( return`TB_ERROR_BIT !== 0 )
375			`begin`
376			`@(posedge CLK_I) ;`
377			`wbm_low_level.end_cycle ;`
378			`disable main ;`
379			`end`
380
381			cyc_count = read_flags`SUBSEQ_WAITS ;
382			`while ( cyc_count > 0 )`
383			`begin`
384			`@(posedge CLK_I) ;`
385			`cyc_count = cyc_count - 1 ;`
386			`end`
387
388			`if (retry === 1)`
389			`wbm_low_level.end_cycle ;`
390			`else`
391			`wbm_low_level.modify_cycle ;`
392			`end`
393
394			`in_use = 0 ;`
395
396			`end //main`
397			`endtask // wb_RMW_read`
398
399			`task wb_RMW_write ;`
400			input `WRITE_STIM_TYPE write_data ;
401			input `WB_TRANSFER_FLAGS write_flags ;
402			inout `WRITE_RETURN_TYPE return ;
403			`reg in_use ;`
404			`reg cab ;`
405			`reg ok ;`
406			`integer cyc_count ;`
407			`integer rty_count ;`
408			`reg retry ;`
409			`begin:main`
410
411			return`TB_ERROR_BIT = 1'b0 ;
412			`cab = 0 ;`
413			return`CYC_ACTUAL_TRANSFER = 0 ;
414			`rty_count = 0 ;`
415
416			`// check if task was called before previous call finished`
417			`if ( in_use === 1 )`
418			`begin`
419			`$display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;`
420			return`TB_ERROR_BIT = 1'b1 ;
421			`disable main ;`
422			`end`
423
424			`in_use = 1 ;`
425
426			`retry = 1 ;`
427
428			`while (retry === 1)`
429			`begin`
430			`// synchronize operation to clock`
431			`//@(posedge CLK_I) ;`
432			`ok = 1 ;`
433			`if (rty_count !== 0)`
434			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
435
436			`if ( ok !== 1 )`
437			`begin`
438			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
439			return`TB_ERROR_BIT = 1'b1 ;
440			`disable main ;`
441			`end`
442
443			`// first insert initial wait states`
444			cyc_count = write_flags`INIT_WAITS ;
445			`while ( cyc_count > 0 )`
446			`begin`
447			`@(posedge CLK_I) ;`
448			`cyc_count = cyc_count - 1 ;`
449			`end`
450
451			`wbm_low_level.wbm_write(write_data, return) ;`
452
453			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
454			`begin`
455			if ( rty_count === `WB_TB_MAX_RTY )
456			`begin`
457			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
458			`retry = 0 ;`
459			`end`
460			`else`
461			`begin`
462			`retry = 1 ;`
463			`rty_count = rty_count + 1 ;`
464			`end`
465			`end`
466			`else`
467			`retry = 0 ;`
468
469			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
470			if ( return`TB_ERROR_BIT !== 0 )
471			`begin`
472			`@(posedge CLK_I) ;`
473			`wbm_low_level.end_cycle ;`
474			`disable main ;`
475			`end`
476
477			cyc_count = write_flags`SUBSEQ_WAITS ;
478			`while ( cyc_count > 0 )`
479			`begin`
480			`@(posedge CLK_I) ;`
481			`cyc_count = cyc_count - 1 ;`
482			`end`
483
484			`wbm_low_level.end_cycle ;`
485			`end`
486
487			`in_use = 0 ;`
488
489			`end //main`
490			`endtask // wb_RMW_write`
491
492			`task wb_block_write ;`
493			input `WB_TRANSFER_FLAGS write_flags ;
494			inout `WRITE_RETURN_TYPE return ;
495
496			`reg in_use ;`
497			reg `WRITE_STIM_TYPE current_write ;
498			`reg cab ;`
499			`reg ok ;`
500			`integer cyc_count ;`
501			`integer rty_count ;`
502			`reg end_blk ;`
503			`begin:main`
504
505			return`CYC_ACTUAL_TRANSFER = 0 ;
506			`rty_count = 0 ;`
507
508			`// check if task was called before previous call finished`
509			`if ( in_use === 1 )`
510			`begin`
511			`$display("*E, wb_block_write routine re-entered! Time %t ", $time) ;`
512			return`TB_ERROR_BIT = 1'b1 ;
513			`disable main ;`
514			`end`
515
516			if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
517			`begin`
518			`$display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;`
519			return`TB_ERROR_BIT = 1'b1 ;
520			`disable main ;`
521			`end`
522
523			`in_use = 1 ;`
524			`@(posedge CLK_I) ;`
525			cab = write_flags`WB_TRANSFER_CAB ;
526			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
527			`if ( ok !== 1 )`
528			`begin`
529			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
530			return`TB_ERROR_BIT = 1'b1 ;
531			`disable main ;`
532			`end`
533
534			`// insert initial wait states`
535			cyc_count = write_flags`INIT_WAITS ;
536			`while ( cyc_count > 0 )`
537			`begin`
538			`@(posedge CLK_I) ;`
539			`cyc_count = cyc_count - 1 ;`
540			`end`
541
542			`end_blk = 0 ;`
543			`while (end_blk === 0)`
544			`begin`
545			`// collect data for current data beat`
546			current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
547			`wbm_low_level.wbm_write(current_write, return) ;`
548
549			`// check result of write operation`
550			`// check for severe test error`
551			if (return`TB_ERROR_BIT !== 0)
552			`begin`
553			`@(posedge CLK_I) ;`
554			`wbm_low_level.end_cycle ;`
555			`disable main ;`
556			`end`
557
558			`// slave returned error or error signal had invalid value`
559			if (return`CYC_ERR !== 0)
560			`end_blk = 1 ;`
561
562			`if (`
563			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
564			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
565			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
566			`)`
567			`begin`
568			`end_blk = 1 ;`
569			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;`
570			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
571			`end`
572
573			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
574			`end_blk = 1 ;`
575
576			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
577			`begin`
578			if ( rty_count === `WB_TB_MAX_RTY )
579			`begin`
580			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;`
581			`end_blk = 1 ;`
582			`end`
583			`else`
584			`begin`
585			`rty_count = rty_count + 1 ;`
586			`end`
587			`end`
588			`else`
589			`rty_count = 0 ;`
590
591			`// check if slave responded at all`
592			if (return`CYC_RESPONSE === 0)
593			`end_blk = 1 ;`
594
595			`// check if all intended data was transfered`
596			if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
597			`end_blk = 1 ;`
598
599			`// insert subsequent wait cycles, if transfer is supposed to continue`
600			`if ( end_blk === 0 )`
601			`begin`
602			cyc_count = write_flags`SUBSEQ_WAITS ;
603			`while ( cyc_count > 0 )`
604			`begin`
605			`@(posedge CLK_I) ;`
606			`cyc_count = cyc_count - 1 ;`
607			`end`
608			`end`
609
610			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
611			`begin`
612			`wbm_low_level.end_cycle ;`
613			`@(posedge CLK_I) ;`
614			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
615			`if ( ok !== 1 )`
616			`begin`
617			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
618			return`TB_ERROR_BIT = 1'b1 ;
619			`end_blk = 1 ;`
620			`end`
621			`end`
622			`end //while`
623
624			`wbm_low_level.end_cycle ;`
625			`in_use = 0 ;`
626			`end //main`
627			`endtask //wb_block_write`
628
629			`task wb_block_read ;`
630			input `WB_TRANSFER_FLAGS read_flags ;
631			inout `READ_RETURN_TYPE return ;
632
633			`reg in_use ;`
634			reg `READ_STIM_TYPE current_read ;
635			`reg cab ;`
636			`reg ok ;`
637			`integer cyc_count ;`
638			`integer rty_count ;`
639			`reg end_blk ;`
640			`integer transfered ;`
641			`begin:main`
642
643			return`CYC_ACTUAL_TRANSFER = 0 ;
644			`transfered = 0 ;`
645			`rty_count = 0 ;`
646
647			`// check if task was called before previous call finished`
648			`if ( in_use === 1 )`
649			`begin`
650			`$display("*E, wb_block_read routine re-entered! Time %t ", $time) ;`
651			return`TB_ERROR_BIT = 1'b1 ;
652			`disable main ;`
653			`end`
654
655			if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
656			`begin`
657			`$display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;`
658			return`TB_ERROR_BIT = 1'b1 ;
659			`disable main ;`
660			`end`
661
662			`in_use = 1 ;`
663			`@(posedge CLK_I) ;`
664			cab = read_flags`WB_TRANSFER_CAB ;
665
666			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
667
668			`if ( ok !== 1 )`
669			`begin`
670			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
671			return`TB_ERROR_BIT = 1'b1 ;
672			`disable main ;`
673			`end`
674
675			`// insert initial wait states`
676			cyc_count = read_flags`INIT_WAITS ;
677			`while ( cyc_count > 0 )`
678			`begin`
679			`@(posedge CLK_I) ;`
680			`cyc_count = cyc_count - 1 ;`
681			`end`
682
683			`end_blk = 0 ;`
684			`while (end_blk === 0)`
685			`begin`
686			`// collect data for current data beat`
687			current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
688
689			`wbm_low_level.wbm_read(current_read, return) ;`
690
691			if ( transfered !== return`CYC_ACTUAL_TRANSFER )
692			`begin`
693			`blk_read_data_out[transfered] = return ;`
694			transfered = return`CYC_ACTUAL_TRANSFER ;
695			`end`
696
697			`// check result of read operation`
698			`// check for severe test error`
699			if (return`TB_ERROR_BIT !== 0)
700			`begin`
701			`@(posedge CLK_I) ;`
702			`wbm_low_level.end_cycle ;`
703			`disable main ;`
704			`end`
705
706			`// slave returned error or error signal had invalid value`
707			if (return`CYC_ERR !== 0)
708			`end_blk = 1 ;`
709
710			`if (`
711			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
712			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
713			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
714			`)`
715			`begin`
716			`end_blk = 1 ;`
717			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;`
718			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
719			`end`
720
721			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
722			`end_blk = 1 ;`
723
724			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
725			`begin`
726			if ( rty_count === `WB_TB_MAX_RTY )
727			`begin`
728			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;`
729			`end_blk = 1 ;`
730			`end`
731			`else`
732			`begin`
733			`rty_count = rty_count + 1 ;`
734			`end`
735			`end`
736			`else`
737			`rty_count = 0 ;`
738
739			`// check if slave responded at all`
740			if (return`CYC_RESPONSE === 0)
741			`end_blk = 1 ;`
742
743			`// check if all intended data was transfered`
744			if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
745			`end_blk = 1 ;`
746
747			`// insert subsequent wait cycles, if transfer is supposed to continue`
748			`if ( end_blk === 0 )`
749			`begin`
750			cyc_count = read_flags`SUBSEQ_WAITS ;
751			`while ( cyc_count > 0 )`
752			`begin`
753			`@(posedge CLK_I) ;`
754			`cyc_count = cyc_count - 1 ;`
755			`end`
756			`end`
757
758			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
759			`begin`
760			`wbm_low_level.end_cycle ;`
761			`@(posedge CLK_I) ;`
762			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
763			`if ( ok !== 1 )`
764			`begin`
765			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
766			return`TB_ERROR_BIT = 1'b1 ;
767			`end_blk = 1 ;`
768			`end`
769			`end`
770			`end //while`
771
772			`wbm_low_level.end_cycle ;`
773			`in_use = 0 ;`
774			`end //main`
775			`endtask //wb_block_read`
776
777			`endmodule`
778