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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%% %%%%
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%%%% WISHBONE SD Card Controller IP Core %%%%
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%%%% %%%%
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%%%% hdl_if.tex %%%%
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%%%% %%%%
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%%%% This file is part of the WISHBONE SD Card %%%%
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%%%% Controller IP Core project %%%%
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%%%% http://www.opencores.org/cores/xxx/ %%%%
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%%%% %%%%
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%%%% Description %%%%
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%%%% documentation 'HDL interface' chapter %%%%
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%%%% %%%%
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%%%% Author(s): %%%%
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%%%% - Marek Czerski, ma.czerski@gmail.com %%%%
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%%%% %%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%% %%%%
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%%%% Copyright (C) 2013 Authors %%%%
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%%%% %%%%
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%%%% This source file may be used and distributed without %%%%
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%%%% restriction provided that this copyright statement is not %%%%
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%%%% removed from the file and that any derivative work contains %%%%
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%%%% the original copyright notice and the associated disclaimer. %%%%
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%%%% %%%%
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%%%% This source file is free software; you can redistribute it %%%%
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%%%% and/or modify it under the terms of the GNU Lesser General %%%%
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%%%% Public License as published by the Free Software Foundation; %%%%
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%%%% either version 2.1 of the License, or (at your option) any %%%%
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%%%% later version. %%%%
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%%%% %%%%
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%%%% This source is distributed in the hope that it will be %%%%
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%%%% useful, but WITHOUT ANY WARRANTY; without even the implied %%%%
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%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR %%%%
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%%%% PURPOSE. See the GNU Lesser General Public License for more %%%%
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%%%% details. %%%%
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%%%% %%%%
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%%%% You should have received a copy of the GNU Lesser General %%%%
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%%%% Public License along with this source; if not, download it %%%%
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%%%% from http://www.opencores.org/lgpl.shtml %%%%
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%%%% %%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{HDL interface}
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\label{sec:hdl_if}
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IP core has very simple interface:
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\begin{figure}[H]
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\centering
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\includegraphics[width=11cm]{../bin/ip_core_if.png}
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% ip_core.png: 384x469 pixel, 96dpi, 10.16x12.41 cm, bb=
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\caption{Wishbone SD Card Controller IP Core interface}
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\label{img:ip_core_if}
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\end{figure}
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Wishbone slave interface provides access from CPU to all IP core registers (see \ref{sec:regs}). It must
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be connected to CPU data master. Wishbone master interface provides access for DMA engine to RAM (see \ref{sec:dma}).
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It must be connected to RAM memory slave. Interrupts signals provides mechanism to notify the CPU about finished transactions (data and command tranfers).
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They are not necesary for proper operation (if You don't want to use interrupts). MMC/SD card interface provides communication with external MMC/SD cards.
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It must be connected to external pins of the FPGA wich are connected to MMC/SD card connector. Because those external pins are bidirectional, IP core
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provides inputs, outputs and output enables for these signals.
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Table \ref{tab:singals} presents all IP core signals with descriptions.
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\begin{table}
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\caption{Signals description}
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\begin{center}
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\begin{tabular}{l|l|l|l}
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\rowcolor[gray]{0.7} name & direction & width & description \\ \hline \hline
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\multicolumn{4}{c}{Wishbone common signals} \\ \hline
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\texttt{wb\_clk\_i} & input & 1 & clock for both master and slave wishbone transactions \\ \hline
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\texttt{wb\_rst\_i} & input & 1 & reset for whole IP core \\ \hline
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\multicolumn{4}{c}{Wishbone slave signals} \\ \hline
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\texttt{wb\_dat\_i} & input & 32 & data input \\ \hline
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\texttt{wb\_dat\_o} & output & 32 & data output \\ \hline
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\texttt{wb\_adr\_i} & input & 32 & address \\ \hline
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\texttt{wb\_sel\_i} & input & 4 & byte select \\ \hline
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\texttt{wb\_we\_i} & input & 1 & write enable \\ \hline
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\texttt{wb\_cyc\_i} & input & 1 & cycle flag \\ \hline
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\texttt{wb\_stb\_i} & input & 1 & strobe \\ \hline
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\texttt{wb\_ack\_o} & output & 1 & acknowledge flag \\ \hline
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\multicolumn{4}{c}{Wishbone master signals} \\ \hline
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\texttt{m\_wb\_dat\_o} & output & 32 & data output \\ \hline
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\texttt{m\_wb\_dat\_i} & input & 32 & data input \\ \hline
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\texttt{m\_wb\_adr\_o} & output & 32 & address \\ \hline
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\texttt{m\_wb\_sel\_o} & output & 4 & byte select \\ \hline
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\texttt{m\_wb\_we\_o} & output & 1 & write enable \\ \hline
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\texttt{m\_wb\_cyc\_o} & output & 1 & cycle flag \\ \hline
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\texttt{m\_wb\_stb\_o} & output & 1 & strobe \\ \hline
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\texttt{m\_wb\_ack\_i} & input & 1 & acknowledge flag \\ \hline
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\texttt{m\_wb\_cti\_o} & output & 3 & cycle type identifier (always 000) \\ \hline
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\texttt{m\_wb\_bte\_o} & output & 2 & burst type (always 00) \\ \hline
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\multicolumn{4}{c}{MMC/SD signals} \\ \hline
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\texttt{sd\_cmd\_dat\_i} & input & 1 & command line input \\ \hline
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\texttt{sd\_cmd\_out\_o} & output & 1 & command line output \\ \hline
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\texttt{sd\_cmd\_oe\_o} & output & 1 & command line output enable \\ \hline
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\texttt{sd\_dat\_dat\_i} & input & 4 & data line inputs \\ \hline
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\texttt{sd\_dat\_out\_o} & output & 4 & data line outputs \\ \hline
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\texttt{sd\_dat\_oe\_o} & output & 1 & data line outputs enable \\ \hline
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\texttt{sd\_clk\_o\_pad} & output & 1 & clock for external MMC/SD card \\ \hline
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\texttt{sd\_clk\_i\_pad} & input & 1 & clock for MMC/SD interface \\ \hline
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\multicolumn{4}{c}{Interrupts} \\ \hline
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\texttt{int\_cmd} & output & 1 & command transaction finished interrupt \\ \hline
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\texttt{int\_data} & output & 1 & data transaction finished interrupt \\ \hline
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\hline
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\end{tabular}
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\label{tab:singals}
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\end{center}
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\end{table}
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\subsection{Clock consideration}
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\label{sec:clock}
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IP core needs two clock sources. First one is for Wishbone bus operation (\texttt{wb\_clk\_i}). There are no constraints for this clock.
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Second one is for MMC/SD interface operation (\texttt{sd\_clk\_i\_pad}).
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\texttt{sd\_clk\_i\_pad} is used to drive \texttt{sd\_clk\_o\_pad} output, which is the external MMC/SD card clock source, through internal
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clock devider. This clock devider is able to devide \texttt{sd\_clk\_i\_pad} clock by 2, 4, 6, 8, ... etc. (2*n where n = [1..256]).
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\texttt{sd\_clk\_o\_pad} clock frequency depends on MMC/SD specification. To fully utilize the transmission bandwidth \texttt{sd\_clk\_o\_pad}
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should be able to perform at 25MHz frequency which imposes constraint of minimum 50MHz on \texttt{sd\_clk\_i\_pad} clock.
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Clock inputs \texttt{wb\_clk\_i} and \texttt{sd\_clk\_i\_pad} can be sourced by the same signal.
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\subsection{DMA engine}
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\label{sec:dma}
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DMA engine is used to lower the CPU usage during data transactions\footnote{Data transaction refers to any traffic on the data lines of MMC/SD card interface.}.
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DMA starts its operation imidiately after succesful end of any read or write command transactions\footnote{Command transaction refers to any traffic on the command line.}
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\footnote{Read or write command refer to command with data payload such as \textit{block read}(CMD17) or \textit{block write}(CMD24).}.
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During write transactions, data is fetched from RAM automatically, starting from known address. This addres has to be configured by the CPU before sending any write command.
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Similarly, during read transactions, data is written to RAM automatically, starting from known address.
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This address also has to be configured by the CPU before sending any read command. Because data transmission is half-duplex,
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read and write addresses are placed in the same configuration register. Function of this register depends on the command to be sent.
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\subsection{Interrupt generation}
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\label{sec:interrupt}
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Interrupts are useful when polling technique is not an option. There are two interrupt sources. One to notify the end of the commans transaction (\texttt{int\_cmd} signal) and
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one to notify the end of the data transaction (\texttt{int\_data} signal). Both interrupts has active high logic. All events that triger each interrupts can be masked(see \ref{sec:regs})
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and therefore, do not participate in interrupt generation(see \ref{img:events}).
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\begin{figure}[H]
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\centering
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\includegraphics[width=11cm]{../bin/events.png}
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% ip_core.png: 384x469 pixel, 96dpi, 10.16x12.41 cm, bb=
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\caption{Interrupt generation scheme}
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\label{img:events}
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\end{figure}
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\subsubsection{Command transaction events}
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\label{sec:cmd_events}
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Command transaction end interrupt is driven by the command transaction events. The events are:
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\begin{description}
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\item[completion] - transaction completed succesfuly,
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\item[error] - transaction completed with error (one or more of the following events occured),
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\item[timeout] - timeout error (the card did not respond in a timely fashion),
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\item[wrong crc] - crc check error (crc calculated from received response data did not match to the crc field of the response),
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\item[wrong index] - index check error (response consists of wrong index field value).
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\end{description}
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\subsubsection{Data transaction events}
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\label{sec:data_events}
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Data transaction end interrupt is driven by the data transaction events. The events are:
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\begin{description}
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\item[completion] - transaction completed succesfuly,
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\item[wrong crc] - crc check error (in case of write transaction, crc received in response to write transaction was different than one calculated by the core;
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in case of read transaction, crc calculated from received data did not match to the crc field of received data),
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\item[fifo error] - internal fifo error (in case of write transaction, tx fifo became empty before all data was send; in case of read transaction, rx fifo became
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full; both cases are caused by to slow wishbone bus or wishbone bus been busy for to long)).
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\end{description}
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