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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%% %%%%
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%%%% WISHBONE SD Card Controller IP Core %%%%
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%%%% %%%%
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%%%% sw_if.tex %%%%
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%%%% %%%%
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%%%% This file is part of the WISHBONE SD Card %%%%
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%%%% Controller IP Core project %%%%
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%%%% http://www.opencores.org/cores/xxx/ %%%%
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%%%% %%%%
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%%%% Description %%%%
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%%%% documentation 'Software interface' chapter %%%%
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%%%% %%%%
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%%%% Author(s): %%%%
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%%%% - Marek Czerski, ma.czerski@gmail.com %%%%
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%%%% %%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%% %%%%
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%%%% Copyright (C) 2013 Authors %%%%
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%%%% %%%%
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%%%% This source file may be used and distributed without %%%%
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%%%% restriction provided that this copyright statement is not %%%%
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%%%% removed from the file and that any derivative work contains %%%%
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%%%% the original copyright notice and the associated disclaimer. %%%%
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%%%% %%%%
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%%%% This source file is free software; you can redistribute it %%%%
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%%%% and/or modify it under the terms of the GNU Lesser General %%%%
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%%%% Public License as published by the Free Software Foundation; %%%%
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%%%% either version 2.1 of the License, or (at your option) any %%%%
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%%%% later version. %%%%
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%%%% %%%%
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%%%% This source is distributed in the hope that it will be %%%%
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%%%% useful, but WITHOUT ANY WARRANTY; without even the implied %%%%
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%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR %%%%
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%%%% PURPOSE. See the GNU Lesser General Public License for more %%%%
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%%%% details. %%%%
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%%%% %%%%
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%%%% You should have received a copy of the GNU Lesser General %%%%
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%%%% Public License along with this source; if not, download it %%%%
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%%%% from http://www.opencores.org/lgpl.shtml %%%%
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%%%% %%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Software interface}
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\label{sec:sw_if}
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Access to IP core registers is provided through Wishbone slave interface.
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\subsection{IP Core registers}
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\label{sec:regs}
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\begin{table}[H]
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\caption{List of registers}
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\begin{tabular}{l|l|l|l}
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\rowcolor[gray]{0.7} name & address & access & description \\ \hline \hline
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\texttt{argument} & \texttt{0x00} & RW & command argument \\ \hline
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\texttt{command} & \texttt{0x04} & RW & command transaction configuration \\ \hline
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\texttt{response0} & \texttt{0x08} & R & bits 31-0 of the response \\ \hline
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\texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
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\texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
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\texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
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\texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
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\texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
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\texttt{clock\_devider} & \texttt{0x24} & RW & MMC/SD interface clock devider \\ \hline
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\texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
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\texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
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\texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
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\texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
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\texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
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\texttt{data\_event\_status} & \texttt{0x3C} & RW & data transaction events status / clear \\ \hline
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\texttt{data\_event\_enable} & \texttt{0x38} & RW & data transaction events enable \\ \hline
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\texttt{blkock\_size} & \texttt{0x44} & RW & read / write block transfer size \\ \hline
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\texttt{blkock\_count} & \texttt{0x48} & RW & read / write block count \\ \hline
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\texttt{dst\_src\_address} & \texttt{0x60} & RW & DMA destination / source address \\ \hline
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\hline
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\end{tabular}
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\label{tab:registers}
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\end{table}
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\subsubsection{Argument register}
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\label{sec:arg_reg}
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Write operation to this register triggers command transaction (command register has to be configured before writing to this register).
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\begin{table}[H]
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\caption{Argument register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:0]} & \texttt{0x00000000} & RW & command argument value. \\ \hline
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\hline
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\end{tabular}
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\label{tab:arg_reg}
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\end{table}
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\subsubsection{Command register}
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\label{sec:cmd_reg}
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This register configures all aspects of command to be sent.
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\begin{table}[H]
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\caption{Command register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:14]} & & & reserved \\ \hline
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\texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
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\texttt{[7]} & & & reserved \\ \hline
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\texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
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0x2 - triggers write data transaction after command transaction\\ \hline
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\texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
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\texttt{[3]} & \texttt{0x0} & RW & check response crc \\ \hline
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\texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,
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core will wait for as long as busy signal remains) \\ \hline
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\texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
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0x2 - wait for long response (136-bits) \\ \hline
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\hline
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\end{tabular}
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\label{tab:cmd_reg}
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\end{table}
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\subsubsection{Response register 0-3}
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\label{sec:resp_reg}
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Response registers 0-3 contains response data bits after end of succesful command transaction (if bits 1-0 of command register were configured to wait for response).
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\begin{table}[H]
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\caption{Response register 0-3}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:0]} & \texttt{0x00000000} & R & response data bits \\ \hline
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\hline
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\end{tabular}
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\label{tab:resp_reg}
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\end{table}
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\subsubsection{Control register}
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\label{sec:control_reg}
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\begin{table}[H]
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\caption{Control register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:1]} & & & reserved \\ \hline
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\texttt{[0]} & \texttt{0x0} & RW & MMC/SD bus width; 0x0 - 1-bit operation; 0x1 - 4-bit operation \\ \hline
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\hline
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\end{tabular}
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\label{tab:control_reg}
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\end{table}
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\subsubsection{Timeout register}
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\label{sec:timeout_reg}
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Timeout register configures transaction watchdog counter. If any transaction will last longer than configured timeout, interrupt will be generated.
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Value in timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cyckles. Register value is calculated by following formula:
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\begin{equation}
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REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_devider} + 1))}
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\end{equation}
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\begin{table}[H]
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\caption{Timeout register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:16]} & & & reserved \\ \hline
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\texttt{[15:0]} & \texttt{0x0} & RW & timeout value \\ \hline
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\hline
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\end{tabular}
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\label{tab:timeout_reg}
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\end{table}
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\subsubsection{Clock devider register}
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\label{sec:div_reg}
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Clock devider register control division of \texttt{sd\_clk\_i\_pad} signal frequency. Output of this devider is routed to MMC/SD interface clock domain.
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Register value is calculated by following formula:
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\begin{equation}
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REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
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\end{equation}
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\begin{table}[H]
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\caption{Clock devider register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:8]} & & & reserved \\ \hline
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\texttt{[7:0]} & \texttt{0x0} & RW & devider ratio \\ \hline
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\hline
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\end{tabular}
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\label{tab:div_reg}
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\end{table}
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\subsubsection{Software reset register}
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\label{sec:reset_reg}
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\begin{table}[H]
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\caption{Software reset register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:1]} & & & reserved \\ \hline
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\texttt{[0]} & \texttt{0x0} & RW & reset; 0x0 - no reset; 0x1 - reset applied \\ \hline
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\hline
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\end{tabular}
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\label{tab:reset_reg}
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\end{table}
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\subsubsection{Voltage information register}
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\label{sec:voltage_reg}
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\begin{table}[H]
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\caption{Software reset register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:0]} & & & reserved \\ \hline
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\hline
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\end{tabular}
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\label{tab:voltage_reg}
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\end{table}
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\subsubsection{Capabilities information register}
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\label{sec:capa_reg}
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\begin{table}[H]
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\caption{Capabilities information register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:0]} & & & reserved \\ \hline
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\hline
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\end{tabular}
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\label{tab:capa_reg}
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\end{table}
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\subsubsection{Command events status register}
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\label{sec:cmd_evt_reg}
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This register holds all pending event flags related to command transactions. Write operation to this register
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clears all flags.
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\begin{table}[H]
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\caption{Command events status register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:5]} & & & reserved \\ \hline
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\texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
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\texttt{[3]} & \texttt{0x0} & RW & crc error event \\ \hline
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\texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
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\texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
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\texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
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\hline
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\end{tabular}
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\label{tab:cmd_evt_reg}
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\end{table}
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\subsubsection{Command transaction events enable register}
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\label{sec:cmd_ena_reg}
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This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
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\begin{table}[H]
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\caption{Command transaction events enable register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:5]} & & & reserved \\ \hline
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\texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
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\texttt{[3]} & \texttt{0x0} & RW & enable crc error event \\ \hline
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\texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
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\texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
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\texttt{[0]} & \texttt{0x0} & RW & enable command transaction succesful completion event \\ \hline
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\hline
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\end{tabular}
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\label{tab:cmd_ena_reg}
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\end{table}
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\subsubsection{Data transaction events status register}
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\label{sec:data_evt_reg}
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This register holds all pending event flags related to data transactions. Write operation to this register
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clears all flags.
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\begin{table}[H]
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\caption{Data transaction events status register}
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\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
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\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
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\texttt{[31:3]} & & & reserved \\ \hline
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\texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
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\texttt{[1]} & \texttt{0x0} & RW & crc error event \\ \hline
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\texttt{[0]} & \texttt{0x0} & RW & data transaction succesful completion event \\ \hline
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\hline
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\end{tabular}
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\label{tab:data_evt_reg}
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\end{table}
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\subsubsection{Data transaction events enable register}
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\label{sec:data_ena_reg}
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|
|
| 292 |
|
|
This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
|
| 293 |
|
|
|
| 294 |
|
|
\begin{table}[H]
|
| 295 |
|
|
\caption{Data transaction events enable register}
|
| 296 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 297 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 298 |
|
|
\texttt{[31:3]} & & & reserved \\ \hline
|
| 299 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
|
| 300 |
|
|
\texttt{[1]} & \texttt{0x0} & RW & enable crc error event \\ \hline
|
| 301 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & enable data transaction succesful completion event \\ \hline
|
| 302 |
|
|
\hline
|
| 303 |
|
|
\end{tabular}
|
| 304 |
|
|
\label{tab:data_ena_reg}
|
| 305 |
|
|
\end{table}
|
| 306 |
|
|
|
| 307 |
|
|
\subsubsection{Block size register}
|
| 308 |
|
|
\label{sec:blocksize_reg}
|
| 309 |
|
|
|
| 310 |
|
|
This register controls the number of bytes to write/read in a single block. Data transaction will transmit number of bytes equal to value of this register times value
|
| 311 |
|
|
of \texttt{blkock\_count} register.
|
| 312 |
|
|
|
| 313 |
|
|
\begin{table}[H]
|
| 314 |
|
|
\caption{Block size register}
|
| 315 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 316 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 317 |
|
|
\texttt{[31:12]} & & & reserved \\ \hline
|
| 318 |
|
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of byes in a single block \\ \hline
|
| 319 |
|
|
\hline
|
| 320 |
|
|
\end{tabular}
|
| 321 |
|
|
\label{tab:blocksize_reg}
|
| 322 |
|
|
\end{table}
|
| 323 |
|
|
|
| 324 |
|
|
\subsubsection{Block count register}
|
| 325 |
|
|
\label{sec:blockcnt_reg}
|
| 326 |
|
|
|
| 327 |
|
|
This register controls the number of blocks to write/read in data transaction. Data transaction will transmit number of bytes equal to value of this register times value
|
| 328 |
|
|
of \texttt{blkock\_size} register.
|
| 329 |
|
|
|
| 330 |
|
|
\begin{table}[H]
|
| 331 |
|
|
\caption{Block count register}
|
| 332 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 333 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 334 |
|
|
\texttt{[31:12]} & & & reserved \\ \hline
|
| 335 |
|
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of blocks in data transaction \\ \hline
|
| 336 |
|
|
\hline
|
| 337 |
|
|
\end{tabular}
|
| 338 |
|
|
\label{tab:blockcnt_reg}
|
| 339 |
|
|
\end{table}
|
| 340 |
|
|
|
| 341 |
|
|
\subsubsection{DMA destination / source register}
|
| 342 |
|
|
\label{sec:dst_src_reg}
|
| 343 |
|
|
|
| 344 |
|
|
This registers configures the DMA source / destination address. For write transactions, this address points to the begining of data block to be sent.
|
| 345 |
|
|
For read transactions, this address points to the begining of data block to be written.
|
| 346 |
|
|
|
| 347 |
|
|
\begin{table}[H]
|
| 348 |
|
|
\caption{DMA destination / source register}
|
| 349 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 350 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 351 |
|
|
\texttt{[31:o]} & 0x00000000 & RW & address \\ \hline
|
| 352 |
|
|
\hline
|
| 353 |
|
|
\end{tabular}
|
| 354 |
|
|
\label{tab:dst_src_reg}
|
| 355 |
|
|
\end{table}
|
| 356 |
|
|
|
