| 1 |
3 |
rozpruwacz |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 2 |
|
|
%%%% %%%%
|
| 3 |
|
|
%%%% WISHBONE SD Card Controller IP Core %%%%
|
| 4 |
|
|
%%%% %%%%
|
| 5 |
|
|
%%%% sw_if.tex %%%%
|
| 6 |
|
|
%%%% %%%%
|
| 7 |
|
|
%%%% This file is part of the WISHBONE SD Card %%%%
|
| 8 |
|
|
%%%% Controller IP Core project %%%%
|
| 9 |
8 |
rozpruwacz |
%%%% http://opencores.org/project,sd_card_controller %%%%
|
| 10 |
3 |
rozpruwacz |
%%%% %%%%
|
| 11 |
|
|
%%%% Description %%%%
|
| 12 |
|
|
%%%% documentation 'Software interface' chapter %%%%
|
| 13 |
|
|
%%%% %%%%
|
| 14 |
|
|
%%%% Author(s): %%%%
|
| 15 |
|
|
%%%% - Marek Czerski, ma.czerski@gmail.com %%%%
|
| 16 |
|
|
%%%% %%%%
|
| 17 |
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 18 |
|
|
%%%% %%%%
|
| 19 |
|
|
%%%% Copyright (C) 2013 Authors %%%%
|
| 20 |
|
|
%%%% %%%%
|
| 21 |
|
|
%%%% This source file may be used and distributed without %%%%
|
| 22 |
|
|
%%%% restriction provided that this copyright statement is not %%%%
|
| 23 |
|
|
%%%% removed from the file and that any derivative work contains %%%%
|
| 24 |
|
|
%%%% the original copyright notice and the associated disclaimer. %%%%
|
| 25 |
|
|
%%%% %%%%
|
| 26 |
|
|
%%%% This source file is free software; you can redistribute it %%%%
|
| 27 |
|
|
%%%% and/or modify it under the terms of the GNU Lesser General %%%%
|
| 28 |
|
|
%%%% Public License as published by the Free Software Foundation; %%%%
|
| 29 |
|
|
%%%% either version 2.1 of the License, or (at your option) any %%%%
|
| 30 |
|
|
%%%% later version. %%%%
|
| 31 |
|
|
%%%% %%%%
|
| 32 |
|
|
%%%% This source is distributed in the hope that it will be %%%%
|
| 33 |
|
|
%%%% useful, but WITHOUT ANY WARRANTY; without even the implied %%%%
|
| 34 |
|
|
%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR %%%%
|
| 35 |
|
|
%%%% PURPOSE. See the GNU Lesser General Public License for more %%%%
|
| 36 |
|
|
%%%% details. %%%%
|
| 37 |
|
|
%%%% %%%%
|
| 38 |
|
|
%%%% You should have received a copy of the GNU Lesser General %%%%
|
| 39 |
|
|
%%%% Public License along with this source; if not, download it %%%%
|
| 40 |
|
|
%%%% from http://www.opencores.org/lgpl.shtml %%%%
|
| 41 |
|
|
%%%% %%%%
|
| 42 |
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 43 |
|
|
\section{Software interface}
|
| 44 |
|
|
\label{sec:sw_if}
|
| 45 |
|
|
|
| 46 |
|
|
Access to IP core registers is provided through Wishbone slave interface.
|
| 47 |
|
|
|
| 48 |
|
|
\subsection{IP Core registers}
|
| 49 |
|
|
\label{sec:regs}
|
| 50 |
|
|
|
| 51 |
|
|
\begin{table}[H]
|
| 52 |
|
|
\caption{List of registers}
|
| 53 |
|
|
\begin{tabular}{l|l|l|l}
|
| 54 |
|
|
\rowcolor[gray]{0.7} name & address & access & description \\ \hline \hline
|
| 55 |
|
|
\texttt{argument} & \texttt{0x00} & RW & command argument \\ \hline
|
| 56 |
|
|
\texttt{command} & \texttt{0x04} & RW & command transaction configuration \\ \hline
|
| 57 |
|
|
\texttt{response0} & \texttt{0x08} & R & bits 31-0 of the response \\ \hline
|
| 58 |
|
|
\texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
|
| 59 |
|
|
\texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
|
| 60 |
|
|
\texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
|
| 61 |
|
|
\texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
|
| 62 |
|
|
\texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
|
| 63 |
|
|
\texttt{clock\_devider} & \texttt{0x24} & RW & MMC/SD interface clock devider \\ \hline
|
| 64 |
|
|
\texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
|
| 65 |
|
|
\texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
|
| 66 |
|
|
\texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
|
| 67 |
|
|
\texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
|
| 68 |
|
|
\texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
|
| 69 |
|
|
\texttt{data\_event\_status} & \texttt{0x3C} & RW & data transaction events status / clear \\ \hline
|
| 70 |
|
|
\texttt{data\_event\_enable} & \texttt{0x38} & RW & data transaction events enable \\ \hline
|
| 71 |
|
|
\texttt{blkock\_size} & \texttt{0x44} & RW & read / write block transfer size \\ \hline
|
| 72 |
|
|
\texttt{blkock\_count} & \texttt{0x48} & RW & read / write block count \\ \hline
|
| 73 |
|
|
\texttt{dst\_src\_address} & \texttt{0x60} & RW & DMA destination / source address \\ \hline
|
| 74 |
|
|
\hline
|
| 75 |
|
|
\end{tabular}
|
| 76 |
|
|
\label{tab:registers}
|
| 77 |
|
|
\end{table}
|
| 78 |
|
|
|
| 79 |
|
|
\subsubsection{Argument register}
|
| 80 |
|
|
\label{sec:arg_reg}
|
| 81 |
|
|
|
| 82 |
|
|
Write operation to this register triggers command transaction (command register has to be configured before writing to this register).
|
| 83 |
|
|
|
| 84 |
|
|
\begin{table}[H]
|
| 85 |
|
|
\caption{Argument register}
|
| 86 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 87 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 88 |
|
|
\texttt{[31:0]} & \texttt{0x00000000} & RW & command argument value. \\ \hline
|
| 89 |
|
|
\hline
|
| 90 |
|
|
\end{tabular}
|
| 91 |
|
|
\label{tab:arg_reg}
|
| 92 |
|
|
\end{table}
|
| 93 |
|
|
|
| 94 |
|
|
\subsubsection{Command register}
|
| 95 |
|
|
\label{sec:cmd_reg}
|
| 96 |
|
|
|
| 97 |
|
|
This register configures all aspects of command to be sent.
|
| 98 |
|
|
|
| 99 |
|
|
\begin{table}[H]
|
| 100 |
|
|
\caption{Command register}
|
| 101 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 102 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 103 |
|
|
\texttt{[31:14]} & & & reserved \\ \hline
|
| 104 |
|
|
\texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
|
| 105 |
|
|
\texttt{[7]} & & & reserved \\ \hline
|
| 106 |
|
|
\texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
|
| 107 |
|
|
0x2 - triggers write data transaction after command transaction\\ \hline
|
| 108 |
|
|
\texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
|
| 109 |
|
|
\texttt{[3]} & \texttt{0x0} & RW & check response crc \\ \hline
|
| 110 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,
|
| 111 |
|
|
core will wait for as long as busy signal remains) \\ \hline
|
| 112 |
|
|
\texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
|
| 113 |
|
|
0x2 - wait for long response (136-bits) \\ \hline
|
| 114 |
|
|
\hline
|
| 115 |
|
|
\end{tabular}
|
| 116 |
|
|
\label{tab:cmd_reg}
|
| 117 |
|
|
\end{table}
|
| 118 |
|
|
|
| 119 |
|
|
\subsubsection{Response register 0-3}
|
| 120 |
|
|
\label{sec:resp_reg}
|
| 121 |
|
|
|
| 122 |
|
|
Response registers 0-3 contains response data bits after end of succesful command transaction (if bits 1-0 of command register were configured to wait for response).
|
| 123 |
|
|
|
| 124 |
|
|
\begin{table}[H]
|
| 125 |
|
|
\caption{Response register 0-3}
|
| 126 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 127 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 128 |
|
|
\texttt{[31:0]} & \texttt{0x00000000} & R & response data bits \\ \hline
|
| 129 |
|
|
\hline
|
| 130 |
|
|
\end{tabular}
|
| 131 |
|
|
\label{tab:resp_reg}
|
| 132 |
|
|
\end{table}
|
| 133 |
|
|
|
| 134 |
|
|
|
| 135 |
|
|
\subsubsection{Control register}
|
| 136 |
|
|
\label{sec:control_reg}
|
| 137 |
|
|
|
| 138 |
|
|
\begin{table}[H]
|
| 139 |
|
|
\caption{Control register}
|
| 140 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 141 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 142 |
|
|
\texttt{[31:1]} & & & reserved \\ \hline
|
| 143 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & MMC/SD bus width; 0x0 - 1-bit operation; 0x1 - 4-bit operation \\ \hline
|
| 144 |
|
|
\hline
|
| 145 |
|
|
\end{tabular}
|
| 146 |
|
|
\label{tab:control_reg}
|
| 147 |
|
|
\end{table}
|
| 148 |
|
|
|
| 149 |
|
|
\subsubsection{Timeout register}
|
| 150 |
|
|
\label{sec:timeout_reg}
|
| 151 |
|
|
|
| 152 |
|
|
Timeout register configures transaction watchdog counter. If any transaction will last longer than configured timeout, interrupt will be generated.
|
| 153 |
|
|
Value in timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cyckles. Register value is calculated by following formula:
|
| 154 |
|
|
\begin{equation}
|
| 155 |
|
|
REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_devider} + 1))}
|
| 156 |
|
|
\end{equation}
|
| 157 |
|
|
|
| 158 |
|
|
\begin{table}[H]
|
| 159 |
|
|
\caption{Timeout register}
|
| 160 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 161 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 162 |
|
|
\texttt{[31:16]} & & & reserved \\ \hline
|
| 163 |
|
|
\texttt{[15:0]} & \texttt{0x0} & RW & timeout value \\ \hline
|
| 164 |
|
|
\hline
|
| 165 |
|
|
\end{tabular}
|
| 166 |
|
|
\label{tab:timeout_reg}
|
| 167 |
|
|
\end{table}
|
| 168 |
|
|
|
| 169 |
|
|
\subsubsection{Clock devider register}
|
| 170 |
|
|
\label{sec:div_reg}
|
| 171 |
|
|
|
| 172 |
|
|
Clock devider register control division of \texttt{sd\_clk\_i\_pad} signal frequency. Output of this devider is routed to MMC/SD interface clock domain.
|
| 173 |
|
|
Register value is calculated by following formula:
|
| 174 |
|
|
\begin{equation}
|
| 175 |
|
|
REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
|
| 176 |
|
|
\end{equation}
|
| 177 |
|
|
|
| 178 |
|
|
\begin{table}[H]
|
| 179 |
|
|
\caption{Clock devider register}
|
| 180 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 181 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 182 |
|
|
\texttt{[31:8]} & & & reserved \\ \hline
|
| 183 |
|
|
\texttt{[7:0]} & \texttt{0x0} & RW & devider ratio \\ \hline
|
| 184 |
|
|
\hline
|
| 185 |
|
|
\end{tabular}
|
| 186 |
|
|
\label{tab:div_reg}
|
| 187 |
|
|
\end{table}
|
| 188 |
|
|
|
| 189 |
|
|
\subsubsection{Software reset register}
|
| 190 |
|
|
\label{sec:reset_reg}
|
| 191 |
|
|
|
| 192 |
|
|
\begin{table}[H]
|
| 193 |
|
|
\caption{Software reset register}
|
| 194 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 195 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 196 |
|
|
\texttt{[31:1]} & & & reserved \\ \hline
|
| 197 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & reset; 0x0 - no reset; 0x1 - reset applied \\ \hline
|
| 198 |
|
|
\hline
|
| 199 |
|
|
\end{tabular}
|
| 200 |
|
|
\label{tab:reset_reg}
|
| 201 |
|
|
\end{table}
|
| 202 |
|
|
|
| 203 |
|
|
\subsubsection{Voltage information register}
|
| 204 |
|
|
\label{sec:voltage_reg}
|
| 205 |
|
|
|
| 206 |
6 |
rozpruwacz |
This register contains the value of power supply voltage expressed in mV. It is read-only register and its
|
| 207 |
|
|
value is configured in HDL.
|
| 208 |
|
|
|
| 209 |
3 |
rozpruwacz |
\begin{table}[H]
|
| 210 |
|
|
\caption{Software reset register}
|
| 211 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 212 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 213 |
6 |
rozpruwacz |
\texttt{[31:0]} & & R & power supply voltage [mV] \\ \hline
|
| 214 |
3 |
rozpruwacz |
\hline
|
| 215 |
|
|
\end{tabular}
|
| 216 |
|
|
\label{tab:voltage_reg}
|
| 217 |
|
|
\end{table}
|
| 218 |
|
|
|
| 219 |
|
|
\subsubsection{Capabilities information register}
|
| 220 |
|
|
\label{sec:capa_reg}
|
| 221 |
|
|
|
| 222 |
|
|
\begin{table}[H]
|
| 223 |
|
|
\caption{Capabilities information register}
|
| 224 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 225 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 226 |
|
|
\texttt{[31:0]} & & & reserved \\ \hline
|
| 227 |
|
|
\hline
|
| 228 |
|
|
\end{tabular}
|
| 229 |
|
|
\label{tab:capa_reg}
|
| 230 |
|
|
\end{table}
|
| 231 |
|
|
|
| 232 |
|
|
\subsubsection{Command events status register}
|
| 233 |
|
|
\label{sec:cmd_evt_reg}
|
| 234 |
|
|
|
| 235 |
|
|
This register holds all pending event flags related to command transactions. Write operation to this register
|
| 236 |
|
|
clears all flags.
|
| 237 |
|
|
|
| 238 |
|
|
\begin{table}[H]
|
| 239 |
|
|
\caption{Command events status register}
|
| 240 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 241 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 242 |
|
|
\texttt{[31:5]} & & & reserved \\ \hline
|
| 243 |
|
|
\texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
|
| 244 |
|
|
\texttt{[3]} & \texttt{0x0} & RW & crc error event \\ \hline
|
| 245 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
|
| 246 |
|
|
\texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
|
| 247 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
|
| 248 |
|
|
\hline
|
| 249 |
|
|
\end{tabular}
|
| 250 |
|
|
\label{tab:cmd_evt_reg}
|
| 251 |
|
|
\end{table}
|
| 252 |
|
|
|
| 253 |
|
|
\subsubsection{Command transaction events enable register}
|
| 254 |
|
|
\label{sec:cmd_ena_reg}
|
| 255 |
|
|
|
| 256 |
|
|
This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
|
| 257 |
|
|
|
| 258 |
|
|
\begin{table}[H]
|
| 259 |
|
|
\caption{Command transaction events enable register}
|
| 260 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 261 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 262 |
|
|
\texttt{[31:5]} & & & reserved \\ \hline
|
| 263 |
|
|
\texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
|
| 264 |
|
|
\texttt{[3]} & \texttt{0x0} & RW & enable crc error event \\ \hline
|
| 265 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
|
| 266 |
|
|
\texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
|
| 267 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & enable command transaction succesful completion event \\ \hline
|
| 268 |
|
|
\hline
|
| 269 |
|
|
\end{tabular}
|
| 270 |
|
|
\label{tab:cmd_ena_reg}
|
| 271 |
|
|
\end{table}
|
| 272 |
|
|
|
| 273 |
|
|
\subsubsection{Data transaction events status register}
|
| 274 |
|
|
\label{sec:data_evt_reg}
|
| 275 |
|
|
|
| 276 |
|
|
This register holds all pending event flags related to data transactions. Write operation to this register
|
| 277 |
|
|
clears all flags.
|
| 278 |
|
|
|
| 279 |
|
|
\begin{table}[H]
|
| 280 |
|
|
\caption{Data transaction events status register}
|
| 281 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 282 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 283 |
|
|
\texttt{[31:3]} & & & reserved \\ \hline
|
| 284 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
|
| 285 |
|
|
\texttt{[1]} & \texttt{0x0} & RW & crc error event \\ \hline
|
| 286 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & data transaction succesful completion event \\ \hline
|
| 287 |
|
|
\hline
|
| 288 |
|
|
\end{tabular}
|
| 289 |
|
|
\label{tab:data_evt_reg}
|
| 290 |
|
|
\end{table}
|
| 291 |
|
|
|
| 292 |
|
|
\subsubsection{Data transaction events enable register}
|
| 293 |
|
|
\label{sec:data_ena_reg}
|
| 294 |
|
|
|
| 295 |
|
|
This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
|
| 296 |
|
|
|
| 297 |
|
|
\begin{table}[H]
|
| 298 |
|
|
\caption{Data transaction events enable register}
|
| 299 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 300 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 301 |
|
|
\texttt{[31:3]} & & & reserved \\ \hline
|
| 302 |
|
|
\texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
|
| 303 |
|
|
\texttt{[1]} & \texttt{0x0} & RW & enable crc error event \\ \hline
|
| 304 |
|
|
\texttt{[0]} & \texttt{0x0} & RW & enable data transaction succesful completion event \\ \hline
|
| 305 |
|
|
\hline
|
| 306 |
|
|
\end{tabular}
|
| 307 |
|
|
\label{tab:data_ena_reg}
|
| 308 |
|
|
\end{table}
|
| 309 |
|
|
|
| 310 |
|
|
\subsubsection{Block size register}
|
| 311 |
|
|
\label{sec:blocksize_reg}
|
| 312 |
|
|
|
| 313 |
|
|
This register controls the number of bytes to write/read in a single block. Data transaction will transmit number of bytes equal to value of this register times value
|
| 314 |
|
|
of \texttt{blkock\_count} register.
|
| 315 |
|
|
|
| 316 |
|
|
\begin{table}[H]
|
| 317 |
|
|
\caption{Block size register}
|
| 318 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 319 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 320 |
|
|
\texttt{[31:12]} & & & reserved \\ \hline
|
| 321 |
|
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of byes in a single block \\ \hline
|
| 322 |
|
|
\hline
|
| 323 |
|
|
\end{tabular}
|
| 324 |
|
|
\label{tab:blocksize_reg}
|
| 325 |
|
|
\end{table}
|
| 326 |
|
|
|
| 327 |
|
|
\subsubsection{Block count register}
|
| 328 |
|
|
\label{sec:blockcnt_reg}
|
| 329 |
|
|
|
| 330 |
|
|
This register controls the number of blocks to write/read in data transaction. Data transaction will transmit number of bytes equal to value of this register times value
|
| 331 |
|
|
of \texttt{blkock\_size} register.
|
| 332 |
|
|
|
| 333 |
|
|
\begin{table}[H]
|
| 334 |
|
|
\caption{Block count register}
|
| 335 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 336 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 337 |
|
|
\texttt{[31:12]} & & & reserved \\ \hline
|
| 338 |
|
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of blocks in data transaction \\ \hline
|
| 339 |
|
|
\hline
|
| 340 |
|
|
\end{tabular}
|
| 341 |
|
|
\label{tab:blockcnt_reg}
|
| 342 |
|
|
\end{table}
|
| 343 |
|
|
|
| 344 |
|
|
\subsubsection{DMA destination / source register}
|
| 345 |
|
|
\label{sec:dst_src_reg}
|
| 346 |
|
|
|
| 347 |
|
|
This registers configures the DMA source / destination address. For write transactions, this address points to the begining of data block to be sent.
|
| 348 |
|
|
For read transactions, this address points to the begining of data block to be written.
|
| 349 |
|
|
|
| 350 |
|
|
\begin{table}[H]
|
| 351 |
|
|
\caption{DMA destination / source register}
|
| 352 |
|
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| 353 |
|
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| 354 |
|
|
\texttt{[31:o]} & 0x00000000 & RW & address \\ \hline
|
| 355 |
|
|
\hline
|
| 356 |
|
|
\end{tabular}
|
| 357 |
|
|
\label{tab:dst_src_reg}
|
| 358 |
|
|
\end{table}
|
| 359 |
|
|
|
