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[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_crc_16.v] - Blame information for rev 3

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// ==========================================================================
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// CRC Generation Unit - Linear Feedback Shift Register implementation
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// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
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// ==========================================================================
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module sd_crc_16(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
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   input        BITVAL;                            // Next input bit
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   input        ENABLE;                            // Enable calculation
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   input        BITSTRB;                           // Current bit valid (Clock)
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   input        CLEAR;                             // Init CRC value
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   output [15:0] CRC;                               // Current output CRC value
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   reg    [15:0] CRC;                               // We need output registers
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   wire         inv;
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   assign inv = BITVAL ^ CRC[15];                   // XOR required?
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   always @(posedge BITSTRB or posedge CLEAR) begin
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      if (CLEAR) begin
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         CRC <= 0;                                  // Init before calculation
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         end
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      else begin
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         if (ENABLE == 1) begin
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             CRC[15] <= CRC[14];
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             CRC[14] <= CRC[13];
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             CRC[13] <= CRC[12];
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             CRC[12] <= CRC[11] ^ inv;
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             CRC[11] <= CRC[10];
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             CRC[10] <= CRC[9];
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             CRC[9] <= CRC[8];
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             CRC[8] <= CRC[7];
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             CRC[7] <= CRC[6];
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             CRC[6] <= CRC[5];
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             CRC[5] <= CRC[4] ^ inv;
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             CRC[4] <= CRC[3];
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             CRC[3] <= CRC[2];
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             CRC[2] <= CRC[1];
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             CRC[1] <= CRC[0];
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             CRC[0] <= inv;
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             end
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         end
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      end
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endmodule

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