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[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_data_master.v] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// WISHBONE SD Card Controller IP Core                          ////
////                                                              ////
//// sd_data_master.v                                             ////
////                                                              ////
//// This file is part of the WISHBONE SD Card                    ////
//// Controller IP Core project                                   ////
//// http://opencores.org/project,sd_card_controller              ////
////                                                              ////
//// Description                                                  ////
//// State machine resposible for controlling data transfers      ////
//// on 4-bit sd card data interface                              ////
////                                                              ////
//// Author(s):                                                   ////
////     - Marek Czerski, ma.czerski@gmail.com                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// Based on original work by                                    ////
////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
////                                                              ////
////     Copyright (C) 2009 Authors                               ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
 
module sd_data_master (
           input sd_clk,
           input rst,
           input start_tx_i,
           input start_rx_i,
           //Output to SD-Host Reg
           output reg d_write_o,
           output reg d_read_o,
           //To fifo filler
           output reg start_tx_fifo_o,
           output reg start_rx_fifo_o,
           input tx_fifo_empty_i,
           input tx_fifo_full_i,
           input rx_fifo_full_i,
           //SD-DATA_Host
           input xfr_complete_i,
           input crc_ok_i,
           //status output
           output reg [`INT_DATA_SIZE-1:0] int_status_o,
           input int_status_rst_i
       );
 
reg tx_cycle;
parameter SIZE = 3;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE          = 3'b000;
parameter START_TX_FIFO = 3'b001;
parameter START_RX_FIFO = 3'b010;
parameter DATA_TRANSFER = 3'b100;
 
reg trans_done;
 
always @(state or start_tx_i or start_rx_i or tx_fifo_full_i or xfr_complete_i or trans_done)
begin: FSM_COMBO
    case(state)
        IDLE: begin
            if (start_tx_i == 1) begin
                next_state <= START_TX_FIFO;
            end
            else if (start_rx_i == 1) begin
                next_state <= START_RX_FIFO;
            end
            else begin
                next_state <= IDLE;
            end
        end
        START_TX_FIFO: begin
            if (tx_fifo_full_i == 1 && xfr_complete_i == 0)
                next_state <= DATA_TRANSFER;
            else
                next_state <= START_TX_FIFO;
        end
        START_RX_FIFO: begin
            if (xfr_complete_i == 0)
                next_state <= DATA_TRANSFER;
            else
                next_state <= START_RX_FIFO;
        end
        DATA_TRANSFER: begin
            if (trans_done)
                next_state <= IDLE;
            else
                next_state <= DATA_TRANSFER;
        end
        default: next_state <= IDLE;
    endcase
end
 
//----------------Seq logic------------
always @(posedge sd_clk or posedge rst)
begin: FSM_SEQ
    if (rst) begin
        state <= IDLE;
    end
    else begin
        state <= next_state;
    end
end
 
//Output logic-----------------
always @(posedge sd_clk or posedge rst)
begin
    if (rst) begin
        start_tx_fifo_o <= 0;
        start_rx_fifo_o <= 0;
        d_write_o <= 0;
        d_read_o <= 0;
        trans_done <= 0;
        tx_cycle <= 0;
        int_status_o <= 0;
    end
    else begin
        case(state)
            IDLE: begin
                start_tx_fifo_o <= 0;
                start_rx_fifo_o <= 0;
                d_write_o <= 0;
                d_read_o <= 0;
                trans_done <= 0;
                tx_cycle <= 0;
            end
            START_RX_FIFO: begin
                start_rx_fifo_o <= 1;
                start_tx_fifo_o <= 0;
                tx_cycle <= 0;
                d_read_o <= 1;
            end
            START_TX_FIFO:  begin
                start_rx_fifo_o <= 0;
                start_tx_fifo_o <= 1;
                tx_cycle <= 1;
                if (tx_fifo_full_i == 1)
                    d_write_o <= 1;
            end
            DATA_TRANSFER: begin
                d_read_o <= 0;
                d_write_o <= 0;
                if (tx_cycle) begin
                    if (tx_fifo_empty_i) begin
                        if (!trans_done)
                            int_status_o[`INT_DATA_CFE] <= 1;
                        trans_done <= 1;
                        //stop sd_data_serial_host
                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end
                else begin
                    if (rx_fifo_full_i) begin
                        if (!trans_done)
                            int_status_o[`INT_DATA_CFE] <= 1;
                        trans_done <= 1;
                        //stop sd_data_serial_host
                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end
                if (xfr_complete_i) begin //Transfer complete
                    d_write_o <= 0;
                    d_read_o <= 0;
                    trans_done <= 1;
                    if (!crc_ok_i)  begin //Wrong CRC and Data line free.
                        if (!trans_done)
                            int_status_o[`INT_DATA_CCRCE] <= 1;
                    end
                    else if (crc_ok_i) begin //Data Line free
                        if (!trans_done)
                            int_status_o[`INT_DATA_CC] <= 1;
                    end
                end
            end
        endcase
        if (int_status_rst_i)
            int_status_o<=0;
    end
end
 
endmodule

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Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_data_master.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE SD Card Controller IP Core ////`
4			`//// ////`
5			`//// sd_data_master.v ////`
6			`//// ////`
7			`//// This file is part of the WISHBONE SD Card ////`
8			`//// Controller IP Core project ////`
9	8	rozpruwacz	`//// http://opencores.org/project,sd_card_controller ////`
10	3	rozpruwacz	`//// ////`
11			`//// Description ////`
12			`//// State machine resposible for controlling data transfers ////`
13			`//// on 4-bit sd card data interface ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Marek Czerski, ma.czerski@gmail.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// Based on original work by ////`
23			`//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////`
24			`//// ////`
25			`//// Copyright (C) 2009 Authors ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`include "sd_defines.h"
50
51			`module sd_data_master (`
52			`input sd_clk,`
53			`input rst,`
54			`input start_tx_i,`
55			`input start_rx_i,`
56			`//Output to SD-Host Reg`
57			`output reg d_write_o,`
58			`output reg d_read_o,`
59			`//To fifo filler`
60			`output reg start_tx_fifo_o,`
61			`output reg start_rx_fifo_o,`
62			`input tx_fifo_empty_i,`
63			`input tx_fifo_full_i,`
64			`input rx_fifo_full_i,`
65			`//SD-DATA_Host`
66			`input xfr_complete_i,`
67			`input crc_ok_i,`
68			`//status output`
69			output reg [`INT_DATA_SIZE-1:0] int_status_o,
70			`input int_status_rst_i`
71			`);`
72
73			`reg tx_cycle;`
74			`parameter SIZE = 3;`
75			`reg [SIZE-1:0] state;`
76			`reg [SIZE-1:0] next_state;`
77			`parameter IDLE = 3'b000;`
78			`parameter START_TX_FIFO = 3'b001;`
79			`parameter START_RX_FIFO = 3'b010;`
80			`parameter DATA_TRANSFER = 3'b100;`
81
82			`reg trans_done;`
83
84			`always @(state or start_tx_i or start_rx_i or tx_fifo_full_i or xfr_complete_i or trans_done)`
85			`begin: FSM_COMBO`
86			`case(state)`
87			`IDLE: begin`
88			`if (start_tx_i == 1) begin`
89			`next_state <= START_TX_FIFO;`
90			`end`
91			`else if (start_rx_i == 1) begin`
92			`next_state <= START_RX_FIFO;`
93			`end`
94			`else begin`
95			`next_state <= IDLE;`
96			`end`
97			`end`
98			`START_TX_FIFO: begin`
99			`if (tx_fifo_full_i == 1 && xfr_complete_i == 0)`
100			`next_state <= DATA_TRANSFER;`
101			`else`
102			`next_state <= START_TX_FIFO;`
103			`end`
104			`START_RX_FIFO: begin`
105			`if (xfr_complete_i == 0)`
106			`next_state <= DATA_TRANSFER;`
107			`else`
108			`next_state <= START_RX_FIFO;`
109			`end`
110			`DATA_TRANSFER: begin`
111			`if (trans_done)`
112			`next_state <= IDLE;`
113			`else`
114			`next_state <= DATA_TRANSFER;`
115			`end`
116			`default: next_state <= IDLE;`
117			`endcase`
118			`end`
119
120			`//----------------Seq logic------------`
121			`always @(posedge sd_clk or posedge rst)`
122			`begin: FSM_SEQ`
123			`if (rst) begin`
124			`state <= IDLE;`
125			`end`
126			`else begin`
127			`state <= next_state;`
128			`end`
129			`end`
130
131			`//Output logic-----------------`
132			`always @(posedge sd_clk or posedge rst)`
133			`begin`
134			`if (rst) begin`
135			`start_tx_fifo_o <= 0;`
136			`start_rx_fifo_o <= 0;`
137			`d_write_o <= 0;`
138			`d_read_o <= 0;`
139			`trans_done <= 0;`
140			`tx_cycle <= 0;`
141			`int_status_o <= 0;`
142			`end`
143			`else begin`
144			`case(state)`
145			`IDLE: begin`
146			`start_tx_fifo_o <= 0;`
147			`start_rx_fifo_o <= 0;`
148			`d_write_o <= 0;`
149			`d_read_o <= 0;`
150			`trans_done <= 0;`
151			`tx_cycle <= 0;`
152			`end`
153			`START_RX_FIFO: begin`
154			`start_rx_fifo_o <= 1;`
155			`start_tx_fifo_o <= 0;`
156			`tx_cycle <= 0;`
157			`d_read_o <= 1;`
158			`end`
159			`START_TX_FIFO: begin`
160			`start_rx_fifo_o <= 0;`
161			`start_tx_fifo_o <= 1;`
162			`tx_cycle <= 1;`
163			`if (tx_fifo_full_i == 1)`
164			`d_write_o <= 1;`
165			`end`
166			`DATA_TRANSFER: begin`
167			`d_read_o <= 0;`
168			`d_write_o <= 0;`
169			`if (tx_cycle) begin`
170			`if (tx_fifo_empty_i) begin`
171			`if (!trans_done)`
172			int_status_o[`INT_DATA_CFE] <= 1;
173			`trans_done <= 1;`
174			`//stop sd_data_serial_host`
175			`d_write_o <= 1;`
176			`d_read_o <= 1;`
177			`end`
178			`end`
179			`else begin`
180			`if (rx_fifo_full_i) begin`
181			`if (!trans_done)`
182			int_status_o[`INT_DATA_CFE] <= 1;
183			`trans_done <= 1;`
184			`//stop sd_data_serial_host`
185			`d_write_o <= 1;`
186			`d_read_o <= 1;`
187			`end`
188			`end`
189			`if (xfr_complete_i) begin //Transfer complete`
190			`d_write_o <= 0;`
191			`d_read_o <= 0;`
192			`trans_done <= 1;`
193			`if (!crc_ok_i) begin //Wrong CRC and Data line free.`
194			`if (!trans_done)`
195			int_status_o[`INT_DATA_CCRCE] <= 1;
196			`end`
197			`else if (crc_ok_i) begin //Data Line free`
198			`if (!trans_done)`
199			int_status_o[`INT_DATA_CC] <= 1;
200			`end`
201			`end`
202			`end`
203			`endcase`
204			`if (int_status_rst_i)`
205			`int_status_o<=0;`
206			`end`
207			`end`
208
209			`endmodule`