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[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_data_xfer_trig.v] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// WISHBONE SD Card Controller IP Core                          ////
////                                                              ////
//// sd_data_xfer_trig.v                                          ////
////                                                              ////
//// This file is part of the WISHBONE SD Card                    ////
//// Controller IP Core project                                   ////
//// http://opencores.org/project,sd_card_controller              ////
////                                                              ////
//// Description                                                  ////
//// Module resposible for triggering data transfer based on      ////
//// command transfer completition code                           ////
////                                                              ////
//// Author(s):                                                   ////
////     - Marek Czerski, ma.czerski@gmail.com                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
 
module sd_data_xfer_trig (
           input sd_clk,
           input rst,
           input cmd_with_data_start_i,
           input r_w_i,
           input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
           output reg start_tx_o,
           output reg start_rx_o
       );
 
reg r_w_reg;
parameter SIZE = 2;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE             = 2'b00;
parameter WAIT_FOR_CMD_INT = 2'b01;
parameter TRIGGER_XFER     = 2'b10;
 
always @(state or cmd_with_data_start_i or r_w_i or cmd_int_status_i)
begin: FSM_COMBO
    case(state)
        IDLE: begin
            if (cmd_with_data_start_i & r_w_i)
                next_state <= TRIGGER_XFER;
            else if (cmd_with_data_start_i)
                next_state <= WAIT_FOR_CMD_INT;
            else
                next_state <= IDLE;
        end
        WAIT_FOR_CMD_INT: begin
            if (cmd_int_status_i[`INT_CMD_CC])
                next_state <= TRIGGER_XFER;
            else if (cmd_int_status_i[`INT_CMD_EI])
                next_state <= IDLE;
            else
                next_state <= WAIT_FOR_CMD_INT;
        end
        TRIGGER_XFER: begin
            next_state <= IDLE;
        end
        default: next_state <= IDLE;
    endcase
end
 
always @(posedge sd_clk or posedge rst)
begin: FSM_SEQ
    if (rst) begin
        state <= IDLE;
    end
    else begin
        state <= next_state;
    end
end
 
always @(posedge sd_clk or posedge rst)
begin
    if (rst) begin
        start_tx_o <= 0;
        start_rx_o <= 0;
        r_w_reg <= 0;
    end
    else begin
        case(state)
            IDLE: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
                r_w_reg <= r_w_i;
            end
            WAIT_FOR_CMD_INT: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
            end
            TRIGGER_XFER: begin
                start_tx_o <= ~r_w_reg;
                start_rx_o <= r_w_reg;
            end
        endcase
    end
end
 
endmodule

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE SD Card Controller IP Core ////`
4			`//// ////`
5			`//// sd_data_xfer_trig.v ////`
6			`//// ////`
7			`//// This file is part of the WISHBONE SD Card ////`
8			`//// Controller IP Core project ////`
9	8	rozpruwacz	`//// http://opencores.org/project,sd_card_controller ////`
10	3	rozpruwacz	`//// ////`
11			`//// Description ////`
12			`//// Module resposible for triggering data transfer based on ////`
13			`//// command transfer completition code ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Marek Czerski, ma.czerski@gmail.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`include "sd_defines.h"
45
46			`module sd_data_xfer_trig (`
47			`input sd_clk,`
48			`input rst,`
49			`input cmd_with_data_start_i,`
50			`input r_w_i,`
51			input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
52			`output reg start_tx_o,`
53			`output reg start_rx_o`
54			`);`
55
56			`reg r_w_reg;`
57			`parameter SIZE = 2;`
58			`reg [SIZE-1:0] state;`
59			`reg [SIZE-1:0] next_state;`
60			`parameter IDLE = 2'b00;`
61			`parameter WAIT_FOR_CMD_INT = 2'b01;`
62			`parameter TRIGGER_XFER = 2'b10;`
63
64			`always @(state or cmd_with_data_start_i or r_w_i or cmd_int_status_i)`
65			`begin: FSM_COMBO`
66			`case(state)`
67			`IDLE: begin`
68			`if (cmd_with_data_start_i & r_w_i)`
69			`next_state <= TRIGGER_XFER;`
70			`else if (cmd_with_data_start_i)`
71			`next_state <= WAIT_FOR_CMD_INT;`
72			`else`
73			`next_state <= IDLE;`
74			`end`
75			`WAIT_FOR_CMD_INT: begin`
76			if (cmd_int_status_i[`INT_CMD_CC])
77			`next_state <= TRIGGER_XFER;`
78			else if (cmd_int_status_i[`INT_CMD_EI])
79			`next_state <= IDLE;`
80			`else`
81			`next_state <= WAIT_FOR_CMD_INT;`
82			`end`
83			`TRIGGER_XFER: begin`
84			`next_state <= IDLE;`
85			`end`
86			`default: next_state <= IDLE;`
87			`endcase`
88			`end`
89
90			`always @(posedge sd_clk or posedge rst)`
91			`begin: FSM_SEQ`
92			`if (rst) begin`
93			`state <= IDLE;`
94			`end`
95			`else begin`
96			`state <= next_state;`
97			`end`
98			`end`
99
100			`always @(posedge sd_clk or posedge rst)`
101			`begin`
102			`if (rst) begin`
103			`start_tx_o <= 0;`
104			`start_rx_o <= 0;`
105			`r_w_reg <= 0;`
106			`end`
107			`else begin`
108			`case(state)`
109			`IDLE: begin`
110			`start_tx_o <= 0;`
111			`start_rx_o <= 0;`
112			`r_w_reg <= r_w_i;`
113			`end`
114			`WAIT_FOR_CMD_INT: begin`
115			`start_tx_o <= 0;`
116			`start_rx_o <= 0;`
117			`end`
118			`TRIGGER_XFER: begin`
119			`start_tx_o <= ~r_w_reg;`
120			`start_rx_o <= r_w_reg;`
121			`end`
122			`endcase`
123			`end`
124			`end`
125
126			`endmodule`

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[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_data_xfer_trig.v] - Blame information for rev 8