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Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_defines.h] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// WISHBONE SD Card Controller IP Core                          ////
////                                                              ////
//// sd_defines.v                                                 ////
////                                                              ////
//// This file is part of the WISHBONE SD Card                    ////
//// Controller IP Core project                                   ////
//// http://opencores.org/project,sd_card_controller              ////
////                                                              ////
//// Description                                                  ////
//// Header file with common definitions                          ////
////                                                              ////
//// Author(s):                                                   ////
////     - Marek Czerski, ma.czerski@gmail.com                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// Based on original work by                                    ////
////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
////                                                              ////
////     Copyright (C) 2009 Authors                               ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//global defines
`define BLKSIZE_W 12
`define BLKCNT_W 16
 
//cmd module interrupts
`define INT_CMD_SIZE 5
`define INT_CMD_CC 0
`define INT_CMD_EI 1
`define INT_CMD_CTE 2
`define INT_CMD_CCRCE 3
`define INT_CMD_CIE  4
 
//data module interrupts
`define INT_DATA_SIZE 3
`define INT_DATA_CC 0
`define INT_DATA_CCRCE 1
`define INT_DATA_CFE 2
 
//command register defines
`define CMD_REG_SIZE 14
`define CMD_RESPONSE_CHECK 1:0
`define CMD_BUSY_CHECK 2
`define CMD_CRC_CHECK 3
`define CMD_IDX_CHECK 4
`define CMD_WITH_DATA 6:5
`define CMD_INDEX 13:8
 
//register addreses
`define argument 8'h00
`define command 8'h04
`define resp0 8'h08
`define resp1 8'h0c
`define resp2 8'h10
`define resp3 8'h14
`define controller 8'h1c
`define timeout 8'h20
`define clock_d 8'h24
`define reset 8'h28
`define voltage 8'h2c
`define capa 8'h30
`define cmd_isr 8'h34
`define cmd_iser 8'h38
`define data_isr 8'h3c
`define data_iser 8'h40
`define blksize 8'h44
`define blkcnt 8'h48
`define dst_src_addr 8'h60
 
//wb module defines
`define RESET_BLOCK_SIZE 512
`define RESET_CLK_DIV 0
`define SUPPLY_VOLTAGE_mV 3300

Line No.	Rev	Author	Line
1	3	rozpruwacz	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE SD Card Controller IP Core ////`
4			`//// ////`
5			`//// sd_defines.v ////`
6			`//// ////`
7			`//// This file is part of the WISHBONE SD Card ////`
8			`//// Controller IP Core project ////`
9	8	rozpruwacz	`//// http://opencores.org/project,sd_card_controller ////`
10	3	rozpruwacz	`//// ////`
11			`//// Description ////`
12			`//// Header file with common definitions ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Marek Czerski, ma.czerski@gmail.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2013 Authors ////`
20			`//// ////`
21			`//// Based on original work by ////`
22			`//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////`
23			`//// ////`
24			`//// Copyright (C) 2009 Authors ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48
49			`//global defines`
50			`define BLKSIZE_W 12
51			`define BLKCNT_W 16
52
53			`//cmd module interrupts`
54			`define INT_CMD_SIZE 5
55			`define INT_CMD_CC 0
56			`define INT_CMD_EI 1
57			`define INT_CMD_CTE 2
58			`define INT_CMD_CCRCE 3
59			`define INT_CMD_CIE 4
60
61			`//data module interrupts`
62			`define INT_DATA_SIZE 3
63			`define INT_DATA_CC 0
64			`define INT_DATA_CCRCE 1
65			`define INT_DATA_CFE 2
66
67			`//command register defines`
68			`define CMD_REG_SIZE 14
69			`define CMD_RESPONSE_CHECK 1:0
70			`define CMD_BUSY_CHECK 2
71			`define CMD_CRC_CHECK 3
72			`define CMD_IDX_CHECK 4
73			`define CMD_WITH_DATA 6:5
74			`define CMD_INDEX 13:8
75
76			`//register addreses`
77			`define argument 8'h00
78			`define command 8'h04
79			`define resp0 8'h08
80			`define resp1 8'h0c
81			`define resp2 8'h10
82			`define resp3 8'h14
83			`define controller 8'h1c
84			`define timeout 8'h20
85			`define clock_d 8'h24
86			`define reset 8'h28
87			`define voltage 8'h2c
88			`define capa 8'h30
89			`define cmd_isr 8'h34
90			`define cmd_iser 8'h38
91			`define data_isr 8'h3c
92			`define data_iser 8'h40
93			`define blksize 8'h44
94			`define blkcnt 8'h48
95			`define dst_src_addr 8'h60
96
97			`//wb module defines`
98			`define RESET_BLOCK_SIZE 512
99			`define RESET_CLK_DIV 0
100	6	rozpruwacz	`define SUPPLY_VOLTAGE_mV 3300

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[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_defines.h] - Blame information for rev 8