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######################################################################
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#### ####
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#### WISHBONE SD Card Controller IP Core ####
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#### ####
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#### Makefile ####
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#### ####
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#### This file is part of the WISHBONE SD Card ####
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#### Controller IP Core project ####
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rozpruwacz |
#### http://opencores.org/project,sd_card_controller ####
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rozpruwacz |
#### ####
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#### Description ####
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#### Altera synthesis makefile ####
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#### ####
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#### Author(s): ####
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#### - Marek Czerski, ma.czerski@gmail.com ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2013 Authors ####
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#### ####
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#### Based on original work by ####
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#### Stefan Kristiansson, stefan.kristiansson@saunalahti.fi ####
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#### ####
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#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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V ?= @
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QUARTUS_DIR ?= /opt/altera/11.0/quartus
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QUARTUS = $(QUARTUS_DIR)/bin/quartus
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SH = $(QUARTUS_DIR)/bin/quartus_sh
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PGM = $(QUARTUS_DIR)/bin/quartus_pgm
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STA = $(QUARTUS_DIR)/bin/quartus_sta
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ASM = $(QUARTUS_DIR)/bin/quartus_asm
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FIT = $(QUARTUS_DIR)/bin/quartus_fit
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MAP = $(QUARTUS_DIR)/bin/quartus_map
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RUN_DIR=$(shell pwd)
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BIN_DIR=$(RUN_DIR)/../bin
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RTL_TOP ?= sdc_controller_top
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DESIGN_NAME ?= sdc_controller
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FPGA_FAMILY ?= "Cyclone IV E"
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FPGA_PART ?= EP4CE40F29C8
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RTL_VERILOG_SRC = $(shell ls ../../../rtl/verilog/*.v ../src/*.v)
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RTL_VERILOG_INCLUDE_DIR = ../../../rtl/verilog
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TCL_FILE=$(DESIGN_NAME).tcl
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SDC_FILE=$(DESIGN_NAME).sdc
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QPF_FILE=$(DESIGN_NAME).qpf
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all: sta
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$(TCL_FILE): $(BIN_DIR)/pin_assignments.tcl $(RTL_VERILOG_SRC) $(BOARD_BACKEND_VERILOG_SRC) $(RTL_VHDL_SRC)
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$(V)echo; echo "#### Generating TCL file ####"; echo
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$(V)echo "# TCL Script for SD Controller Synthesis" > $@
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$(V)echo "# This file is autogenerated - any changes will be overwritten" >> $@
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$(V)echo "# See the Makefile in syn/quartus/bin to make changes" >> $@
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$(V)echo "project_new $(DESIGN_NAME) -overwrite" >> $@
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$(V)echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
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$(V)echo "set_global_assignment -name DEVICE $(FPGA_PART)" >> $@
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$(V)echo "set_global_assignment -name TOP_LEVEL_ENTITY $(RTL_TOP)" >> $@
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$(V)for file in $(RTL_VERILOG_SRC); do \
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echo "set_global_assignment -name VERILOG_FILE $$file" >> $@ ; \
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done
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$(V)for file in $(BOARD_BACKEND_VERILOG_SRC); do \
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echo "set_global_assignment -name VERILOG_FILE $$file" >> $@ ; \
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done
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$(V)for file in $(RTL_VHDL_SRC); do \
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echo "set_global_assignment -name VHDL_FILE $$file" >> $@ ; \
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done
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$(V)echo "set_global_assignment -name SEARCH_PATH $(RTL_VERILOG_INCLUDE_DIR)" >> $@
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$(V)echo "set_global_assignment -name SDC_FILE $(DESIGN_NAME).sdc" >> $@
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# Do pin assignments
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$(V)if [ -f $(BIN_DIR)/pin_assignments.tcl ]; then \
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cat $(BIN_DIR)/pin_assignments.tcl >> $@ ; \
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fi;
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$(V)echo "project_close" >> $@
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$(V)echo
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$(SDC_FILE): $(BIN_DIR)/constraints.sdc
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$(V)echo; echo "#### Generating SDC file ####"; echo
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$(V)echo "# SDC file for SD Controller" > $@
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$(V)echo "# This file is autogenerated - any changes will be overwritten" >> $@
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$(V)echo "# See the Makefile in syn/quartus/bin to make changes" >> $@
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$(V)if [ -f $(BIN_DIR)/constraints.sdc ]; then \
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cat $(BIN_DIR)/constraints.sdc >> $@ ; \
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fi;
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$(V)echo
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$(QPF_FILE): $(TCL_FILE) $(SDC_FILE)
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$(V) echo "#### Generating project files ####"
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$(V)$(SH) -t $(TCL_FILE)
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project: $(QPF_FILE)
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quartus: $(QPF_FILE)
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$(V)$(QUARTUS) $(QPF_FILE)
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pgm:
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$(V)$(PGM) --mode=jtag -o p\;$(DESIGN_NAME).sof
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sta: asm
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$(V)$(STA) $(DESIGN_NAME)
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asm: fit
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$(V)$(ASM) $(DESIGN_NAME)
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fit: map
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$(V)$(FIT) $(DESIGN_NAME)
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map: project
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$(V)$(MAP) $(DESIGN_NAME)
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print_config:
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$(V)echo; echo "### Synthesis make configuration ###"; echo
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$(V)echo "FPGA_FAMILY="$(FPGA_FAMILY)
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$(V)echo "FPGA_PART="$(FPGA_PART)
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$(V)echo
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print_rtl_sources:
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$(V)echo $(RTL_VERILOG_SRC)
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clean:
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rm -rf *.* db incremental_db
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