Subversion Repositories sdhc-sc-core

-- SDHC-SC-Core

-- Secure Digital High Capacity Self Configuring Core

-- 

-- (C) Copyright 2010, Rainer Kastl

-- All rights reserved.

-- 

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution.

--     * Neither the name of the <organization> nor the

--       names of its contributors may be used to endorse or promote products

--       derived from this software without specific prior written permission.

-- 

-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND

-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- 

-- File        : CycSimpleDualPortedRam-Syn-ea.vhdl

-- Owner       : Rainer Kastl

-- Description : 

-- Links       : 

-- 

-- megafunction wizard: %RAM: 2-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram 

-- ============================================================

-- File Name: CycSimpleDualPortedRam.vhd

-- Megafunction Name(s):

--                      altsyncram

--

-- Simulation Library Files(s):

--                      altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2010 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions 

--and other software and tools, and its AMPP partner logic 

--functions, and any output files from any of the foregoing 

--(including device programming or simulation files), and any 

--associated documentation or information are expressly subject 

--to the terms and conditions of the Altera Program License 

--Subscription Agreement, Altera MegaCore Function License 

--Agreement, or other applicable license agreement, including, 

--without limitation, that your use is for the sole purpose of 

--programming logic devices manufactured by Altera and sold by 

--Altera or its authorized distributors.  Please refer to the 

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY CycSimpleDualPortedRam IS

        PORT

        (

                clock           : IN STD_LOGIC  := '1';

                data            : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                rdaddress               : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

                wraddress               : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

                wren            : IN STD_LOGIC  := '0';

                q               : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

        );

END CycSimpleDualPortedRam;

ARCHITECTURE SYN OF cycsimpledualportedram IS

        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (31 DOWNTO 0);

        COMPONENT altsyncram

        GENERIC (

                address_reg_b           : STRING;

                clock_enable_input_a            : STRING;

                clock_enable_input_b            : STRING;

                clock_enable_output_a           : STRING;

                clock_enable_output_b           : STRING;

                intended_device_family          : STRING;

                lpm_type                : STRING;

                numwords_a              : NATURAL;

                numwords_b              : NATURAL;

                operation_mode          : STRING;

                outdata_aclr_b          : STRING;

                outdata_reg_b           : STRING;

                power_up_uninitialized          : STRING;

                read_during_write_mode_mixed_ports              : STRING;

                widthad_a               : NATURAL;

                widthad_b               : NATURAL;

                width_a         : NATURAL;

                width_b         : NATURAL;

                width_byteena_a         : NATURAL

        );

        PORT (

                        wren_a  : IN STD_LOGIC ;

                        clock0  : IN STD_LOGIC ;

                        address_a       : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

                        address_b       : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

                        q_b     : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

                        data_a  : IN STD_LOGIC_VECTOR (31 DOWNTO 0)

        );

        END COMPONENT;

BEGIN

        q    <= sub_wire0(31 DOWNTO 0);

        altsyncram_component : altsyncram

        GENERIC MAP (

                address_reg_b => "CLOCK0",

                clock_enable_input_a => "BYPASS",

                clock_enable_input_b => "BYPASS",

                clock_enable_output_a => "BYPASS",

                clock_enable_output_b => "BYPASS",

                intended_device_family => "Cyclone II",

                lpm_type => "altsyncram",

                numwords_a => 128,

                numwords_b => 128,

                operation_mode => "DUAL_PORT",

                outdata_aclr_b => "NONE",

                outdata_reg_b => "CLOCK0",

                power_up_uninitialized => "FALSE",

                read_during_write_mode_mixed_ports => "OLD_DATA",

                widthad_a => 7,

                widthad_b => 7,

                width_a => 32,

                width_b => 32,

                width_byteena_a => 1

        )

        PORT MAP (

                wren_a => wren,

                clock0 => clock,

                address_a => wraddress,

                address_b => rdaddress,

                data_a => data,

                q_b => sub_wire0

        );

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"

-- Retrieval info: PRIVATE: CLRq NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"

-- Retrieval info: PRIVATE: Clock NUMERIC "0"

-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"

-- Retrieval info: PRIVATE: ECC NUMERIC "0"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"

-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"

-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"

-- Retrieval info: PRIVATE: MIFfilename STRING ""

-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"

-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"

-- Retrieval info: PRIVATE: REGdata NUMERIC "1"

-- Retrieval info: PRIVATE: REGq NUMERIC "0"

-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGrren NUMERIC "1"

-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGwren NUMERIC "1"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"

-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"

-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"

-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"

-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"

-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"

-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"

-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: enable NUMERIC "0"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"

-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"

-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"

-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"

-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"

-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"

-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"

-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock

-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]

-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]

-- Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL rdaddress[6..0]

-- Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL wraddress[6..0]

-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren

-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0

-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0

-- Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0

-- Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.cmp FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_inst.vhd FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_waveforms.html TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_wave*.jpg FALSE

-- Retrieval info: LIB_FILE: altera_mf