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rkastl |
-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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rkastl |
-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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rkastl |
--
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rkastl |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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164 |
rkastl |
--
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-- File : Sd-p.vhdl
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-- Owner : Rainer Kastl
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-- Description : Definitions for SD cards and controllers (Spec 2.0)
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-- Links :
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--
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rkastl |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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rkastl |
use work.Global.all;
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rkastl |
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package Sd is
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rkastl |
-- CMD transfer: constants
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rkastl |
constant cSdStartBit : std_ulogic := '0';
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constant cSdEndBit : std_ulogic := '1';
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constant cSdTransBitHost : std_ulogic := '1';
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rkastl |
constant cSdTransBitSlave : std_ulogic := '0';
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rkastl |
-- CMD transfer: types
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rkastl |
constant cSdCmdIdHigh : natural := 6;
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subtype aSdCmdId is std_ulogic_vector(cSdCmdIdHigh-1 downto 0);
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rkastl |
subtype aSdCmdArg is std_ulogic_vector(31 downto 0);
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rkastl |
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rkastl |
type aSdCmdContent is record
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rkastl |
id : aSdCmdId;
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rkastl |
arg : aSdCmdArg;
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end record aSdCmdContent;
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rkastl |
constant cDefaultSdCmdContent : aSdCmdContent := (
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rkastl |
id => (others => '0'),
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arg => (others => '0'));
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rkastl |
type aSdCmdToken is record
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rkastl |
startbit : std_ulogic; -- cSdStartBit
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transbit : std_ulogic;
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content : aSdCmdContent;
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crc7 : std_ulogic_vector(6 downto 0); -- CRC of content
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endbit : std_ulogic; --cSdEndBit
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rkastl |
end record aSdCmdToken;
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rkastl |
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rkastl |
constant cDefaultSdCmdToken : aSdCmdToken := (
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startbit => cActivated,
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transbit => cActivated,
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content => cDefaultSdCmdContent,
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crc7 => (others => '0'),
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endbit => cInactivated);
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rkastl |
-- SD Card Regs
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subtype aVoltageWindow is std_ulogic_vector(23 downto 15);
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constant cVoltageWindow : aVoltageWindow := (others => '1');
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rkastl |
constant cSdR3Id : aSdCmdId := (others => '1');
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constant cSdR2Id : aSdCmdId := (others => '1');
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rkastl |
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type aSdRegOCR is record
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voltagewindow : aVoltageWindow;
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rkastl |
ccs : std_ulogic;
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nBusy : std_ulogic;
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rkastl |
end record aSdRegOCR;
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rkastl |
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subtype aSdCardStatus is std_ulogic_vector(31 downto 0);
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rkastl |
constant cSdStatusReadyForDataBit : natural := 8;
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constant cDefaultSdCardStatus : aSdCardStatus := (others => '0');
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rkastl |
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constant cSdOCRQuery : aSdRegOCR := (
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voltagewindow => (others => '0'),
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rkastl |
ccs => '0',
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nBusy => '0');
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rkastl |
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function OCRToArg (ocr : in aSdRegOCR) return aSdCmdArg;
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function ArgToOcr (arg : in aSdCmdArg) return aSdRegOCR;
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subtype aSdCIDMID is std_ulogic_vector(7 downto 0);
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subtype aSdCIDOID is std_ulogic_vector(15 downto 0);
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subtype aSdCIDPNM is std_ulogic_vector(39 downto 0);
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subtype aSdCIDPRV is std_ulogic_vector(7 downto 0);
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subtype aSdCIDPSN is std_ulogic_vector(31 downto 0);
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subtype aSdCIDMDT is std_ulogic_vector(11 downto 0);
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type aSdRegCID is record
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rkastl |
mid : aSdCIDMID;
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oid : aSdCIDOID;
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name : aSdCIDPNM;
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revision : aSdCIDPRV;
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rkastl |
serialnumber : aSdCIDPSN;
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rkastl |
date : aSdCIDMDT;
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rkastl |
end record;
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constant cCIDLength : natural := 127;
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constant cDefaultSdRegCID : aSdRegCID := (
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rkastl |
mid => (others => '0'),
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oid => (others => '0'),
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name => (others => '0'),
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revision => (others => '0'),
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rkastl |
serialnumber => (others => '0'),
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rkastl |
date => (others => '0'));
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rkastl |
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function UpdateCID(icid : in aSdRegCID; data : in std_ulogic; pos : in
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natural) return aSdRegCID;
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rkastl |
subtype aSdRCA is std_ulogic_vector(15 downto 0);
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constant cDefaultRCA : aSdRCA := (others => '0');
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rkastl |
constant cSdWideModeBit : natural := 31-(63-50); -- first word
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rkastl |
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rkastl |
-- Data types
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rkastl |
subtype aSdData is std_ulogic_vector(3 downto 0);
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constant cSdStartBits : aSdData := (others => cSdStartBit);
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constant cSdEndBits : aSdData := (others => cSdEndBit);
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rkastl |
constant cBlocklen : natural := 512 * 8; -- 512 bytes
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subtype aSdDataBlock is std_ulogic_vector(cBlocklen - 1 downto 0);
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type aSdDataBusMode is (standard, wide);
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rkastl |
type aSdDataMode is (usual, widewidth);
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rkastl |
type aSdDataBits is (ScrBits, SwitchFunctionBits);
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rkastl |
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rkastl |
constant cScrBitsCount : natural := 4096 - 64 + 7; -- expressed in bits
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constant cSwitchFunctionBitsCount : natural := 4096 - 512 + 7; -- expressed in bits
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rkastl |
constant cWideModeBitAddr : natural := 50;
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constant cHighSpeedBitAddr : natural := 401;
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constant cSwitchFunctionBitLowAddr : natural := 376;
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rkastl |
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rkastl |
-- Types for entities
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rkastl |
-- between SdController and SdCmd
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rkastl |
type aSdCmdFromController is record
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rkastl |
Content : aSdCmdContent; -- id and arg to sent to card
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Valid : std_ulogic; -- gets asserted when Content is valid and can be sent to card
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rkastl |
ExpectCID : std_ulogic; -- gets asserted when next response is R2
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rkastl |
CheckCrc : std_ulogic; -- gets asserted when CRC has to be checked (exceptions is R3)
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rkastl |
end record aSdCmdFromController;
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rkastl |
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rkastl |
type aSdCmdToController is record
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rkastl |
Ack : std_ulogic; -- Gets asserted when crc was sent, but endbit was not. This way we can minimize the wait time between sending 2 cmds.
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Receiving : std_ulogic; -- gets asserted when a response is received currently
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Content : aSdCmdContent; -- received id and arg, see valid
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Valid : std_ulogic; -- gets asserted when CmdContent is valid (therefore a cmd was received and can be saved)
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Err : std_ulogic; -- gets asserted when an error occurred during receiving a cmd, for example the crc check does not hold
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Cid : aSdRegCID; -- received CID register of the card, see valid
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rkastl |
end record aSdCmdToController;
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rkastl |
constant cDefaultSdCmdToController : aSdCmdToController := (
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Ack => cInactivated,
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rkastl |
Receiving => cInactivated,
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Valid => cInactivated,
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Content => cDefaultSdCmdContent,
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Err => cInactivated,
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Cid => cDefaultSdRegCID);
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rkastl |
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rkastl |
constant cDataRamAddrWidth : natural := 7;
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constant cDataRamDataWidth : natural := 32;
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subtype aWord is std_ulogic_vector(cDataRamDataWidth - 1 downto 0);
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subtype aAddr is natural range 0 to 2**cDataRamAddrWidth - 1;
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type aSdControllerToRam is record
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Addr : aAddr;
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end record aSdControllerToRam;
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constant cDefaultSdControllerToRam : aSdControllerToRam := (Addr => 0);
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type aSdControllerFromRam is record
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Data : aWord;
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end record aSdControllerFromRam;
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rkastl |
-- between SdController and SdData
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type aSdDataFromController is record
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rkastl |
Mode : aSdDataBusMode; -- select 1 bit or 4 bit mode
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DataMode : aSdDataMode; -- select usual or wide width data
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ExpectBits : aSdDataBits; -- how many bits are expected in wide with data mode
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Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
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CheckBusy : std_ulogic; -- check for busy signaling
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157 |
rkastl |
DisableRb : std_ulogic; -- disable read back: do not save read data to fifo
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rkastl |
end record aSdDataFromController;
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rkastl |
constant cDefaultSdDataFromController : aSdDataFromController := (
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rkastl |
Mode => standard,
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DataMode => usual,
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ExpectBits => ScrBits,
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Valid => cInactivated,
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rkastl |
CheckBusy => cInactivated,
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DisableRb => cActivated);
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rkastl |
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rkastl |
type aSpeedBits is record
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HighSpeedSupported : std_ulogic;
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SwitchFunctionOK : std_ulogic_vector(3 downto 0); -- 0x01 when ok
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end record aSpeedBits;
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constant cDefaultSpeedBits : aSpeedBits := (
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HighSpeedSupported => '0',
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SwitchFunctionOK => (others => '0'));
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rkastl |
type aSdDataToController is record
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Ack : std_ulogic; -- gets asserted when a datablock was sent to the card
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Receiving : std_ulogic; -- gets asserted when a datablock is currently received
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Valid : std_ulogic; -- gets asserted when DataBlock is valid and therefore it was received correctly
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Busy : std_ulogic; -- gets asserted when the card returns busy
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Err : std_ulogic; -- gets asserted when an error occurred during receiving a data block (CRC)
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126 |
rkastl |
SpeedBits : aSpeedBits; -- gets set, when data for check or switch function cmd is received (DataMode = widewidth and ExpectBits = SwitchFunctionBits
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WideMode : std_ulogic; -- gets set, when scr is read (datamode = widewidth and ExpectBits = ScrBits)
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rkastl |
end record aSdDataToController;
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constant cDefaultSdDataToController : aSdDataToController := (
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Ack => cInactivated,
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Receiving => cInactivated,
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Valid => cInactivated,
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Busy => cInactivated,
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rkastl |
Err => cInactivated,
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SpeedBits => cDefaultSpeedBits,
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WideMode => cInactivated);
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92 |
rkastl |
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240 |
109 |
rkastl |
-- SdData to Ram
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type aSdDataToRam is record
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En : std_ulogic;
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Addr : aAddr;
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Data : aWord;
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We : std_ulogic;
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end record aSdDataToRam;
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constant cDefaultSdDataToRam : aSdDataToRam := (
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En => cInactivated,
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Addr => 0,
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Data => (others => '0'),
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We => cInactivated);
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type aSdDataFromRam is record
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Data : aWord;
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end record aSdDataFromRam;
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257 |
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258 |
92 |
rkastl |
-- between SdController and wishbone interface
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259 |
88 |
rkastl |
type aSdRegisters is record
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260 |
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CardStatus : aSdCardStatus;
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261 |
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end record aSdRegisters;
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262 |
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263 |
92 |
rkastl |
-- constants for SdController
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264 |
57 |
rkastl |
subtype aRCA is std_ulogic_vector(15 downto 0);
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265 |
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constant cSdDefaultRCA : aRCA := (others => '0');
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267 |
29 |
rkastl |
-- command ids
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268 |
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-- abbreviations:
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269 |
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-- RCA: relative card address
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270 |
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271 |
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constant cSdCmdGoIdleState : aSdCmdId := std_ulogic_vector(to_unsigned(0,
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cSdCmdIdHigh)); -- no args
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273 |
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274 |
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constant cSdCmdAllSendCID : aSdCmdId := std_ulogic_vector(to_unsigned(2,
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cSdCmdIdHigh)); -- no args
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276 |
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277 |
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constant cSdCmdSendRelAdr : aSdCmdId := std_ulogic_vector(to_unsigned(3,
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cSdCmdIdHigh)); -- no args
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279 |
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280 |
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constant cSdCmdSetDSR : aSdCmdId := std_ulogic_vector(to_unsigned(4,
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cSdCmdIdHigh)); -- [31:16] DSR
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282 |
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283 |
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constant cSdCmdSelCard : aSdCmdId := std_ulogic_vector(to_unsigned(7,
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cSdCmdIdHigh)); -- [31:16] RCA
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285 |
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286 |
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constant cSdCmdDeselCard : aSdCmdId := cSdCmdSelCard; -- [31:16] RCA
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287 |
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288 |
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constant cSdCmdSendIfCond : aSdCmdId := std_ulogic_vector(to_unsigned(8,
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289 |
54 |
rkastl |
cSdCmdIdHigh));
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290 |
29 |
rkastl |
|
291 |
54 |
rkastl |
constant cSdDefaultVoltage : std_ulogic_vector(3 downto 0) := "0001"; -- 2.7
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292 |
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-- - 3.6 V
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293 |
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constant cCheckpattern : std_ulogic_vector(7 downto 0) := "10101010";
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-- recommended
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295 |
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296 |
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constant cSdArgVoltage : aSdCmdArg :=
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297 |
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"00000000000000000000" & -- reserved
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298 |
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cSdDefaultVoltage & -- supply voltage
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299 |
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cCheckPattern;
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300 |
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301 |
29 |
rkastl |
constant cSdCmdSendCSD : aSdCmdId := std_ulogic_vector(to_unsigned(9,
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302 |
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cSdCmdIdHigh)); -- [31:16] RCA
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303 |
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304 |
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constant cSdCmdSendCID : aSdCmdId := std_ulogic_vector(to_unsigned(10,
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305 |
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cSdCmdIdHigh)); -- [31:16] RCA
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306 |
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307 |
|
|
constant cSdCmdStopTrans : aSdCmdId := std_ulogic_vector(to_unsigned(12,
|
308 |
|
|
cSdCmdIdHigh)); -- no args
|
309 |
|
|
|
310 |
|
|
constant cSdCmdSendStatus : aSdCmdId := std_ulogic_vector(to_unsigned(13,
|
311 |
|
|
cSdCmdIdHigh)); -- [31:16] RCA
|
312 |
|
|
|
313 |
57 |
rkastl |
constant cSdNextIsACMD : aSdCmdId := std_ulogic_vector(to_unsigned(55,
|
314 |
|
|
cSdCmdIdHigh));
|
315 |
|
|
constant cSdACMDArg : aSdCmdArg := cSdDefaultRCA & X"0000"; -- [31:16] RCA
|
316 |
|
|
constant cSdArgAppCmdPos : natural := 5;
|
317 |
|
|
|
318 |
113 |
rkastl |
constant cSdCmdReadSingleBlock : aSdCmdId := std_ulogic_vector(to_unsigned(17, cSdCmdIdHigh));
|
319 |
123 |
rkastl |
constant cSdCmdWriteSingleBlock : aSdCmdId := std_ulogic_vector(to_unsigned(24, cSdCmdIdHigh));
|
320 |
113 |
rkastl |
|
321 |
57 |
rkastl |
constant cSdCmdACMD41 : aSdCmdId := std_ulogic_vector(to_unsigned(41, cSdCmdIdHigh));
|
322 |
99 |
rkastl |
constant cSdCmdSendSCR : aSdCmdId := std_ulogic_vector(to_unsigned(51, cSdCmdIdHigh));
|
323 |
102 |
rkastl |
constant cSdCmdSetBusWidth : aSdCmdId := std_ulogic_vector(to_unsigned(6, cSdCmdIdHigh)); -- [31:2] stuff, [1:0] bus width
|
324 |
|
|
constant cSdWideBusWidth : std_ulogic_vector(1 downto 0) := "10";
|
325 |
|
|
constant cSdStandardBusWidth : std_ulogic_vector(1 downto 0) := "00";
|
326 |
60 |
rkastl |
|
327 |
103 |
rkastl |
constant cSdCmdSwitchFunction : aSdCmdId := std_ulogic_vector(to_unsigned(6, cSdCmdIdHigh));
|
328 |
|
|
-- 31: mode
|
329 |
|
|
constant cSdCmdCheckMode : std_ulogic := '0';
|
330 |
|
|
constant cSdCmdSwitchMode : std_ulogic := '1';
|
331 |
|
|
-- 30:24 reserved
|
332 |
|
|
-- 23:8 function group 6 - 3
|
333 |
|
|
-- 7:4 group 2 for command system
|
334 |
|
|
-- 3:0 group 1 for access mode
|
335 |
104 |
rkastl |
constant cSdCmdCheckSpeedSupport : aSdCmdArg := X"00FFFFF1";
|
336 |
|
|
constant cSdCmdSwitchSpeed : aSdCmdArg := X"80FFFFF1";
|
337 |
126 |
rkastl |
constant cSdHighSpeedFunctionSupportBit : natural := 401;
|
338 |
104 |
rkastl |
constant cSdHighSpeedFunctionGroupLow : natural := 376;
|
339 |
103 |
rkastl |
|
340 |
111 |
rkastl |
type aiSdCmd is record
|
341 |
|
|
Cmd : std_ulogic;
|
342 |
|
|
end record aiSdCmd;
|
343 |
|
|
|
344 |
|
|
type aoSdCmd is record
|
345 |
|
|
Cmd : std_ulogic;
|
346 |
|
|
En : std_ulogic;
|
347 |
|
|
end record aoSdCmd;
|
348 |
|
|
|
349 |
132 |
rkastl |
|
350 |
111 |
rkastl |
type aiSdData is record
|
351 |
132 |
rkastl |
Data : aSdData;
|
352 |
111 |
rkastl |
end record aiSdData;
|
353 |
|
|
|
354 |
|
|
type aoSdData is record
|
355 |
132 |
rkastl |
Data : aSdData;
|
356 |
|
|
En : aSdData;
|
357 |
111 |
rkastl |
end record aoSdData;
|
358 |
132 |
rkastl |
|
359 |
|
|
constant cDefaultSdData : aoSdData := (
|
360 |
|
|
Data => (others => '0'),
|
361 |
|
|
En => (others => '0'));
|
362 |
126 |
rkastl |
|
363 |
29 |
rkastl |
end package Sd;
|
364 |
|
|
|
365 |
60 |
rkastl |
package body Sd is
|
366 |
|
|
|
367 |
|
|
function OCRToArg (ocr : in aSdRegOCR) return aSdCmdArg is
|
368 |
|
|
variable temp : aSdCmdArg;
|
369 |
|
|
begin
|
370 |
|
|
temp := ocr.nBusy & ocr.ccs & "000000" & ocr.voltagewindow &
|
371 |
|
|
"000000000000000";
|
372 |
|
|
return temp;
|
373 |
|
|
end function OCRtoArg;
|
374 |
|
|
|
375 |
|
|
function ArgToOcr (arg : in aSdCmdArg) return aSdRegOCR is
|
376 |
|
|
variable ocr : aSdRegOCR;
|
377 |
|
|
begin
|
378 |
|
|
ocr.nBusy := arg(31);
|
379 |
|
|
ocr.ccs := arg(30);
|
380 |
|
|
ocr.voltagewindow := arg(23 downto 15);
|
381 |
|
|
return ocr;
|
382 |
|
|
end function ArgToOcr;
|
383 |
|
|
|
384 |
62 |
rkastl |
function UpdateCID(icid : in aSdRegCID; data : in std_ulogic; pos : in
|
385 |
|
|
natural) return aSdRegCID is
|
386 |
|
|
variable cid : aSdRegCID;
|
387 |
|
|
begin
|
388 |
|
|
cid := icid;
|
389 |
|
|
|
390 |
|
|
if (pos <= 127 and pos >= 120) then
|
391 |
|
|
cid.mid(pos-120) := data;
|
392 |
|
|
elsif (pos <= 119 and pos >= 104) then
|
393 |
|
|
cid.oid(pos-104) := data;
|
394 |
|
|
elsif (pos <= 103 and pos >= 64) then
|
395 |
|
|
cid.name(pos-64) := data;
|
396 |
|
|
elsif (pos <= 63 and pos >= 56) then
|
397 |
|
|
cid.revision(pos-56) := data;
|
398 |
|
|
elsif (pos <= 55 and pos >= 24) then
|
399 |
|
|
cid.serialnumber(pos-24) := data;
|
400 |
|
|
elsif (pos <= 19 and pos >= 8) then
|
401 |
|
|
cid.date(pos-8) := data;
|
402 |
|
|
end if;
|
403 |
|
|
|
404 |
|
|
return cid;
|
405 |
|
|
end function UpdateCID;
|
406 |
|
|
|
407 |
60 |
rkastl |
end package body Sd;
|
408 |
|
|
|