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-- SDHC-SC-Core
-- Secure Digital High Capacity Self Configuring Core
-- 
-- (C) Copyright 2010, Rainer Kastl
-- All rights reserved.
-- 
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
--       notice, this list of conditions and the following disclaimer in the
--       documentation and/or other materials provided with the distribution.
--     * Neither the name of the <organization> nor the
--       names of its contributors may be used to endorse or promote products
--       derived from this software without specific prior written permission.
-- 
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-- File        : SdCmd-Rtl-ea.vhdl
-- Owner       : Rainer Kastl
-- Description : FSM for low level sending of SD commands and receiving responses
-- Links       : SD Spec 2.00
-- 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.Global.all;
use work.Sd.all;
use work.CRCs.all;
 
entity SdCmd is
        port (
                iClk         : in std_ulogic; -- Clk, rising edge
                iRstSync     : in std_ulogic; -- Reset, synchronous active high
 
                iStrobe      : in std_ulogic; -- Strobe to send data
 
                iFromController : in aSdCmdFromController;
                oToController   : out aSdCmdToController;
 
                -- SDCard
                iCmd : in aiSdCmd;
                oCmd : out aoSdCmd
        );
end entity SdCmd;
 
architecture Rtl of SdCmd is
 
        type aSdCmdState is (idle, sending, receiving);
        type aRegion is (startbit, transbit, cmdid, arg, cid, crc, endbit, waitstate);
 
        subtype aCounter is unsigned(integer(log2(real(128))) - 1 downto 0);
 
        type aRegSet is record
                State         : aSdCmdState;
                Region        : aRegion;
                Counter       : aCounter;
                ReceivedToken : aSdCmdToken;
                Cid           : aSdRegCID;
        end record aRegSet;
 
        constant cDefaultRegSet : aRegSet := (
        State         => idle,
        Region        => startbit,
        Counter       => to_unsigned(0, aCounter'length),
        ReceivedToken => cDefaultSdCmdToken,
        Cid           => cDefaultSdRegCID);
 
        type aOutputRegSet is record
                Controller : aSdCmdToController;
                Cmd        : aoSdCmd;
        end record aOutputRegSet;
 
        constant cDefaultOutputRegSet : aOutputRegSet := (
        Controller => cDefaultSdCmdToController,
        Cmd => (Cmd       => '0',
        En         => '0'));
 
        type aCrcOut is record
                Clear  : std_ulogic;
                DataIn : std_ulogic;
                Data   : std_ulogic;
        end record aCrcOut;
 
        constant cDefaultCrcOut : aCrcOut := (
        Clear  => cInactivated,
        DataIn => cInactivated,
        Data   => cInactivated);
 
        signal SerialCrc, CrcCorrect : std_ulogic;
        signal CrcOut : aCrcOut;
 
        signal R, NextR : aRegSet;
        signal O, NextO : aOutputRegSet;
 
begin
 
        oToController <= O.Controller;
        oCmd <= O.Cmd;
 
        -- State register
        CmdStateReg : process (iClk)
        begin
                if iClk'event and iClk = cActivated then
                        if iRstSync = cActivated then
                                R <= cDefaultRegSet;
                                O <= cDefaultOutputRegSet;
                        else
 
                                if (iStrobe = cActivated) then
                                        R <= NextR;
                                        O <= NextO;
                                end if;
                        end if;
                end if;
        end process CmdStateReg;
 
        -- Comb. process
        NextStateAndOutput : process (iFromController, iCmd.Cmd, SerialCrc, CrcCorrect, iStrobe, R)
 
                procedure NextStateWhenAllSent (constant nextlength : in natural; constant toRegion : in aRegion) is
                begin
                        if (R.Counter > 0) then
                                NextR.Counter <= R.Counter - 1;
                        else
                                NextR.Counter <= to_unsigned(nextlength, NextR.Counter'length);
                                NextR.Region <= toRegion;
                        end if;
                end procedure NextStateWhenAllSent;
 
                procedure ShiftIntoCrc(constant data : in std_ulogic) is
                begin
                        CrcOut.DataIn <= cActivated;
                        CrcOut.Data   <= data;
                end procedure;
 
                procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
                begin
                        NextO.Cmd.En  <= cActivated;
                        NextO.Cmd.Cmd <= container(to_integer(R.Counter));
 
                        ShiftIntoCrc(container(to_integer(R.Counter)));
                        NextStateWhenAllSent(nextlength, toRegion);
                end procedure SendBitsAndCalcCrc;
 
                procedure RecvBitsAndCalcCrc (signal container : out std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
                begin
                        container(to_integer(R.Counter)) <= iCmd.Cmd;
                        ShiftIntoCrc(iCmd.Cmd);
                        NextStateWhenAllSent(nextlength, toRegion);
                end procedure RecvBitsAndCalcCrc;
 
        begin
                -- defaults
                NextR                    <= R;
                NextO                    <= cDefaultOutputRegSet;
                NextO.Controller.Content <= R.ReceivedToken.content;
                NextO.Controller.Cid     <= R.Cid;
                CrcOut                   <= cDefaultCrcOut;
 
                case R.State is
                        when idle =>
                                        -- Start receiving or start transmitting
                                if (iCmd.Cmd = cSdStartBit) then
                                        -- Start receiving
                                        ShiftIntoCrc(iCmd.Cmd);
 
                                        NextR.ReceivedToken.startbit <= iCmd.Cmd;
                                        NextR.State                  <= receiving;
                                        NextR.Region                 <= transbit;
 
                                elsif (iFromController.Valid = cActivated) then
                                        -- Start sending
                                        NextR.State  <= sending;
                                        NextR.Region <= startbit;
 
                                end if;
 
                        when sending =>
                                NextO.Cmd.En <= cActivated;
 
                                case R.Region is
                                        when startbit =>
                                                NextO.Cmd.Cmd  <= cSdStartBit;
                                                NextR.Region <= transbit;
                                                ShiftIntoCrc(cSdStartBit);
 
                                        when transbit =>
                                                NextO.Cmd.Cmd   <= cSdTransBitHost;
                                                NextR.Counter <= to_unsigned(iFromController.Content.id'high, aCounter'length);
                                                NextR.Region <= cmdid;
                                                ShiftIntoCrc(cSdTransBitHost);
 
                                        when cmdid =>
                                                SendBitsAndCalcCrc(iFromController.Content.id, arg,     iFromController.Content.arg'high);
 
                                        when arg =>
                                                SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);
 
                                        when crc =>
                                                NextO.Cmd.Cmd <= SerialCrc;
 
                                                if (R.Counter > 0) then
                                                        NextR.Counter <= R.Counter - 1;
 
                                                else
                                                        NextR.Region         <= endbit;
                                                        NextO.Controller.Ack <= cActivated;
                                                end if;
 
                                        when endbit =>
                                                NextO.Cmd.Cmd <= cSdEndBit;
                                                NextR.Region  <= waitstate;
 
                                        when waitstate =>
                                                NextO.Cmd.En <= cInactivated;
                                                NextR.State  <= idle;
                                                NextR.Region <= startbit;
 
                                        when others =>
                                                report "SdCmd: Region not handled" severity error;
 
                                end case;
 
                        when receiving =>
                                NextO.Controller.Receiving   <= cActivated;
 
                                case R.Region is
                                        when transbit =>
                                                NextR.ReceivedToken.transbit <= iCmd.Cmd;
                                                NextR.Counter <= to_unsigned(NextR.ReceivedToken.Content.id'high, NextR.Counter'length);
                                                NextR.Region <= cmdid;
                                                ShiftIntoCrc(iCmd.Cmd);
 
                                        when cmdid =>
                                                if (iFromController.ExpectCID = cInactivated) then
                                                        RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, arg, NextR.ReceivedToken.Content.arg'high);
 
                                                elsif (iFromController.ExpectCID = cActivated) then
                                                        RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, cid, cCIDLength-8);
                                                        CrcOut.Clear <= cActivated;
 
                                                end if;
 
                                        when arg =>
                                                RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.arg, crc, crc7'high-1);
 
                                        when cid =>
                                                NextR.Cid <= UpdateCID(R.Cid, iCmd.Cmd, to_integer(R.Counter)+8);
                                                ShiftIntoCrc(iCmd.Cmd);
                                                NextStateWhenAllSent(crc7'high-1, crc);
 
                                        when crc =>
                                                NextR.ReceivedToken.crc7(to_integer(R.Counter)) <= iCmd.Cmd;
                                                ShiftIntoCrc(iCmd.Cmd);
 
                                                if (R.Counter > 0) then
                                                        NextR.Counter <= R.Counter - 1;
                                                else
                                                        NextR.Region <= endbit;
                                                end if;
 
                                        when endbit =>
                                                NextR.ReceivedToken.endbit <= iCmd.Cmd;
 
                                                        -- check 
                                                if (iFromController.CheckCrc = cActivated) then
                                                        if (CrcCorrect = cActivated and R.ReceivedToken.transbit = cSdTransBitSlave) then
                                                                NextO.Controller.Valid <= cActivated;
 
                                                        else
                                                                NextO.Controller.Err <= cActivated;
 
                                                        end if;
                                                else
                                                        NextO.Controller.Valid <= cActivated;
                                                end if;
 
                                                NextR.State <= idle;
                                                NextR.Region <= startbit;
 
                                        when others =>
                                                report "SdCmd : Region not handled" severity error;
 
                                end case;
 
                        when others =>
                                report "SdCmd: State not handled" severity error;
 
                end case;
 
        end process NextStateAndOutput;
 
        CRC7_inst: entity work.Crc
        generic map(
                gPolynom => crc7)
        port map(
                iClk         => iClk,
                iRstSync     => iRstSync,
                iClear           => CrcOut.Clear,
                iStrobe      => iStrobe,
                iDataIn      => CrcOut.DataIn,
                iData        => CrcOut.Data,
                oIsCorrect   => CrcCorrect,
                oSerial      => SerialCrc);
 
end architecture Rtl;

Line No.	Rev	Author	Line
1	164	rkastl	`-- SDHC-SC-Core`
2			`-- Secure Digital High Capacity Self Configuring Core`
3	92	rkastl	`--`
4	170	rkastl	`-- (C) Copyright 2010, Rainer Kastl`
5			`-- All rights reserved.`
6	164	rkastl	`--`
7	170	rkastl	`-- Redistribution and use in source and binary forms, with or without`
8			`-- modification, are permitted provided that the following conditions are met:`
9			`-- * Redistributions of source code must retain the above copyright`
10			`-- notice, this list of conditions and the following disclaimer.`
11			`-- * Redistributions in binary form must reproduce the above copyright`
12			`-- notice, this list of conditions and the following disclaimer in the`
13			`-- documentation and/or other materials provided with the distribution.`
14			`-- * Neither the name of the <organization> nor the`
15			`-- names of its contributors may be used to endorse or promote products`
16			`-- derived from this software without specific prior written permission.`
17	164	rkastl	`--`
18	170	rkastl	`-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND`
19			`-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
20			`-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
21			`-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY`
22			`-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
23			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
27			`-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28	164	rkastl	`--`
29			`-- File : SdCmd-Rtl-ea.vhdl`
30			`-- Owner : Rainer Kastl`
31			`-- Description : FSM for low level sending of SD commands and receiving responses`
32			`-- Links : SD Spec 2.00`
33			`--`
34	34	rkastl
35			`library ieee;`
36			`use ieee.std_logic_1164.all;`
37			`use ieee.numeric_std.all;`
38			`use ieee.math_real.all;`
39			`use work.Global.all;`
40			`use work.Sd.all;`
41			`use work.CRCs.all;`
42
43			`entity SdCmd is`
44			`port (`
45	105	rkastl	`iClk : in std_ulogic; -- Clk, rising edge`
46	165	rkastl	`iRstSync : in std_ulogic; -- Reset, synchronous active high`
47	136	rkastl
48	105	rkastl	`iStrobe : in std_ulogic; -- Strobe to send data`
49	34	rkastl
50	37	rkastl	`iFromController : in aSdCmdFromController;`
51	105	rkastl	`oToController : out aSdCmdToController;`
52	37	rkastl
53			`-- SDCard`
54	111	rkastl	`iCmd : in aiSdCmd;`
55			`oCmd : out aoSdCmd`
56	34	rkastl	`);`
57			`end entity SdCmd;`
58
59			`architecture Rtl of SdCmd is`
60
61	83	rkastl	`type aSdCmdState is (idle, sending, receiving);`
62	111	rkastl	`type aRegion is (startbit, transbit, cmdid, arg, cid, crc, endbit, waitstate);`
63	136	rkastl
64	83	rkastl	`subtype aCounter is unsigned(integer(log2(real(128))) - 1 downto 0);`
65	37	rkastl
66	83	rkastl	`type aRegSet is record`
67			`State : aSdCmdState;`
68			`Region : aRegion;`
69			`Counter : aCounter;`
70			`ReceivedToken : aSdCmdToken;`
71			`Cid : aSdRegCID;`
72			`end record aRegSet;`
73
74			`constant cDefaultRegSet : aRegSet := (`
75			`State => idle,`
76			`Region => startbit,`
77			`Counter => to_unsigned(0, aCounter'length),`
78			`ReceivedToken => cDefaultSdCmdToken,`
79			`Cid => cDefaultSdRegCID);`
80
81			`type aOutputRegSet is record`
82	136	rkastl	`Controller : aSdCmdToController;`
83			`Cmd : aoSdCmd;`
84	83	rkastl	`end record aOutputRegSet;`
85
86			`constant cDefaultOutputRegSet : aOutputRegSet := (`
87			`Controller => cDefaultSdCmdToController,`
88	111	rkastl	`Cmd => (Cmd => '0',`
89			`En => '0'));`
90	83	rkastl
91	165	rkastl	`type aCrcOut is record`
92	83	rkastl	`Clear : std_ulogic;`
93	37	rkastl	`DataIn : std_ulogic;`
94	83	rkastl	`Data : std_ulogic;`
95	37	rkastl	`end record aCrcOut;`
96	39	rkastl
97	62	rkastl	`constant cDefaultCrcOut : aCrcOut := (`
98	83	rkastl	`Clear => cInactivated,`
99	62	rkastl	`DataIn => cInactivated,`
100	83	rkastl	`Data => cInactivated);`
101	62	rkastl
102	56	rkastl	`signal SerialCrc, CrcCorrect : std_ulogic;`
103	83	rkastl	`signal CrcOut : aCrcOut;`
104	34	rkastl
105	83	rkastl	`signal R, NextR : aRegSet;`
106			`signal O, NextO : aOutputRegSet;`
107	56	rkastl
108	34	rkastl	`begin`
109
110	83	rkastl	`oToController <= O.Controller;`
111	111	rkastl	`oCmd <= O.Cmd;`
112	77	rkastl
113	34	rkastl	`-- State register`
114	165	rkastl	`CmdStateReg : process (iClk)`
115	34	rkastl	`begin`
116	165	rkastl	`if iClk'event and iClk = cActivated then`
117			`if iRstSync = cActivated then`
118			`R <= cDefaultRegSet;`
119			`O <= cDefaultOutputRegSet;`
120			`else`
121	83	rkastl
122	165	rkastl	`if (iStrobe = cActivated) then`
123			`R <= NextR;`
124			`O <= NextO;`
125			`end if;`
126	111	rkastl	`end if;`
127	34	rkastl	`end if;`
128			`end process CmdStateReg;`
129
130			`-- Comb. process`
131	111	rkastl	`NextStateAndOutput : process (iFromController, iCmd.Cmd, SerialCrc, CrcCorrect, iStrobe, R)`
132
133	83	rkastl	`procedure NextStateWhenAllSent (constant nextlength : in natural; constant toRegion : in aRegion) is`
134	34	rkastl	`begin`
135	83	rkastl	`if (R.Counter > 0) then`
136	111	rkastl	`NextR.Counter <= R.Counter - 1;`
137	34	rkastl	`else`
138	111	rkastl	`NextR.Counter <= to_unsigned(nextlength, NextR.Counter'length);`
139			`NextR.Region <= toRegion;`
140	34	rkastl	`end if;`
141			`end procedure NextStateWhenAllSent;`
142
143	56	rkastl	`procedure ShiftIntoCrc(constant data : in std_ulogic) is`
144			`begin`
145	83	rkastl	`CrcOut.DataIn <= cActivated;`
146			`CrcOut.Data <= data;`
147	56	rkastl	`end procedure;`
148
149	83	rkastl	`procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is`
150	39	rkastl	`begin`
151	111	rkastl	`NextO.Cmd.En <= cActivated;`
152			`NextO.Cmd.Cmd <= container(to_integer(R.Counter));`
153	83	rkastl
154			`ShiftIntoCrc(container(to_integer(R.Counter)));`
155			`NextStateWhenAllSent(nextlength, toRegion);`
156	39	rkastl	`end procedure SendBitsAndCalcCrc;`
157
158	83	rkastl	`procedure RecvBitsAndCalcCrc (signal container : out std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is`
159	56	rkastl	`begin`
160	111	rkastl	`container(to_integer(R.Counter)) <= iCmd.Cmd;`
161			`ShiftIntoCrc(iCmd.Cmd);`
162	83	rkastl	`NextStateWhenAllSent(nextlength, toRegion);`
163	56	rkastl	`end procedure RecvBitsAndCalcCrc;`
164
165	36	rkastl	`begin`
166			`-- defaults`
167	83	rkastl	`NextR <= R;`
168			`NextO <= cDefaultOutputRegSet;`
169			`NextO.Controller.Content <= R.ReceivedToken.content;`
170			`NextO.Controller.Cid <= R.Cid;`
171			`CrcOut <= cDefaultCrcOut;`
172	39	rkastl
173	83	rkastl	`case R.State is`
174	34	rkastl	`when idle =>`
175	105	rkastl	`-- Start receiving or start transmitting`
176	111	rkastl	`if (iCmd.Cmd = cSdStartBit) then`
177	136	rkastl	`-- Start receiving`
178	111	rkastl	`ShiftIntoCrc(iCmd.Cmd);`
179	136	rkastl
180	111	rkastl	`NextR.ReceivedToken.startbit <= iCmd.Cmd;`
181	136	rkastl	`NextR.State <= receiving;`
182			`NextR.Region <= transbit;`
183	105	rkastl
184	56	rkastl	`elsif (iFromController.Valid = cActivated) then`
185	136	rkastl	`-- Start sending`
186			`NextR.State <= sending;`
187	111	rkastl	`NextR.Region <= startbit;`
188	136	rkastl
189	37	rkastl	`end if;`
190	34	rkastl
191	83	rkastl	`when sending =>`
192	111	rkastl	`NextO.Cmd.En <= cActivated;`
193	34	rkastl
194	83	rkastl	`case R.Region is`
195			`when startbit =>`
196	111	rkastl	`NextO.Cmd.Cmd <= cSdStartBit;`
197			`NextR.Region <= transbit;`
198	83	rkastl	`ShiftIntoCrc(cSdStartBit);`
199	34	rkastl
200	83	rkastl	`when transbit =>`
201	111	rkastl	`NextO.Cmd.Cmd <= cSdTransBitHost;`
202			`NextR.Counter <= to_unsigned(iFromController.Content.id'high, aCounter'length);`
203			`NextR.Region <= cmdid;`
204	83	rkastl	`ShiftIntoCrc(cSdTransBitHost);`
205	34	rkastl
206	83	rkastl	`when cmdid =>`
207	105	rkastl	`SendBitsAndCalcCrc(iFromController.Content.id, arg, iFromController.Content.arg'high);`
208	34	rkastl
209	83	rkastl	`when arg =>`
210			`SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);`
211	34	rkastl
212	83	rkastl	`when crc =>`
213	111	rkastl	`NextO.Cmd.Cmd <= SerialCrc;`
214	34	rkastl
215	83	rkastl	`if (R.Counter > 0) then`
216	111	rkastl	`NextR.Counter <= R.Counter - 1;`
217	56	rkastl
218	83	rkastl	`else`
219	136	rkastl	`NextR.Region <= endbit;`
220	83	rkastl	`NextO.Controller.Ack <= cActivated;`
221			`end if;`
222	56	rkastl
223	83	rkastl	`when endbit =>`
224	136	rkastl	`NextO.Cmd.Cmd <= cSdEndBit;`
225			`NextR.Region <= waitstate;`
226	56	rkastl
227	111	rkastl	`when waitstate =>`
228			`NextO.Cmd.En <= cInactivated;`
229	136	rkastl	`NextR.State <= idle;`
230	111	rkastl	`NextR.Region <= startbit;`
231
232	83	rkastl	`when others =>`
233			`report "SdCmd: Region not handled" severity error;`
234	62	rkastl
235	83	rkastl	`end case;`
236	56	rkastl
237	83	rkastl	`when receiving =>`
238			`NextO.Controller.Receiving <= cActivated;`
239	56	rkastl
240	83	rkastl	`case R.Region is`
241			`when transbit =>`
242	111	rkastl	`NextR.ReceivedToken.transbit <= iCmd.Cmd;`
243			`NextR.Counter <= to_unsigned(NextR.ReceivedToken.Content.id'high, NextR.Counter'length);`
244			`NextR.Region <= cmdid;`
245			`ShiftIntoCrc(iCmd.Cmd);`
246	56	rkastl
247	83	rkastl	`when cmdid =>`
248			`if (iFromController.ExpectCID = cInactivated) then`
249			`RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, arg, NextR.ReceivedToken.Content.arg'high);`
250	56	rkastl
251	83	rkastl	`elsif (iFromController.ExpectCID = cActivated) then`
252			`RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, cid, cCIDLength-8);`
253			`CrcOut.Clear <= cActivated;`
254
255			`end if;`
256
257			`when arg =>`
258			`RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.arg, crc, crc7'high-1);`
259
260			`when cid =>`
261	111	rkastl	`NextR.Cid <= UpdateCID(R.Cid, iCmd.Cmd, to_integer(R.Counter)+8);`
262			`ShiftIntoCrc(iCmd.Cmd);`
263	83	rkastl	`NextStateWhenAllSent(crc7'high-1, crc);`
264
265			`when crc =>`
266	111	rkastl	`NextR.ReceivedToken.crc7(to_integer(R.Counter)) <= iCmd.Cmd;`
267			`ShiftIntoCrc(iCmd.Cmd);`
268	83	rkastl
269			`if (R.Counter > 0) then`
270	111	rkastl	`NextR.Counter <= R.Counter - 1;`
271	83	rkastl	`else`
272	111	rkastl	`NextR.Region <= endbit;`
273	83	rkastl	`end if;`
274
275			`when endbit =>`
276	111	rkastl	`NextR.ReceivedToken.endbit <= iCmd.Cmd;`
277	83	rkastl
278	105	rkastl	`-- check`
279	89	rkastl	`if (iFromController.CheckCrc = cActivated) then`
280			`if (CrcCorrect = cActivated and R.ReceivedToken.transbit = cSdTransBitSlave) then`
281			`NextO.Controller.Valid <= cActivated;`
282	83	rkastl
283	89	rkastl	`else`
284			`NextO.Controller.Err <= cActivated;`
285	83	rkastl
286	89	rkastl	`end if;`
287			`else`
288			`NextO.Controller.Valid <= cActivated;`
289	83	rkastl	`end if;`
290
291	111	rkastl	`NextR.State <= idle;`
292			`NextR.Region <= startbit;`
293	105	rkastl
294	83	rkastl	`when others =>`
295			`report "SdCmd : Region not handled" severity error;`
296
297			`end case;`
298
299			`when others =>`
300	34	rkastl	`report "SdCmd: State not handled" severity error;`
301	83	rkastl
302	34	rkastl	`end case;`
303	83	rkastl
304	34	rkastl	`end process NextStateAndOutput;`
305
306			`CRC7_inst: entity work.Crc`
307	83	rkastl	`generic map(`
308			`gPolynom => crc7)`
309			`port map(`
310			`iClk => iClk,`
311	165	rkastl	`iRstSync => iRstSync,`
312			`iClear => CrcOut.Clear,`
313	105	rkastl	`iStrobe => iStrobe,`
314	83	rkastl	`iDataIn => CrcOut.DataIn,`
315			`iData => CrcOut.Data,`
316			`oIsCorrect => CrcCorrect,`
317			`oSerial => SerialCrc);`
318	34	rkastl
319			`end architecture Rtl;`

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