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[/] [sdhc-sc-core/] [trunk/] [grpSd/] [unitSdTop/] [Files.tcl] - Blame information for rev 185

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1 164 rkastl
# SDHC-SC-Core
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# Secure Digital High Capacity Self Configuring Core
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# 
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# (C) Copyright 2010, Rainer Kastl
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# All rights reserved.
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# 
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#     * Redistributions of source code must retain the above copyright
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#       notice, this list of conditions and the following disclaimer.
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#     * Redistributions in binary form must reproduce the above copyright
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#       notice, this list of conditions and the following disclaimer in the
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#       documentation and/or other materials provided with the distribution.
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#     * Neither the name of the <organization> nor the
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#       names of its contributors may be used to endorse or promote products
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#       derived from this software without specific prior written permission.
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# 
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# 
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# File        : Files.tcl
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# Owner       : Rainer Kastl
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# Description : 
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# Links       : 
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# 
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set pkgs {Global Global
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        Sd Sd
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        Crc CRCs
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        Rs232 Rs232
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        Components Ics307Values
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        Wishbone Wishbone
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        Sd SdWb
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}
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set units {Crc Crc {Rtl}
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        Sd SdCmd {Rtl}
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        StrobesClocks Counter {Rtl}
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        Sd SdController {Rtl}
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        Sd SdData {Rtl}
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        Cyclone2 CycSimpleDualPortedRam {Syn}
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        Memory SimpleDualPortedRam {Rtl}
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        Memory SinglePortedRam {Rtl}
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        StrobesClocks StrobeGen {Rtl}
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        Sd SdWbSlave {Rtl}
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        Sd SdClockMaster {Rtl}
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        Sd SdCardSynchronizer {Rtl}
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        Synchronization Synchronizer {Rtl}
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        StrobesClocks EdgeDetector {Rtl}
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        Sd SdWbSdControllerSync {Rtl}
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        Sd SdClkDomain {Rtl}
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        Cyclone2 WriteDataFifo {Syn}
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        Sd SdTop {Rtl}}
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