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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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rkastl |
-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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rkastl |
--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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rkastl |
--
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rkastl |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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rkastl |
--
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-- File : tbEdgeDetection-Bhv-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description :
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-- Links : See EDS at FH Hagenberg
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.Global.all;
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entity tbEdgeDet is
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end entity tbEdgeDet;
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architecture Bhv of tbEdgeDet is
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-- generics
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constant cClkFrequency : natural := 25E6;
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constant simulationTime : time := 1200 ns;
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-- component ports
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signal Clk : std_ulogic := cInactivated;
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signal nResetAsync : std_ulogic := cnInactivated;
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signal EdgeDetected, ClearEdgeDetected, iLine : std_ulogic;
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signal EdgeDetected2, EdgeDetected3 : std_ulogic;
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signal EdgeDetected4, EdgeDetected5 : std_ulogic;
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signal EdgeDetected6 : std_ulogic;
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begin -- architecture Bhv
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-- component instantiation
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DUT : entity work.EdgeDetector(Rtl)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected);
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DUT2 : entity work.EdgeDetector(Rtl)
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generic map (
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gEdgeDetection => cDetectFallingEdge)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected2);
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DUT3 : entity work.EdgeDetector(Rtl)
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generic map (
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gEdgeDetection => cDetectAnyEdge)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected3);
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DUT4 : entity work.EdgeDetector(Rtl)
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generic map (gOutputRegistered => false)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected4);
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DUT5 : entity work.EdgeDetector(Rtl)
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generic map (
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gEdgeDetection => cDetectFallingEdge,
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gOutputRegistered => false)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected5);
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DUT6 : entity work.EdgeDetector(Rtl)
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generic map (
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gEdgeDetection => cDetectAnyEdge,
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gOutputRegistered => false)
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port map (
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iLine => iLine,
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inResetAsync => nResetAsync,
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iClk => Clk,
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iClearEdgeDetected => ClearEdgeDetected,
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oEdgeDetected => EdgeDetected6);
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Clk <= not Clk after (1 sec / cClkFrequency) / 2;
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nResetAsync <= cnInactivated after 0 ns,
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cnActivated after 100 ns,
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cnInactivated after 200 ns;
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TestProcess : process is
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begin
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iLine <= '0' after 0 ns, '1' after 301 ns, '0' after 390 ns,
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'1' after 550 ns, '0' after 600 ns, '1' after 690 ns,
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'0' after 1000 ns;
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ClearEdgeDetected <= '0' after 0 ns, '1' after 430 ns, '0' after 470 ns, '1'
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after 590 ns, '0' after 630 ns, '1' after 810 ns,
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'0' after 830 ns;
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wait;
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end process TestProcess;
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-- Simulation is finished after predefined time.
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SimulationFinished : process
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begin
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wait for simulationTime;
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assert false
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report "This is not a failure: Simulation finished !!!"
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severity failure;
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end process SimulationFinished;
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end architecture Bhv;
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