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-- SDHC-SC-Core

-- Secure Digital High Capacity Self Configuring Core

-- 

-- (C) Copyright 2010, Rainer Kastl

-- All rights reserved.

-- 

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

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--     * Neither the name of the <organization> nor the

--       names of its contributors may be used to endorse or promote products

--       derived from this software without specific prior written permission.

-- 

-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND

-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

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-- 

-- File        : StrobeGen-e.vhdl

-- Owner       : Rainer Kastl

-- Description : 

-- Links       : See EDS at FH Hagenberg

-- 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.Global.all;

entity StrobeGen is

  generic (

    gClkFrequency    : natural := 25E6;

    gStrobeCycleTime : time    := 1 sec);

  port (

    -- Sequential logic inside this unit

    iClk         : in std_ulogic;

    inResetAsync : in std_ulogic := '1';

    iRstSync     : in std_ulogic := '0';

    -- Strobe with the above given cycle time

    oStrobe      : out std_ulogic);

begin

  assert ((1 sec / gClkFrequency) <= gStrobeCycleTime)

    report "Mp: The Clk frequency is to low to generate such a short strobe cycle."

    severity error;

end StrobeGen;