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[/] [sdram_controller/] [trunk/] [sdram_init.vhd] - Blame information for rev 12

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----------------------------------------------------------------------------------
-- Company: OPL Aerospatiale AG
-- Engineer: Owen Lynn <lynn0p@hotmail.com>
-- 
-- Create Date:    17:29:55 08/29/2009 
-- Design Name: 
-- Module Name:    sdram_init - impl 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: This is the FSM that gets the DDR SDRAM chip past init. Otherwise
--  the main FSM would grow pretty unwieldy and unstable.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--  Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
--  Released under the GNU Lesser General Public License, Version 3
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity sdram_init is
        port(
                clk_000 : in std_logic;
                reset   : in std_logic;
 
                clke  : out std_logic;
                cmd   : out std_logic_vector(2 downto 0);
                bank  : out std_logic_vector(1 downto 0);
                addr  : out std_logic_vector(12 downto 0);
                done  : out std_logic
        );
end sdram_init;
 
architecture impl of sdram_init is
        component wait_counter is
                generic(
                        BITS : integer;
                        CLKS : integer
                );
                port(
                         clk : in std_logic;
                         rst : in std_logic;
                        done : out std_logic
                );
        end component;
 
        constant CMD_NOP        : std_logic_vector(2 downto 0)  := "111";
        constant CMD_PRECHARGE  : std_logic_vector(2 downto 0)  := "010";
        constant CMD_AUTO_REFR  : std_logic_vector(2 downto 0)  := "100";
        constant CMD_LOAD_MR    : std_logic_vector(2 downto 0)  := "000";
 
        constant CLKS_200US         : integer := 30000; -- well, it's supposed to be 20000, but i'm fudging
 
        type INIT_STATES is ( STATE_START, STATE_WAIT200US, STATE_CLKE, STATE_PRECHARGE_ALL0, STATE_WAIT_PRECHARGE_ALL0, STATE_LOAD_MRE,
                              STATE_WAIT_MRE, STATE_LOAD_MRN, STATE_WAIT_MRN, STATE_PRECHARGE_ALL1, STATE_WAIT_PRECHARGE_ALL1, STATE_AUTO_REFRESH0,
                                                                 STATE_WAIT_AR_CTR0, STATE_WAIT_AUTO_REFRESH0, STATE_AUTO_REFRESH1, STATE_WAIT_AR_CTR1, STATE_WAIT_AUTO_REFRESH1,
                                                                 STATE_WAIT_200_CLOCKS, STATE_DONE );
 
        signal init_state : INIT_STATES;
 
        signal wait200us_rst : std_logic;
        signal wait200us_done : std_logic;
 
        signal wait_ar_rst : std_logic;
        signal wait_ar_done : std_logic;
 
        signal wait_200clks_rst : std_logic;
        signal wait_200clks_done : std_logic;
 
        signal a058 : std_logic;
        signal a10 : std_logic;
        signal bk0 : std_logic;
 
begin
 
        WAIT200US_CTR: wait_counter
        generic map(
                BITS => 16,
                CLKS => CLKS_200US
        )
        port map(
                clk => clk_000,
                rst => wait200us_rst,
                done => wait200us_done
        );
 
        WAIT_AR_CTR: wait_counter
        generic map(
                BITS => 4,
                CLKS => 11
        )
        port map(
                clk => clk_000,
                rst => wait_ar_rst,
                done => wait_ar_done
        );
 
        WAIT_200CLKS_CTR: wait_counter
        generic map(
                BITS => 8,
                CLKS => 200
        )
        port map(
                clk => clk_000,
                rst => wait_200clks_rst,
                done => wait_200clks_done
        );
 
        -- really optimized output of FSM
        addr(12) <= '0';
        addr(11) <= '0';
        addr(10) <= a10;
        addr(9)  <= '0';
        addr(8)  <= a058;
        addr(7)  <= '0';
        addr(6)  <= '0';
        addr(5)  <= a058;
        addr(4)  <= '0';
        addr(3)  <= '0';
        addr(2)  <= '0';
        addr(1)  <= '0';
        addr(0)  <= a058;
        bank(1) <= '0';
        bank(0) <= bk0;
 
        process (clk_000, reset)
        begin
                if (reset = '1') then
                        init_state <= STATE_START;
                        wait200us_rst <= '1';
                        wait_ar_rst <= '1';
                        wait_200clks_rst <= '1';
                        clke <= '0';
                        cmd <= CMD_NOP;
                        bk0 <= '0';
                        a10 <= '0'; a058 <= '0';
                        done <= '0';
                elsif (rising_edge(clk_000)) then
                        case init_state is
                                when STATE_START =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT200US;
 
                                when STATE_WAIT200US =>
                                        wait200us_rst <= '0';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        if( wait200us_done = '1' ) then
                                                init_state <= STATE_CLKE;
                                        else
                                                init_state <= init_state;
                                        end if;
 
                                when STATE_CLKE =>
                                        clke <= '1';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '1'; a058 <= '0'; -- timing kludge
                                        init_state <= STATE_PRECHARGE_ALL0;
 
                                when STATE_PRECHARGE_ALL0 =>
                                        cmd <= CMD_PRECHARGE;
                                        bk0 <= '0';
                                        a10 <= '1'; a058 <= '0';
                                        init_state <= STATE_WAIT_PRECHARGE_ALL0;
 
                                when STATE_WAIT_PRECHARGE_ALL0 =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_LOAD_MRE;
 
                                when STATE_LOAD_MRE =>
                                        cmd <= CMD_LOAD_MR;
                                        bk0 <= '1';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT_MRE;
 
                                when STATE_WAIT_MRE =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '1'; -- timing kludge
                                        init_state <= STATE_LOAD_MRN;
 
                                when STATE_LOAD_MRN =>
                                        cmd <= CMD_LOAD_MR;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '1';
                                        init_state <= STATE_WAIT_MRN;
 
                                when STATE_WAIT_MRN =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '1'; -- timing kludge
                                        init_state <= STATE_PRECHARGE_ALL1;
 
                                when STATE_PRECHARGE_ALL1 =>
                                        cmd <= CMD_PRECHARGE;
                                        bk0 <= '0';
                                        a10 <= '1'; a058 <= '0';
                                        init_state <= STATE_WAIT_PRECHARGE_ALL1;
 
                                when STATE_WAIT_PRECHARGE_ALL1 =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_AUTO_REFRESH0;
 
                                when STATE_AUTO_REFRESH0 =>
                                        wait_ar_rst <= '1';
                                        cmd <= CMD_AUTO_REFR;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT_AR_CTR0;
 
                                when STATE_WAIT_AR_CTR0 =>
                                        wait_ar_rst <= '0';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT_AUTO_REFRESH0;
 
                                when STATE_WAIT_AUTO_REFRESH0 =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        if (wait_ar_done = '1') then
                                                init_state <= STATE_AUTO_REFRESH1;
                                        else
                                                init_state <= init_state;
                                        end if;
 
                                when STATE_AUTO_REFRESH1 =>
                                        wait_ar_rst <= '1';
                                        cmd <= CMD_AUTO_REFR;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT_AR_CTR1;
 
                                when STATE_WAIT_AR_CTR1 =>
                                        wait_ar_rst <= '0';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        init_state <= STATE_WAIT_AUTO_REFRESH1;
 
                                when STATE_WAIT_AUTO_REFRESH1 =>
                                        wait_200clks_rst <= '1';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        if (wait_ar_done = '1') then
                                                init_state <= STATE_WAIT_200_CLOCKS;
                                        else
                                                init_state <= init_state;
                                        end if;
 
                                when STATE_WAIT_200_CLOCKS =>
                                        wait_200clks_rst <= '0';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                                        if (wait_200clks_done = '1') then
                                                init_state <= STATE_DONE;
                                        else
                                                init_state <= init_state;
                                        end if;
 
                                 when STATE_DONE =>
                                        done <= '1';
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
 
                                when others =>
                                        cmd <= CMD_NOP;
                                        bk0 <= '0';
                                        a10 <= '0'; a058 <= '0';
                        end case;
                end if;
        end process;
end impl;
 

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Subversion Repositories sdram_controller

[/] [sdram_controller/] [trunk/] [sdram_init.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	lynn0p	`----------------------------------------------------------------------------------`
2			`-- Company: OPL Aerospatiale AG`
3			`-- Engineer: Owen Lynn <lynn0p@hotmail.com>`
4			`--`
5			`-- Create Date: 17:29:55 08/29/2009`
6			`-- Design Name:`
7			`-- Module Name: sdram_init - impl`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description: This is the FSM that gets the DDR SDRAM chip past init. Otherwise`
12			`-- the main FSM would grow pretty unwieldy and unstable.`
13			`--`
14			`-- Dependencies:`
15			`--`
16			`-- Revision:`
17			`-- Revision 0.01 - File Created`
18			`-- Additional Comments:`
19			`-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>`
20			`-- Released under the GNU Lesser General Public License, Version 3`
21			`--`
22			`----------------------------------------------------------------------------------`
23			`library IEEE;`
24			`use IEEE.STD_LOGIC_1164.ALL;`
25			`use IEEE.STD_LOGIC_ARITH.ALL;`
26			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity sdram_init is`
34			`port(`
35			`clk_000 : in std_logic;`
36			`reset : in std_logic;`
37
38			`clke : out std_logic;`
39			`cmd : out std_logic_vector(2 downto 0);`
40			`bank : out std_logic_vector(1 downto 0);`
41			`addr : out std_logic_vector(12 downto 0);`
42			`done : out std_logic`
43			`);`
44			`end sdram_init;`
45
46			`architecture impl of sdram_init is`
47			`component wait_counter is`
48			`generic(`
49			`BITS : integer;`
50			`CLKS : integer`
51			`);`
52			`port(`
53			`clk : in std_logic;`
54			`rst : in std_logic;`
55			`done : out std_logic`
56			`);`
57			`end component;`
58
59			`constant CMD_NOP : std_logic_vector(2 downto 0) := "111";`
60			`constant CMD_PRECHARGE : std_logic_vector(2 downto 0) := "010";`
61			`constant CMD_AUTO_REFR : std_logic_vector(2 downto 0) := "100";`
62			`constant CMD_LOAD_MR : std_logic_vector(2 downto 0) := "000";`
63
64	12	lynn0p	`constant CLKS_200US : integer := 30000; -- well, it's supposed to be 20000, but i'm fudging`
65	2	lynn0p
66			`type INIT_STATES is ( STATE_START, STATE_WAIT200US, STATE_CLKE, STATE_PRECHARGE_ALL0, STATE_WAIT_PRECHARGE_ALL0, STATE_LOAD_MRE,`
67			`STATE_WAIT_MRE, STATE_LOAD_MRN, STATE_WAIT_MRN, STATE_PRECHARGE_ALL1, STATE_WAIT_PRECHARGE_ALL1, STATE_AUTO_REFRESH0,`
68			`STATE_WAIT_AR_CTR0, STATE_WAIT_AUTO_REFRESH0, STATE_AUTO_REFRESH1, STATE_WAIT_AR_CTR1, STATE_WAIT_AUTO_REFRESH1,`
69			`STATE_WAIT_200_CLOCKS, STATE_DONE );`
70
71			`signal init_state : INIT_STATES;`
72
73			`signal wait200us_rst : std_logic;`
74			`signal wait200us_done : std_logic;`
75
76			`signal wait_ar_rst : std_logic;`
77			`signal wait_ar_done : std_logic;`
78
79			`signal wait_200clks_rst : std_logic;`
80			`signal wait_200clks_done : std_logic;`
81
82			`signal a058 : std_logic;`
83			`signal a10 : std_logic;`
84			`signal bk0 : std_logic;`
85
86			`begin`
87
88			`WAIT200US_CTR: wait_counter`
89			`generic map(`
90			`BITS => 16,`
91			`CLKS => CLKS_200US`
92			`)`
93			`port map(`
94			`clk => clk_000,`
95			`rst => wait200us_rst,`
96			`done => wait200us_done`
97			`);`
98
99			`WAIT_AR_CTR: wait_counter`
100			`generic map(`
101			`BITS => 4,`
102			`CLKS => 11`
103			`)`
104			`port map(`
105			`clk => clk_000,`
106			`rst => wait_ar_rst,`
107			`done => wait_ar_done`
108			`);`
109
110			`WAIT_200CLKS_CTR: wait_counter`
111			`generic map(`
112			`BITS => 8,`
113			`CLKS => 200`
114			`)`
115			`port map(`
116			`clk => clk_000,`
117			`rst => wait_200clks_rst,`
118			`done => wait_200clks_done`
119			`);`
120
121			`-- really optimized output of FSM`
122			`addr(12) <= '0';`
123			`addr(11) <= '0';`
124			`addr(10) <= a10;`
125			`addr(9) <= '0';`
126			`addr(8) <= a058;`
127			`addr(7) <= '0';`
128			`addr(6) <= '0';`
129			`addr(5) <= a058;`
130			`addr(4) <= '0';`
131			`addr(3) <= '0';`
132			`addr(2) <= '0';`
133			`addr(1) <= '0';`
134			`addr(0) <= a058;`
135			`bank(1) <= '0';`
136			`bank(0) <= bk0;`
137
138			`process (clk_000, reset)`
139			`begin`
140			`if (reset = '1') then`
141			`init_state <= STATE_START;`
142			`wait200us_rst <= '1';`
143			`wait_ar_rst <= '1';`
144			`wait_200clks_rst <= '1';`
145			`clke <= '0';`
146			`cmd <= CMD_NOP;`
147			`bk0 <= '0';`
148			`a10 <= '0'; a058 <= '0';`
149			`done <= '0';`
150			`elsif (rising_edge(clk_000)) then`
151			`case init_state is`
152			`when STATE_START =>`
153			`cmd <= CMD_NOP;`
154			`bk0 <= '0';`
155			`a10 <= '0'; a058 <= '0';`
156			`init_state <= STATE_WAIT200US;`
157
158			`when STATE_WAIT200US =>`
159			`wait200us_rst <= '0';`
160			`cmd <= CMD_NOP;`
161			`bk0 <= '0';`
162			`a10 <= '0'; a058 <= '0';`
163			`if( wait200us_done = '1' ) then`
164			`init_state <= STATE_CLKE;`
165			`else`
166			`init_state <= init_state;`
167			`end if;`
168
169			`when STATE_CLKE =>`
170			`clke <= '1';`
171			`cmd <= CMD_NOP;`
172			`bk0 <= '0';`
173			`a10 <= '1'; a058 <= '0'; -- timing kludge`
174			`init_state <= STATE_PRECHARGE_ALL0;`
175
176			`when STATE_PRECHARGE_ALL0 =>`
177			`cmd <= CMD_PRECHARGE;`
178			`bk0 <= '0';`
179			`a10 <= '1'; a058 <= '0';`
180			`init_state <= STATE_WAIT_PRECHARGE_ALL0;`
181
182			`when STATE_WAIT_PRECHARGE_ALL0 =>`
183			`cmd <= CMD_NOP;`
184			`bk0 <= '0';`
185			`a10 <= '0'; a058 <= '0';`
186			`init_state <= STATE_LOAD_MRE;`
187
188			`when STATE_LOAD_MRE =>`
189			`cmd <= CMD_LOAD_MR;`
190			`bk0 <= '1';`
191			`a10 <= '0'; a058 <= '0';`
192			`init_state <= STATE_WAIT_MRE;`
193
194			`when STATE_WAIT_MRE =>`
195			`cmd <= CMD_NOP;`
196			`bk0 <= '0';`
197			`a10 <= '0'; a058 <= '1'; -- timing kludge`
198			`init_state <= STATE_LOAD_MRN;`
199
200			`when STATE_LOAD_MRN =>`
201			`cmd <= CMD_LOAD_MR;`
202			`bk0 <= '0';`
203			`a10 <= '0'; a058 <= '1';`
204			`init_state <= STATE_WAIT_MRN;`
205
206			`when STATE_WAIT_MRN =>`
207			`cmd <= CMD_NOP;`
208			`bk0 <= '0';`
209			`a10 <= '0'; a058 <= '1'; -- timing kludge`
210			`init_state <= STATE_PRECHARGE_ALL1;`
211
212			`when STATE_PRECHARGE_ALL1 =>`
213			`cmd <= CMD_PRECHARGE;`
214			`bk0 <= '0';`
215			`a10 <= '1'; a058 <= '0';`
216			`init_state <= STATE_WAIT_PRECHARGE_ALL1;`
217
218			`when STATE_WAIT_PRECHARGE_ALL1 =>`
219			`cmd <= CMD_NOP;`
220			`bk0 <= '0';`
221			`a10 <= '0'; a058 <= '0';`
222			`init_state <= STATE_AUTO_REFRESH0;`
223
224			`when STATE_AUTO_REFRESH0 =>`
225			`wait_ar_rst <= '1';`
226			`cmd <= CMD_AUTO_REFR;`
227			`bk0 <= '0';`
228			`a10 <= '0'; a058 <= '0';`
229			`init_state <= STATE_WAIT_AR_CTR0;`
230
231			`when STATE_WAIT_AR_CTR0 =>`
232			`wait_ar_rst <= '0';`
233			`cmd <= CMD_NOP;`
234			`bk0 <= '0';`
235			`a10 <= '0'; a058 <= '0';`
236			`init_state <= STATE_WAIT_AUTO_REFRESH0;`
237
238			`when STATE_WAIT_AUTO_REFRESH0 =>`
239			`cmd <= CMD_NOP;`
240			`bk0 <= '0';`
241			`a10 <= '0'; a058 <= '0';`
242			`if (wait_ar_done = '1') then`
243			`init_state <= STATE_AUTO_REFRESH1;`
244			`else`
245			`init_state <= init_state;`
246			`end if;`
247
248			`when STATE_AUTO_REFRESH1 =>`
249			`wait_ar_rst <= '1';`
250			`cmd <= CMD_AUTO_REFR;`
251			`bk0 <= '0';`
252			`a10 <= '0'; a058 <= '0';`
253			`init_state <= STATE_WAIT_AR_CTR1;`
254
255			`when STATE_WAIT_AR_CTR1 =>`
256			`wait_ar_rst <= '0';`
257			`cmd <= CMD_NOP;`
258			`bk0 <= '0';`
259			`a10 <= '0'; a058 <= '0';`
260			`init_state <= STATE_WAIT_AUTO_REFRESH1;`
261
262			`when STATE_WAIT_AUTO_REFRESH1 =>`
263			`wait_200clks_rst <= '1';`
264			`cmd <= CMD_NOP;`
265			`bk0 <= '0';`
266			`a10 <= '0'; a058 <= '0';`
267			`if (wait_ar_done = '1') then`
268			`init_state <= STATE_WAIT_200_CLOCKS;`
269			`else`
270			`init_state <= init_state;`
271			`end if;`
272
273			`when STATE_WAIT_200_CLOCKS =>`
274			`wait_200clks_rst <= '0';`
275			`cmd <= CMD_NOP;`
276			`bk0 <= '0';`
277			`a10 <= '0'; a058 <= '0';`
278			`if (wait_200clks_done = '1') then`
279			`init_state <= STATE_DONE;`
280			`else`
281			`init_state <= init_state;`
282			`end if;`
283
284			`when STATE_DONE =>`
285			`done <= '1';`
286			`cmd <= CMD_NOP;`
287			`bk0 <= '0';`
288			`a10 <= '0'; a058 <= '0';`
289
290			`when others =>`
291			`cmd <= CMD_NOP;`
292			`bk0 <= '0';`
293			`a10 <= '0'; a058 <= '0';`
294			`end case;`
295			`end if;`
296			`end process;`
297			`end impl;`
298