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[/] [sgmii/] [trunk/] [build/] [mMdioMstr.v] - Blame information for rev 25

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/*
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
 
        This file is part of SGMII-IP-Core.
    SGMII-IP-Core is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    SGMII-IP-Core is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with SGMII-IP-Core.  If not, see <http://www.gnu.org/licenses/>.
 
File            :
Description     :
Remarks         :
Revision        :
        Date    Author          Description
02/09/12        Jefflieu
*/
 
module mMdioMstr(
        input i_Clk,
        input i_ARst_L,
        //Wishbone interface
        input i_Cyc,i_Stb,i_WEn,
        output reg o_Ack,
        input [1:0] i2_Addr,
        input [31:0] i32_WrData,
        output reg [31:0] o32_RdData,
 
        //MDIO Interface
        output  o_Mdc,
        inout   io_Mdio);
 
 
        reg [15:0] r16_WrData;
        reg [15:0] r16_RdData;
        reg [15:0] r16_Cmd;
        reg [4:0] r5_BitCnt;
        reg [3:0] rv_ClkDiv;
        reg r_Mdc;
        reg r_Mdo;
        reg r_Frame;
        wire w_NewCmd;
        reg r_NewCmd;
        wire w_ReadFrame;
 
        //Bus Interface
        always@(posedge i_Clk or negedge i_ARst_L)
        if(~i_ARst_L) begin
                r16_Cmd <= 16'h0;
                r16_WrData <= 16'h0;
                r_NewCmd <= 1'b0;
        end else begin
                if(i_Cyc & i_Stb & i_WEn)
                        case(i2_Addr)
                        2'b00:  r16_Cmd <= i32_WrData[15:0];
                        2'b01:  r16_WrData <= i32_WrData[15:0];
                        endcase
                case(i2_Addr)
                        2'b00:  o32_RdData <= {16'h0,r16_Cmd};
                        2'b01:  o32_RdData <= {16'h0,r16_WrData};
                        2'b10:  o32_RdData <= {16'h0,r16_RdData};
                        2'b11:  o32_RdData <= {16'h0,r16_RdData};
                endcase
 
                o_Ack <= (~o_Ack) & i_Cyc & i_Stb;
                if(r_Frame)//Reset
                        r_NewCmd <= 1'b0;
                else if(w_NewCmd)       //Set
                        r_NewCmd <= 1'b1;
        end
 
        assign w_NewCmd = i_Cyc & i_Stb & i_WEn & o_Ack & (i2_Addr==2'b00);
        assign w_ReadFrame = (r16_Cmd[13:12]==2'b10)?1'b1:1'b0;
 
        assign o_Mdc = r_Mdc?1'bz:1'b0; //OpenDrain
        assign io_Mdio = (r_Mdo|(~r_Frame))?1'bz:1'b0;
        always@(posedge i_Clk or negedge i_ARst_L)
        if(~i_ARst_L)
                begin
                        rv_ClkDiv <= 4'b0;
                        r_Mdc<=1'b0;
                end
        else begin
                        rv_ClkDiv <= rv_ClkDiv+4'b1;
                        if(&rv_ClkDiv) r_Mdc<=~r_Mdc;
                end
 
 
        always@(posedge i_Clk or negedge i_ARst_L)
        if(~i_ARst_L)
                begin
                        r_Frame <= 1'b0;
                        r5_BitCnt <= 5'b11111;
                        r_Mdo <= 1'b1;
                        r16_RdData <= 16'h0;
                end
        else
                begin
                        if((&rv_ClkDiv) && ~r_Mdc)
                        begin //At the rising edge of MDC clock
                                if(r_NewCmd)            //If New Command Available Start Frame Half a clock earlier by 
                                        r_Frame<=1'b1;
                                else
                                if(~(|r5_BitCnt))
                                        r_Frame<=1'b0;
                        end
 
                        if(~r_Frame) r_Mdo <= 1'b1;
                        else
                                if(r_Frame && (&rv_ClkDiv) && r_Mdc)  //AT the Falling edge and 
                                begin
                                r_Mdo <= r5_BitCnt[4]?r16_Cmd[r5_BitCnt[3:0]]:(w_ReadFrame?1'b1:r16_WrData[r5_BitCnt[3:0]]);
                                end
 
                        if(~r_Frame)    //Load Bit Count
                                r5_BitCnt <= 5'b11111;
                        else if(r_Frame && (&rv_ClkDiv) && ~r_Mdc)      //At the rising edge count down
                                r5_BitCnt<=r5_BitCnt-5'b1;
 
                        if((r_Frame && (&rv_ClkDiv) && ~r_Mdc))
                                r16_RdData[r5_BitCnt[3:0]]<=io_Mdio;
                end
 
 
endmodule

Line No.	Rev	Author	Line
1	25	jefflieu	`/*`
2			`Copyright � 2012 JeffLieu-lieumychuong@gmail.com`
3
4			`This file is part of SGMII-IP-Core.`
5			`SGMII-IP-Core is free software: you can redistribute it and/or modify`
6			`it under the terms of the GNU General Public License as published by`
7			`the Free Software Foundation, either version 3 of the License, or`
8			`(at your option) any later version.`
9
10			`SGMII-IP-Core is distributed in the hope that it will be useful,`
11			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`GNU General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.`
17
18			`File :`
19			`Description :`
20			`Remarks :`
21			`Revision :`
22			`Date Author Description`
23			`02/09/12 Jefflieu`
24			`*/`
25
26			`module mMdioMstr(`
27			`input i_Clk,`
28			`input i_ARst_L,`
29			`//Wishbone interface`
30			`input i_Cyc,i_Stb,i_WEn,`
31			`output reg o_Ack,`
32			`input [1:0] i2_Addr,`
33			`input [31:0] i32_WrData,`
34			`output reg [31:0] o32_RdData,`
35
36			`//MDIO Interface`
37			`output o_Mdc,`
38			`inout io_Mdio);`
39
40
41			`reg [15:0] r16_WrData;`
42			`reg [15:0] r16_RdData;`
43			`reg [15:0] r16_Cmd;`
44			`reg [4:0] r5_BitCnt;`
45			`reg [3:0] rv_ClkDiv;`
46			`reg r_Mdc;`
47			`reg r_Mdo;`
48			`reg r_Frame;`
49			`wire w_NewCmd;`
50			`reg r_NewCmd;`
51			`wire w_ReadFrame;`
52
53			`//Bus Interface`
54			`always@(posedge i_Clk or negedge i_ARst_L)`
55			`if(~i_ARst_L) begin`
56			`r16_Cmd <= 16'h0;`
57			`r16_WrData <= 16'h0;`
58			`r_NewCmd <= 1'b0;`
59			`end else begin`
60			`if(i_Cyc & i_Stb & i_WEn)`
61			`case(i2_Addr)`
62			`2'b00: r16_Cmd <= i32_WrData[15:0];`
63			`2'b01: r16_WrData <= i32_WrData[15:0];`
64			`endcase`
65			`case(i2_Addr)`
66			`2'b00: o32_RdData <= {16'h0,r16_Cmd};`
67			`2'b01: o32_RdData <= {16'h0,r16_WrData};`
68			`2'b10: o32_RdData <= {16'h0,r16_RdData};`
69			`2'b11: o32_RdData <= {16'h0,r16_RdData};`
70			`endcase`
71
72			`o_Ack <= (~o_Ack) & i_Cyc & i_Stb;`
73			`if(r_Frame)//Reset`
74			`r_NewCmd <= 1'b0;`
75			`else if(w_NewCmd) //Set`
76			`r_NewCmd <= 1'b1;`
77			`end`
78
79			`assign w_NewCmd = i_Cyc & i_Stb & i_WEn & o_Ack & (i2_Addr==2'b00);`
80			`assign w_ReadFrame = (r16_Cmd[13:12]==2'b10)?1'b1:1'b0;`
81
82			`assign o_Mdc = r_Mdc?1'bz:1'b0; //OpenDrain`
83			`assign io_Mdio = (r_Mdo\|(~r_Frame))?1'bz:1'b0;`
84			`always@(posedge i_Clk or negedge i_ARst_L)`
85			`if(~i_ARst_L)`
86			`begin`
87			`rv_ClkDiv <= 4'b0;`
88			`r_Mdc<=1'b0;`
89			`end`
90			`else begin`
91			`rv_ClkDiv <= rv_ClkDiv+4'b1;`
92			`if(&rv_ClkDiv) r_Mdc<=~r_Mdc;`
93			`end`
94
95
96			`always@(posedge i_Clk or negedge i_ARst_L)`
97			`if(~i_ARst_L)`
98			`begin`
99			`r_Frame <= 1'b0;`
100			`r5_BitCnt <= 5'b11111;`
101			`r_Mdo <= 1'b1;`
102			`r16_RdData <= 16'h0;`
103			`end`
104			`else`
105			`begin`
106			`if((&rv_ClkDiv) && ~r_Mdc)`
107			`begin //At the rising edge of MDC clock`
108			`if(r_NewCmd) //If New Command Available Start Frame Half a clock earlier by`
109			`r_Frame<=1'b1;`
110			`else`
111			`if(~(\|r5_BitCnt))`
112			`r_Frame<=1'b0;`
113			`end`
114
115			`if(~r_Frame) r_Mdo <= 1'b1;`
116			`else`
117			`if(r_Frame && (&rv_ClkDiv) && r_Mdc) //AT the Falling edge and`
118			`begin`
119			`r_Mdo <= r5_BitCnt[4]?r16_Cmd[r5_BitCnt[3:0]]:(w_ReadFrame?1'b1:r16_WrData[r5_BitCnt[3:0]]);`
120			`end`
121
122			`if(~r_Frame) //Load Bit Count`
123			`r5_BitCnt <= 5'b11111;`
124			`else if(r_Frame && (&rv_ClkDiv) && ~r_Mdc) //At the rising edge count down`
125			`r5_BitCnt<=r5_BitCnt-5'b1;`
126
127			`if((r_Frame && (&rv_ClkDiv) && ~r_Mdc))`
128			`r16_RdData[r5_BitCnt[3:0]]<=io_Mdio;`
129			`end`
130
131
132			`endmodule`

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[/] [sgmii/] [trunk/] [build/] [mMdioMstr.v] - Blame information for rev 25