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[/] [sgmii/] [trunk/] [build/] [mPacketGenerator.sv] - Blame information for rev 25

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module pkt_gen32 (
clk,
rst,
 
control,
status,
config_1,
config_2,
i32_Payload1,
i32_Payload2,
i32_Payload3,
i32_Payload4,
 
pkt_rdy,
pkt_dv,
pkt_sop,
pkt_eop,
pkt_data,
pkt_BE,
pkt_rd,
pkt_len_rdy,
pkt_len,
pkt_len_rd);
 
input clk;
input rst;
input   [15:00] control;
output reg [31:00]      status;
input   [31:00] config_1;
input   [31:00] config_2;
input   [31:00] i32_Payload1;
input   [31:00] i32_Payload2;
input   [31:00] i32_Payload3;
input   [31:00] i32_Payload4;
 
output  pkt_rdy;
output  pkt_dv;
output  pkt_sop;
output  pkt_eop;
output  [31:00] pkt_data;
input   pkt_rd;
output  [1:0] pkt_BE;
 
input pkt_len_rd;
output pkt_len_rdy;
output [15:00] pkt_len;
 
typedef enum  {IDLE, RDY, END, WAIT} state_type;
 
parameter MAC_SRC       = 48'h00_1F_02_03_AA_BB;
parameter MAC_DST       = 48'h00_27_0E_1A_46_03;
parameter IP_SRC        = 32'hC0_A8_00_01;
parameter IP_DST        = 32'hC0_A8_01_B0;
 
reg [15:0] polynomial[16];
 
state_type st;
wire enable;
wire sw_rst;
wire [31:0] src_ip;
wire [31:0] dst_ip;
reg [31:00] mux_data;
reg [31:00] random_data;
reg [15:00] word_cnt;
reg [15:00] byte_cnt;
reg [31:00] timer;
reg [15:00] i_pkt_length;
reg [15:00] ip_rand;
 
wire [31:00] shift_random_data;
 
wire sop;
wire eop;
wire dv;
wire time_exp;
 
reg pkt_rd_d;
reg one_sec_clk;
reg [31:00] one_sec_tmr;
localparam ONE_SEC_CYCLES = 124_999_999;
reg [31:00] datarate;
reg tmr_en;
 
assign enable = control[0];
assign sw_rst = control[1];
 
        always@(posedge clk or posedge rst)
        begin
        if(rst) begin
                one_sec_tmr <= 0;
                one_sec_clk <= 0;
                datarate <= 0;
                end
        else begin
                if(one_sec_tmr==ONE_SEC_CYCLES) begin
                        one_sec_tmr <= 0;
                        one_sec_clk <= 1'b1;
                        end
                else
                        begin
                        one_sec_tmr <= one_sec_tmr+1;
                        one_sec_clk <= 1'b0;
                        end
                if(one_sec_clk) begin
                                datarate <= 0;
                                status <= datarate; end
                else if(dv)
                                datarate <= datarate+1;
                end
        end
 
        always@(posedge clk or posedge rst)
        if(rst)
                st <= IDLE;
        else
                begin
                        if((sw_rst) || (~enable))
                                st<= IDLE;
                        else
                                case(st)
                                        IDLE: st <= RDY;
                                        RDY : if(eop) st<= END;
                                        END : st <= WAIT;
                                        WAIT: if(time_exp) st <= IDLE;
                                endcase
                end
 
        assign pkt_rdy = (st==RDY);
        assign pkt_len_rdy = enable;
        assign pkt_len = i_pkt_length;
        assign eop = (byte_cnt<=4 && byte_cnt>0 && dv ==1'b1);
        assign sop = (byte_cnt == i_pkt_length && dv == 1'b1);
        assign pkt_eop = eop;
        assign pkt_dv  = dv;
        assign pkt_sop = sop;
        assign dv = pkt_rd_d && (st==RDY);
        assign pkt_BE = byte_cnt[1:0];
 
        always@(posedge clk)
        begin
                if(st==IDLE||st==END) begin
                        word_cnt <= 0;
                        byte_cnt <= config_1[15:0];
                        i_pkt_length <= config_1[15:0];
                        end
                else
                if(dv) begin
                        word_cnt <= word_cnt+1;
                        if(byte_cnt>4)
                                byte_cnt <= byte_cnt-4;
                        else
                                byte_cnt <= 0;
                end
 
                if(st==IDLE)
                    tmr_en <= 1'b0;
                else if(sop)
                    tmr_en <= 1'b1;
 
                if(st==IDLE)
                                timer <= config_2;
                else if(tmr_en && (timer!=0))		timer <= timer - 1;
 
                if(st==RDY)
                        pkt_rd_d <= pkt_rd; else
                        pkt_rd_d <= 1'b0;
        end
 
        /*always@(*)
        begin
    case(word_cnt)
                0: mux_data <= MAC_DST[47:16];
                1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};
                2: mux_data <= MAC_SRC[31:00];
                3: mux_data <= {config_1[15:0],16'h0000};//{16'h0800,16'h0000};
                4: mux_data <= 32'h00;//{config_1[15:0],16'h0000};
                5: mux_data <= {16'h0000,16'h0000};
                6: mux_data <= {16'h0000,src_ip[31:16]};
                7: mux_data <= {src_ip[15:0],IP_DST[31:16]};
                8: mux_data <= {IP_DST[15:0],16'h0000};
                default: mux_data <= {byte_cnt,byte_cnt};//random_data;
                endcase
        end*/
        always@(*)
        begin
    case(word_cnt)
                0: mux_data <= MAC_DST[47:16];
                1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};
                2: mux_data <= MAC_SRC[31:00];
                3: mux_data <= {(config_1[15:0]-16'd14),16'h0000};//{16'h0800,16'h0000};
                4: mux_data <= i32_Payload1;
                5: mux_data <= i32_Payload2;
                6: mux_data <= i32_Payload3;
                7: mux_data <= i32_Payload4;
                default: mux_data <= {32'h0102_0304};//random_data;
                endcase
        end
 
 
        assign time_exp = (timer==0);
        assign pkt_data = mux_data;
 
        //random data generation
        assign shift_random_data = {random_data[30:0],^(random_data&32'h1034_BCFE)};
        always@(posedge clk)
        begin
                if(word_cnt==3 && dv==1'b1)
                        random_data <= MAC_DST[31:00];
                else
                        if(dv) begin
                                random_data <= random_data[31]?shift_random_data:(~shift_random_data);
        end
        end
 
        always@(posedge clk or posedge rst)
        begin
                if(rst) begin
                  ip_rand <= 16'h1;
                  //For this polynomial, look for maxim-ic.com/app-notes/index.mvp/id/1743
                  polynomial[00] = 16'h0;
                  polynomial[01] = 16'h0;
                  polynomial[02] = 16'h0005;
                  polynomial[03] = 16'h0009;
                  polynomial[04] = 16'h0012;
                  polynomial[05] = 16'h0021;
                  polynomial[06] = 16'h0041;
                  polynomial[07] = 16'h008E;
                  polynomial[08] = 16'h0108;
                  polynomial[09] = 16'h0204;
                  polynomial[10] = 16'h0402;
                  polynomial[11] = 16'h0829;
                  polynomial[12] = 16'h100D;
                  polynomial[13] = 16'h2015;
                  polynomial[14] = 16'h4001;
                  polynomial[15] = 16'h8016;
                        end
                else
                        begin
                                if(eop & dv)            begin
                                        ip_rand = {ip_rand[15:0],^(ip_rand&(polynomial[config_1[19:16]]))};
                                  ip_rand[(config_1[19:16]+1)] = 1'b0;
                                  //synthesis_off
                                  $display("IPRAND = %d",ip_rand);
                                  //synthesis_on
                                end
                        end
        end
 
        assign src_ip = {IP_SRC[31:16],ip_rand};
 
        //synthesis_off
        /*
        always@(posedge clk or posedge rst)
        begin
          integer found[];
          integer i;
          integer cnt;
                if(rst) begin
                  cnt = 0;
                  for(i=0;i<5000;i++)
                  begin
                    found[i]=0;
            end
                end
                else
                        begin
                        if(sop & dv)            begin
                                        if(found[ip_rand]==0) begin
                                           cnt++;
                                           found[ip_rand]=1;
                                           $display("Total Streams %d",cnt);
                                          end
                                end
                        end
        end*/
 
        //synthesis_on
 
endmodule

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [mPacketGenerator.sv] - Blame information for rev 25

Line No.	Rev	Author	Line
1	25	jefflieu	`module pkt_gen32 (`
2			`clk,`
3			`rst,`
4
5			`control,`
6			`status,`
7			`config_1,`
8			`config_2,`
9			`i32_Payload1,`
10			`i32_Payload2,`
11			`i32_Payload3,`
12			`i32_Payload4,`
13
14			`pkt_rdy,`
15			`pkt_dv,`
16			`pkt_sop,`
17			`pkt_eop,`
18			`pkt_data,`
19			`pkt_BE,`
20			`pkt_rd,`
21			`pkt_len_rdy,`
22			`pkt_len,`
23			`pkt_len_rd);`
24
25			`input clk;`
26			`input rst;`
27			`input [15:00] control;`
28			`output reg [31:00] status;`
29			`input [31:00] config_1;`
30			`input [31:00] config_2;`
31			`input [31:00] i32_Payload1;`
32			`input [31:00] i32_Payload2;`
33			`input [31:00] i32_Payload3;`
34			`input [31:00] i32_Payload4;`
35
36			`output pkt_rdy;`
37			`output pkt_dv;`
38			`output pkt_sop;`
39			`output pkt_eop;`
40			`output [31:00] pkt_data;`
41			`input pkt_rd;`
42			`output [1:0] pkt_BE;`
43
44			`input pkt_len_rd;`
45			`output pkt_len_rdy;`
46			`output [15:00] pkt_len;`
47
48			`typedef enum {IDLE, RDY, END, WAIT} state_type;`
49
50			`parameter MAC_SRC = 48'h00_1F_02_03_AA_BB;`
51			`parameter MAC_DST = 48'h00_27_0E_1A_46_03;`
52			`parameter IP_SRC = 32'hC0_A8_00_01;`
53			`parameter IP_DST = 32'hC0_A8_01_B0;`
54
55			`reg [15:0] polynomial[16];`
56
57			`state_type st;`
58			`wire enable;`
59			`wire sw_rst;`
60			`wire [31:0] src_ip;`
61			`wire [31:0] dst_ip;`
62			`reg [31:00] mux_data;`
63			`reg [31:00] random_data;`
64			`reg [15:00] word_cnt;`
65			`reg [15:00] byte_cnt;`
66			`reg [31:00] timer;`
67			`reg [15:00] i_pkt_length;`
68			`reg [15:00] ip_rand;`
69
70			`wire [31:00] shift_random_data;`
71
72			`wire sop;`
73			`wire eop;`
74			`wire dv;`
75			`wire time_exp;`
76
77			`reg pkt_rd_d;`
78			`reg one_sec_clk;`
79			`reg [31:00] one_sec_tmr;`
80			`localparam ONE_SEC_CYCLES = 124_999_999;`
81			`reg [31:00] datarate;`
82			`reg tmr_en;`
83
84			`assign enable = control[0];`
85			`assign sw_rst = control[1];`
86
87			`always@(posedge clk or posedge rst)`
88			`begin`
89			`if(rst) begin`
90			`one_sec_tmr <= 0;`
91			`one_sec_clk <= 0;`
92			`datarate <= 0;`
93			`end`
94			`else begin`
95			`if(one_sec_tmr==ONE_SEC_CYCLES) begin`
96			`one_sec_tmr <= 0;`
97			`one_sec_clk <= 1'b1;`
98			`end`
99			`else`
100			`begin`
101			`one_sec_tmr <= one_sec_tmr+1;`
102			`one_sec_clk <= 1'b0;`
103			`end`
104			`if(one_sec_clk) begin`
105			`datarate <= 0;`
106			`status <= datarate; end`
107			`else if(dv)`
108			`datarate <= datarate+1;`
109			`end`
110			`end`
111
112			`always@(posedge clk or posedge rst)`
113			`if(rst)`
114			`st <= IDLE;`
115			`else`
116			`begin`
117			`if((sw_rst) \|\| (~enable))`
118			`st<= IDLE;`
119			`else`
120			`case(st)`
121			`IDLE: st <= RDY;`
122			`RDY : if(eop) st<= END;`
123			`END : st <= WAIT;`
124			`WAIT: if(time_exp) st <= IDLE;`
125			`endcase`
126			`end`
127
128			`assign pkt_rdy = (st==RDY);`
129			`assign pkt_len_rdy = enable;`
130			`assign pkt_len = i_pkt_length;`
131			`assign eop = (byte_cnt<=4 && byte_cnt>0 && dv ==1'b1);`
132			`assign sop = (byte_cnt == i_pkt_length && dv == 1'b1);`
133			`assign pkt_eop = eop;`
134			`assign pkt_dv = dv;`
135			`assign pkt_sop = sop;`
136			`assign dv = pkt_rd_d && (st==RDY);`
137			`assign pkt_BE = byte_cnt[1:0];`
138
139			`always@(posedge clk)`
140			`begin`
141			`if(st==IDLE\|\|st==END) begin`
142			`word_cnt <= 0;`
143			`byte_cnt <= config_1[15:0];`
144			`i_pkt_length <= config_1[15:0];`
145			`end`
146			`else`
147			`if(dv) begin`
148			`word_cnt <= word_cnt+1;`
149			`if(byte_cnt>4)`
150			`byte_cnt <= byte_cnt-4;`
151			`else`
152			`byte_cnt <= 0;`
153			`end`
154
155			`if(st==IDLE)`
156			`tmr_en <= 1'b0;`
157			`else if(sop)`
158			`tmr_en <= 1'b1;`
159
160			`if(st==IDLE)`
161			`timer <= config_2;`
162			`else if(tmr_en && (timer!=0)) timer <= timer - 1;`
163
164			`if(st==RDY)`
165			`pkt_rd_d <= pkt_rd; else`
166			`pkt_rd_d <= 1'b0;`
167			`end`
168
169			`/always@()`
170			`begin`
171			`case(word_cnt)`
172			`0: mux_data <= MAC_DST[47:16];`
173			`1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};`
174			`2: mux_data <= MAC_SRC[31:00];`
175			`3: mux_data <= {config_1[15:0],16'h0000};//{16'h0800,16'h0000};`
176			`4: mux_data <= 32'h00;//{config_1[15:0],16'h0000};`
177			`5: mux_data <= {16'h0000,16'h0000};`
178			`6: mux_data <= {16'h0000,src_ip[31:16]};`
179			`7: mux_data <= {src_ip[15:0],IP_DST[31:16]};`
180			`8: mux_data <= {IP_DST[15:0],16'h0000};`
181			`default: mux_data <= {byte_cnt,byte_cnt};//random_data;`
182			`endcase`
183			`end*/`
184			`always@(*)`
185			`begin`
186			`case(word_cnt)`
187			`0: mux_data <= MAC_DST[47:16];`
188			`1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};`
189			`2: mux_data <= MAC_SRC[31:00];`
190			`3: mux_data <= {(config_1[15:0]-16'd14),16'h0000};//{16'h0800,16'h0000};`
191			`4: mux_data <= i32_Payload1;`
192			`5: mux_data <= i32_Payload2;`
193			`6: mux_data <= i32_Payload3;`
194			`7: mux_data <= i32_Payload4;`
195			`default: mux_data <= {32'h0102_0304};//random_data;`
196			`endcase`
197			`end`
198
199
200			`assign time_exp = (timer==0);`
201			`assign pkt_data = mux_data;`
202
203			`//random data generation`
204			`assign shift_random_data = {random_data[30:0],^(random_data&32'h1034_BCFE)};`
205			`always@(posedge clk)`
206			`begin`
207			`if(word_cnt==3 && dv==1'b1)`
208			`random_data <= MAC_DST[31:00];`
209			`else`
210			`if(dv) begin`
211			`random_data <= random_data[31]?shift_random_data:(~shift_random_data);`
212			`end`
213			`end`
214
215			`always@(posedge clk or posedge rst)`
216			`begin`
217			`if(rst) begin`
218			`ip_rand <= 16'h1;`
219			`//For this polynomial, look for maxim-ic.com/app-notes/index.mvp/id/1743`
220			`polynomial[00] = 16'h0;`
221			`polynomial[01] = 16'h0;`
222			`polynomial[02] = 16'h0005;`
223			`polynomial[03] = 16'h0009;`
224			`polynomial[04] = 16'h0012;`
225			`polynomial[05] = 16'h0021;`
226			`polynomial[06] = 16'h0041;`
227			`polynomial[07] = 16'h008E;`
228			`polynomial[08] = 16'h0108;`
229			`polynomial[09] = 16'h0204;`
230			`polynomial[10] = 16'h0402;`
231			`polynomial[11] = 16'h0829;`
232			`polynomial[12] = 16'h100D;`
233			`polynomial[13] = 16'h2015;`
234			`polynomial[14] = 16'h4001;`
235			`polynomial[15] = 16'h8016;`
236			`end`
237			`else`
238			`begin`
239			`if(eop & dv) begin`
240			`ip_rand = {ip_rand[15:0],^(ip_rand&(polynomial[config_1[19:16]]))};`
241			`ip_rand[(config_1[19:16]+1)] = 1'b0;`
242			`//synthesis_off`
243			`$display("IPRAND = %d",ip_rand);`
244			`//synthesis_on`
245			`end`
246			`end`
247			`end`
248
249			`assign src_ip = {IP_SRC[31:16],ip_rand};`
250
251			`//synthesis_off`
252			`/*`
253			`always@(posedge clk or posedge rst)`
254			`begin`
255			`integer found[];`
256			`integer i;`
257			`integer cnt;`
258			`if(rst) begin`
259			`cnt = 0;`
260			`for(i=0;i<5000;i++)`
261			`begin`
262			`found[i]=0;`
263			`end`
264			`end`
265			`else`
266			`begin`
267			`if(sop & dv) begin`
268			`if(found[ip_rand]==0) begin`
269			`cnt++;`
270			`found[ip_rand]=1;`
271			`$display("Total Streams %d",cnt);`
272			`end`
273			`end`
274			`end`
275			`end*/`
276
277			`//synthesis_on`
278
279			`endmodule`