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jefflieu |
/*
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Copyright © 2012 JeffLieu-lieumychuong@gmail.com
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This file is part of SGMII-IP-Core.
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SGMII-IP-Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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SGMII-IP-Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
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File : sgmii_demo.v
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Description : This file implements top-level file to test SGMII core
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Remarks :
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Revision :
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Date Author Description
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*/
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`define CMD_NOP 3'b000
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`define CMD_RD 3'b001
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`define CMD_WR 3'b010
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`define CMD_WT 3'b011
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`define CMD_JMP 3'b100
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`define CMD_JEQ 3'b101
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`define CMD_END 3'b111
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`define MDIO_RD 2'b10
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`define MDIO_WR 2'b01
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`define MDIO_RD_FRAME(RDWR,PHYADDR,REGADDR) {16'h0,2'b01,RDWR,PHYADDR,REGADDR,2'b11}
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`define MDIO_WR_FRAME(RDWR,PHYADDR,REGADDR) {16'h0,2'b01,RDWR,PHYADDR,REGADDR,2'b10}
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`define MDIO_RD_REG27 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd27)}
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`define MDIO_RD_REG17 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd17)}
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`define MDIO_RD_REG00 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_RD,5'b0,5'd0)}
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`define MDIO_RD_REG01 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd01)}
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`define MDIO_RD_REG04 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd04)}
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`define MDIO_RD_REG22 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd22)}
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`define MDIO_WR_REG27 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd27)}
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`define MDIO_WR_REG00 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd0)}
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`define MDIO_WR_REG22 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd22)}
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module mWishboneMaster88E1111#(parameter pCommands=32,pAddrW=8,pChipSelect=2)
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(
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output [pChipSelect-1:0] ov_CSel,
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output o_Cyc,
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output o_Stb,
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output o_WEn,
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output [31:0] o32_WrData,
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input [31:0] i32_RdData,
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output [pAddrW-1:0] ov_Addr,
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input i_Ack,
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input i_ARst_L,
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input i_Clk);
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localparam pInstrWidth = pAddrW+32+3+8+pChipSelect;
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localparam pFETCH = 4'b0001,
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pEXECU = 4'b0010,
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pNEXTI = 4'b0100,
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pWAIT = 4'b1000;
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reg [3:0] r4_State;
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reg [pInstrWidth-1:0] rv_InstrReg;
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reg [pInstrWidth-1:0] rv_MicroCodes[0:pCommands-1];
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reg [31:0] r32_ReadData;
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reg [7:0] r8_InstrCnt;
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reg [31:0] r32_WaitTmr;
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wire [2:0] w3_Opcode;
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wire [7:0] w8_WaitTime;
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/*Instruction Format
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y-bit chipslect, 8-bit WaitTime, 3bit-Opcode, x-bit Address, 32-bit Data
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*/
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assign ov_CSel = rv_InstrReg[pInstrWidth-1-:pChipSelect];
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assign w8_WaitTime = rv_InstrReg[pInstrWidth-1-pChipSelect-:8];
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assign w3_Opcode = rv_InstrReg[pInstrWidth-1-pChipSelect-8-:3];
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assign ov_Addr = rv_InstrReg[pInstrWidth-1-pChipSelect-8-3-:pAddrW];
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assign o32_WrData = rv_InstrReg[31:0];
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always@(posedge i_Clk or negedge i_ARst_L)
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if(!i_ARst_L) begin
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r8_InstrCnt <= 8'h0;
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r4_State <= pFETCH;
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r32_WaitTmr <= 32'h0;
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end
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else begin
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case(r4_State)
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pFETCH : begin
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rv_InstrReg <= rv_MicroCodes[r8_InstrCnt];
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r4_State <= pEXECU;
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end
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pEXECU : begin
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if(w3_Opcode==`CMD_WT)
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begin
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r4_State<=pWAIT;
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r32_WaitTmr <= o32_WrData[31:0];
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end
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else if(w3_Opcode==`CMD_RD||w3_Opcode==`CMD_WR) begin
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if(i_Ack)
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begin
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r4_State<=pWAIT;
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r32_WaitTmr <= {24'h0,w8_WaitTime};
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if(w3_Opcode==`CMD_RD) r32_ReadData <= i32_RdData;
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end
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end
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else begin
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r4_State<=pWAIT;
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r32_WaitTmr <= {24'h0,w8_WaitTime};
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end
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end
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pNEXTI : begin
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if(w3_Opcode==`CMD_JMP)
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r8_InstrCnt <= ov_Addr;
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else
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if(w3_Opcode==`CMD_JEQ) begin
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if(r32_ReadData==o32_WrData)
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r8_InstrCnt <= ov_Addr;
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else
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r8_InstrCnt <= r8_InstrCnt+8'h1;
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end
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else
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r8_InstrCnt <= r8_InstrCnt+8'h1;
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r4_State <= pFETCH;
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end
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pWAIT : if(w3_Opcode==`CMD_END)
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r4_State <= pWAIT;
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else
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if(r32_WaitTmr==0) r4_State <= pNEXTI; else r32_WaitTmr<=r32_WaitTmr-16'h1;
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endcase
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end
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assign o_Cyc = (r4_State==pEXECU)?1'b1:1'b0;
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assign o_Stb = (r4_State==pEXECU)?1'b1:1'b0;
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assign o_WEn = (r4_State==pEXECU&&w3_Opcode==`CMD_WR)?1'b1:1'b0;
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always@(posedge i_Clk)
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begin
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rv_MicroCodes[0] <={2'b01,8'h4,`CMD_RD ,8'h28 ,32'h0 };
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rv_MicroCodes[1] <={2'b01,8'h4,`CMD_WR ,8'h20 ,32'hFFFF };//Set link timer to 1.6ms
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rv_MicroCodes[2] <={2'b01,8'h4,`CMD_WR ,8'h24 ,32'h001F };//
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rv_MicroCodes[3] <={2'b01,8'h4,`CMD_WR ,8'h7C ,32'h0001 };//Enable SGMII Mode, MAC Side
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rv_MicroCodes[4] <={2'b01,8'h4,`CMD_WR ,8'h00 ,32'h1340 };//Restart
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rv_MicroCodes[5] <=`MDIO_RD_REG27;
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rv_MicroCodes[6] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[7] <={2'b10,8'h4,`CMD_RD ,8'h02 ,32'h1340 };//Read MDIO Registers
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rv_MicroCodes[8] <={2'b10,8'h4,`CMD_WR ,8'h01 ,{r32_ReadData[31:4],4'h4}};//Write to Register 27 to change mode
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rv_MicroCodes[9] <=`MDIO_WR_REG27;
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rv_MicroCodes[10] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[11] <=`MDIO_RD_REG22;
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rv_MicroCodes[12] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[13] <={2'b10,8'h4,`CMD_RD ,8'h02 ,32'h1340 };//Read MDIO Registers
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rv_MicroCodes[14] <={2'b10,8'h4,`CMD_WR ,8'h01 ,{r32_ReadData[31:8],8'h01} };//Switch Page
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rv_MicroCodes[15] <=`MDIO_WR_REG22;
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rv_MicroCodes[16] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[17] <={2'b10,8'h4,`CMD_WR ,8'h01 ,32'h0000_9000 };//Soft Reset, Disable Auto Negotiation
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rv_MicroCodes[18] <=`MDIO_WR_REG00;
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rv_MicroCodes[19] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd125_000_000};
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rv_MicroCodes[20] <=`MDIO_RD_REG04;
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rv_MicroCodes[21] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[22] <=`MDIO_RD_REG00;
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rv_MicroCodes[23] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
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rv_MicroCodes[24] <=`MDIO_RD_REG01;
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rv_MicroCodes[25] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048};
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rv_MicroCodes[26] <=`MDIO_RD_REG17;
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rv_MicroCodes[27] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048};
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rv_MicroCodes[28] <={2'b00,8'hFF,`CMD_JMP ,8'd20 ,32'b0 };
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end
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endmodule
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