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//IP Functional Simulation Model
//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:10:19:19:54:28:SJ cbx_simgen 2012:10:19:19:52:08:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
 
 
 
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors.  Please refer to the
// applicable agreement for further details.
 
// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).
 
 
//synopsys translate_off
 
//synthesis_resources = altera_std_synchronizer 8 altera_std_synchronizer_bundle 3 altpll 1 altsyncram 2 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 lut 942 mux21 1096 oper_add 27 oper_decoder 4 oper_less_than 11 oper_mux 16 oper_selector 42
`timescale 1 ps / 1 ps
module  sgmii
        (
        address,
        clk,
        gmii_rx_d,
        gmii_rx_dv,
        gmii_rx_err,
        gmii_tx_d,
        gmii_tx_en,
        gmii_tx_err,
        gxb_cal_blk_clk,
        gxb_pwrdn_in,
        hd_ena,
        led_an,
        led_char_err,
        led_col,
        led_crs,
        led_disp_err,
        led_link,
        mii_col,
        mii_crs,
        mii_rx_d,
        mii_rx_dv,
        mii_rx_err,
        mii_tx_d,
        mii_tx_en,
        mii_tx_err,
        pcs_pwrdn_out,
        read,
        readdata,
        reconfig_busy,
        reconfig_clk,
        reconfig_fromgxb,
        reconfig_togxb,
        ref_clk,
        reset,
        reset_rx_clk,
        reset_tx_clk,
        rx_clk,
        rx_clkena,
        rx_recovclkout,
        rxp,
        set_10,
        set_100,
        set_1000,
        tx_clk,
        tx_clkena,
        txp,
        waitrequest,
        write,
        writedata) /* synthesis synthesis_clearbox=1 */;
        input   [4:0]  address;
        input   clk;
        output   [7:0]  gmii_rx_d;
        output   gmii_rx_dv;
        output   gmii_rx_err;
        input   [7:0]  gmii_tx_d;
        input   gmii_tx_en;
        input   gmii_tx_err;
        input   gxb_cal_blk_clk;
        input   gxb_pwrdn_in;
        output   hd_ena;
        output   led_an;
        output   led_char_err;
        output   led_col;
        output   led_crs;
        output   led_disp_err;
        output   led_link;
        output   mii_col;
        output   mii_crs;
        output   [3:0]  mii_rx_d;
        output   mii_rx_dv;
        output   mii_rx_err;
        input   [3:0]  mii_tx_d;
        input   mii_tx_en;
        input   mii_tx_err;
        output   pcs_pwrdn_out;
        input   read;
        output   [15:0]  readdata;
        input   reconfig_busy;
        input   reconfig_clk;
        output   [4:0]  reconfig_fromgxb;
        input   [3:0]  reconfig_togxb;
        input   ref_clk;
        input   reset;
        input   reset_rx_clk;
        input   reset_tx_clk;
        output   rx_clk;
        output   rx_clkena;
        output   rx_recovclkout;
        input   rxp;
        output   set_10;
        output   set_100;
        output   set_1000;
        output   tx_clk;
        output   tx_clkena;
        output   txp;
        output   waitrequest;
        input   write;
        input   [15:0]  writedata;
 
        wire  wire_n1i10i_dout;
        wire  wire_n1i10O_dout;
        wire  wire_n1i11O_dout;
        wire  wire_n1i1ii_dout;
        wire  wire_nlili0O_dout;
        wire  wire_nliliii_dout;
        wire  wire_nliliil_dout;
        wire  wire_nliliiO_dout;
        wire  [1:0]   wire_n01ill_dout;
        wire  [1:0]   wire_n01ilO_dout;
        wire  [15:0]   wire_n1i10l_dout;
        wire  [5:0]   wire_nl01O_clk;
        wire  wire_nl01O_fref;
        wire  wire_nl01O_icdrclk;
        wire  wire_nl01O_locked;
        wire  [9:0]   wire_n00OOO_q_b;
        wire  [9:0]   wire_ni1O0i_q_b;
        wire  wire_nl0iO_nonusertocmu;
        wire  wire_nl0il_dpriodisableout;
        wire  wire_nl0il_dprioout;
        wire  wire_nl0il_quadresetout;
        wire  [3:0]   wire_nl0il_rxanalogresetout;
        wire  [3:0]   wire_nl0il_rxcrupowerdown;
        wire  [3:0]   wire_nl0il_rxdigitalresetout;
        wire  [3:0]   wire_nl0il_rxibpowerdown;
        wire  [1599:0]   wire_nl0il_rxpcsdprioout;
        wire  [1199:0]   wire_nl0il_rxpmadprioout;
        wire  [3:0]   wire_nl0il_txanalogresetout;
        wire  [3:0]   wire_nl0il_txdetectrxpowerdown;
        wire  [3:0]   wire_nl0il_txdigitalresetout;
        wire  [3:0]   wire_nl0il_txdividerpowerdown;
        wire  [3:0]   wire_nl0il_txobpowerdown;
        wire  [599:0]   wire_nl0il_txpcsdprioout;
        wire  [1199:0]   wire_nl0il_txpmadprioout;
        wire  wire_nl0ii_cdrctrllocktorefclkout;
        wire  wire_nl0ii_clkout;
        wire  [1:0]   wire_nl0ii_ctrldetect;
        wire  [19:0]   wire_nl0ii_dataout;
        wire  [1:0]   wire_nl0ii_disperr;
        wire  [399:0]   wire_nl0ii_dprioout;
        wire  [1:0]   wire_nl0ii_errdetect;
        wire  [1:0]   wire_nl0ii_patterndetect;
        wire  wire_nl0ii_rlv;
        wire  [1:0]   wire_nl0ii_runningdisp;
        wire  [1:0]   wire_nl0ii_syncstatus;
        wire  wire_nl00O_clockout;
        wire  wire_nl00O_diagnosticlpbkout;
        wire  [299:0]   wire_nl00O_dprioout;
        wire  wire_nl00O_freqlocked;
        wire  [9:0]   wire_nl00O_recoverdataout;
        wire  wire_nl00O_reverselpbkout;
        wire  wire_nl00O_signaldetect;
        wire  wire_nl00l_clkout;
        wire  [9:0]   wire_nl00l_dataout;
        wire  [149:0]   wire_nl00l_dprioout;
        wire  wire_nl00l_txdetectrx;
        wire  wire_nl00i_clockout;
        wire  wire_nl00i_dataout;
        wire  [299:0]   wire_nl00i_dprioout;
        wire  wire_nl00i_seriallpbkout;
        reg     nli000i55;
        reg     nli000i56;
        reg     nli001O57;
        reg     nli001O58;
        reg     nli010i59;
        reg     nli010i60;
        reg     nli011l63;
        reg     nli011l64;
        reg     nli011O61;
        reg     nli011O62;
        reg     nli0l0i53;
        reg     nli0l0i54;
        reg     nli0lii51;
        reg     nli0lii52;
        reg     nli0liO49;
        reg     nli0liO50;
        reg     nli0lll47;
        reg     nli0lll48;
        reg     nli0lOi45;
        reg     nli0lOi46;
        reg     nli0O0i41;
        reg     nli0O0i42;
        reg     nli0O1l43;
        reg     nli0O1l44;
        reg     nli0Oii39;
        reg     nli0Oii40;
        reg     nli0OiO37;
        reg     nli0OiO38;
        reg     nli0OlO35;
        reg     nli0OlO36;
        reg     nli0OOl33;
        reg     nli0OOl34;
        reg     nli1llO79;
        reg     nli1llO80;
        reg     nli1lOi77;
        reg     nli1lOi78;
        reg     nli1O0O75;
        reg     nli1O0O76;
        reg     nli1Oii73;
        reg     nli1Oii74;
        reg     nli1Oil71;
        reg     nli1Oil72;
        reg     nli1OlO69;
        reg     nli1OlO70;
        reg     nli1OOi67;
        reg     nli1OOi68;
        reg     nli1OOl65;
        reg     nli1OOl66;
        reg     nlii00l13;
        reg     nlii00l14;
        reg     nlii01i19;
        reg     nlii01i20;
        reg     nlii01l17;
        reg     nlii01l18;
        reg     nlii01O15;
        reg     nlii01O16;
        reg     nlii0ii11;
        reg     nlii0ii12;
        reg     nlii0il10;
        reg     nlii0il9;
        reg     nlii0Oi7;
        reg     nlii0Oi8;
        reg     nlii0Ol5;
        reg     nlii0Ol6;
        reg     nlii0OO3;
        reg     nlii0OO4;
        reg     nlii10i29;
        reg     nlii10i30;
        reg     nlii10O27;
        reg     nlii10O28;
        reg     nlii11l31;
        reg     nlii11l32;
        reg     nlii1iO25;
        reg     nlii1iO26;
        reg     nlii1ll23;
        reg     nlii1ll24;
        reg     nlii1Ol21;
        reg     nlii1Ol22;
        reg     nliii1l1;
        reg     nliii1l2;
        reg     n00iO;
        reg     n011l;
        reg     n011O;
        reg     n01ll;
        reg     n01Ol;
        reg     n01OO;
        reg     n10ii;
        reg     n10il;
        reg     n11OO;
        reg     n1i1l;
        reg     n1l1i;
        reg     n1O0i;
        reg     n00ll;
        reg     n01lO;
        reg     n101i;
        reg     n10lO;
        reg     n1i0O;
        reg     n1iiO;
        reg     n1ill;
        reg     n1iOO;
        reg     n1l0O;
        reg     n1lii;
        reg     n1llO;
        reg     n1O1i;
        reg     n1O1l;
        reg     n1O1O;
        reg     n1Oll;
        reg     n1OlO;
        reg     n00Oii;
        reg     n00Oll;
        reg     n00OOl;
        reg     n01iil;
        reg     n01ili;
        reg     n0i01l;
        reg     n0i10i;
        reg     n0i10l;
        reg     n0i11i;
        reg     n0i11l;
        reg     n0i11O;
        reg     n0i1iO;
        reg     n0i1li;
        reg     n0i1ll;
        reg     n0i1Ol;
        reg     n0i1OO;
        reg     n0i0l;
        reg     n0iii;
        reg     n0i1Oi;
        reg     n0ii0O;
        reg     n0i0iO;
        reg     n0i0li;
        reg     n0i0ll;
        reg     n0i0lO;
        reg     n0i0Oi;
        reg     n0ii0i;
        reg     n0ii1l;
        reg     n0ii1O;
        reg     n0iiil;
        reg     n0iiiO;
        reg     n0iill;
        reg     n0iOii;
        reg     n0iO0i;
        reg     n0010i;
        reg     n0010l;
        reg     n0010O;
        reg     n0011i;
        reg     n001ii;
        reg     n001il;
        reg     n001iO;
        reg     n001li;
        reg     n00lOO;
        reg     n00O0l;
        reg     n00O0O;
        reg     n00O1i;
        reg     n00Oil;
        reg     n00OiO;
        reg     n00Oli;
        reg     n00OlO;
        reg     n01l0l;
        reg     n01l0O;
        reg     n01lOi;
        reg     n01lOl;
        reg     n01lOO;
        reg     n01O0i;
        reg     n01O0l;
        reg     n01O0O;
        reg     n01O1i;
        reg     n01O1l;
        reg     n01O1O;
        reg     n01Oii;
        reg     n01OiO;
        reg     n01OOO;
        reg     n0ilOi;
        reg     n0ilOO;
        reg     n0iO1i;
        reg     n0iO1l;
        reg     n0l01i;
        reg     n0l01O;
        reg     n0l11l;
        reg     n0l1iO;
        reg     n0l1ll;
        reg     n0l1lO;
        reg     n0l1Oi;
        reg     n0l1Ol;
        reg     n0l1OO;
        reg     n0iOil;
        reg     n0iOli;
        reg     n0iOll;
        reg     n0iOlO;
        reg     n0iOOi;
        reg     n0iOOl;
        reg     n0iOOO;
        reg     n0l0ll;
        reg     n0l11i;
        reg     n0li0O;
        reg     n0liil;
        reg     n0lili;
        reg     n0liOi;
        reg     n0liOl;
        reg     n0liOO;
        reg     n0ll1i;
        reg     n0ll1l;
        reg     n0ll1O;
        reg     n0llli;
        reg     n0llll;
        reg     n0lllO;
        reg     n0llOi;
        reg     n0llOl;
        reg     n0llOO;
        reg     n0O10i;
        reg     n0O10l;
        reg     n0O10O;
        reg     n0O11O;
        reg     n0O1ii;
        reg     n0O1il;
        reg     n0O1iO;
        reg     n0O1li;
        reg     n0O1ll;
        reg     n0O1Oi;
        reg     n0O0ll;
        reg     n0O0Oi;
        reg     n0Oiil;
        reg     n101ll;
        reg     nlOi01l;
        reg     n0lO0O;
        reg     n0lO1i;
        reg     n0O0iO;
        reg     n0O11i;
        reg     n0Oi1i;
        reg     n0Oili;
        reg     nlil01i;
        reg     nlil01l;
        reg     nlil01O;
        reg     nlil10i;
        reg     nlil1li;
        reg     nlil1ll;
        reg     nlil1lO;
        reg     nlil1Oi;
        reg     nlil1Ol;
        reg     nlil1OO;
        reg     nlili1i;
        reg     n0O0li;
        reg     n0O0lO;
        reg     n0OilO;
        reg     nlil0OO;
        reg     nlil1il;
        reg     nlili1l;
        reg     n01i0O;
        reg     n01iii;
        reg     n0OiOi;
        reg     n0OiOl;
        reg     n0OiOO;
        reg     n0Ol1l;
        reg     n0Ol0i;
        reg     n0Ol0l;
        reg     n0Ol0O;
        reg     n0Ol1O;
        reg     n0Olii;
        reg     n0Olil;
        reg     n0OliO;
        reg     n0Olli;
        reg     n0Olll;
        reg     n0OO1l;
        reg     n110l;
        reg     n11ii;
        reg     nl010i;
        reg     nllllO;
        reg     nlOOll;
        reg     n11il;
        reg     n11iO;
        reg     n11li;
        reg     n11ll;
        reg     n11lO;
        reg     n11Ol;
        wire    wire_n11Oi_CLRN;
        reg     ni00ll;
        reg     ni001i;
        reg     ni001l;
        reg     ni001O;
        reg     ni00ii;
        reg     ni00il;
        reg     ni00iO;
        reg     ni00lO;
        reg     ni00Oi;
        reg     ni00OO;
        reg     ni01Ol;
        reg     ni01OO;
        reg     ni010i;
        reg     ni010l;
        reg     ni01ii;
        reg     ni1O0l;
        reg     ni1O0O;
        reg     ni1Oii;
        reg     ni1Oil;
        reg     ni1OiO;
        reg     ni1OOi;
        reg     ni1OOl;
        reg     ni1OOO;
        reg     ni011l;
        reg     ni0lli;
        reg     ni0l0i;
        reg     ni0l0l;
        reg     ni0l0O;
        reg     ni0l1l;
        reg     ni0O0O;
        reg     ni1i1l;
        reg     ni0OOi;
        reg     ni0OOO;
        reg     nii10i;
        reg     nii10l;
        reg     nii11i;
        reg     nii11l;
        reg     nii11O;
        reg     nii1ii;
        reg     ni0lll;
        reg     ni0lOi;
        reg     ni0lOl;
        reg     ni0lOO;
        reg     ni0O0i;
        reg     ni0O1i;
        reg     ni0O1l;
        reg     ni0O1O;
        reg     nii00l;
        reg     nii00O;
        reg     nii0ii;
        reg     nii0il;
        reg     nii0iO;
        reg     nii0li;
        reg     nii0ll;
        reg     nii0lO;
        reg     nii0Oi;
        reg     nii0Ol;
        reg     nii0OO;
        reg     niii0l;
        reg     niii0O;
        reg     niii1l;
        reg     niiiii;
        reg     niiiil;
        reg     niiiiO;
        reg     niiili;
        reg     niiill;
        reg     niiilO;
        reg     nil00i;
        reg     nil01l;
        reg     nil01O;
        reg     nil0ii;
        reg     nil1Ol;
        reg     nil1OO;
        reg     ni0lii;
        reg     nil00l;
        reg     nil01i;
        reg     nil0iO;
        reg     n011il;
        reg     n1i00i;
        reg     n1i00l;
        reg     n1i00O;
        reg     n1i0ii;
        reg     n1i0iO;
        reg     n1i1il;
        reg     n1i1lO;
        reg     nili0i;
        reg     nili0l;
        reg     niO00i;
        reg     niO01l;
        reg     niO0ii;
        reg     niO1ll;
        reg     niO1Oi;
        reg     niO1OO;
        reg     nliil0l;
        reg     nliiOlO;
        reg     nliiOOl;
        reg     n0OllO;
        reg     n0OlOl;
        reg     n0OlOO;
        reg     n0OO0i;
        reg     n0OO0l;
        reg     n0OO0O;
        reg     n0OO1O;
        reg     n0OOii;
        reg     n0OOil;
        reg     n0OOiO;
        reg     n0OOli;
        reg     ni10Ol;
        reg     ni10OO;
        reg     ni1i0i;
        reg     ni1i0l;
        reg     ni1i0O;
        reg     ni1i1O;
        reg     ni1iii;
        reg     ni1iil;
        reg     ni1iiO;
        reg     ni1ili;
        reg     ni1ill;
        reg     ni1ilO;
        reg     ni1iOi;
        reg     ni1iOl;
        reg     ni1iOO;
        reg     ni1l0i;
        reg     ni1l0l;
        reg     ni1l0O;
        reg     ni1l1i;
        reg     ni1l1l;
        reg     ni1l1O;
        reg     ni1lii;
        reg     ni1lil;
        reg     ni1liO;
        reg     ni1lli;
        reg     ni1lll;
        reg     ni1llO;
        reg     ni1lOi;
        reg     ni1lOl;
        reg     ni1lOO;
        reg     ni1O1i;
        reg     ni1O1l;
        reg     ni1O1O;
        reg     nill0l;
        reg     nilOOi;
        reg     nilOOl;
        reg     nilOOO;
        reg     niO0il;
        reg     niO0li;
        reg     niO10i;
        reg     niO10l;
        reg     niO10O;
        reg     niO11i;
        reg     niO11l;
        reg     niO11O;
        reg     n0O1i;
        reg     niO0O;
        reg     niOiO;
        wire    wire_niOil_PRN;
        reg     nl00ii;
        wire    wire_nl000O_ENA;
        reg     n0lil;
        reg     niO1i;
        reg     niOii;
        reg     niOli;
        reg     niOll;
        reg     niOlO;
        reg     niOOi;
        reg     niOOl;
        reg     niOOO;
        reg     nl01l;
        reg     nl10i;
        reg     nl10l;
        reg     nl10O;
        reg     nl11i;
        reg     nl11l;
        reg     nl11O;
        reg     nl1ii;
        reg     nl1il;
        reg     nl1iO;
        reg     nl1li;
        reg     nl1ll;
        reg     nl1lO;
        reg     nl1Oi;
        reg     nl1Ol;
        reg     nl1OO;
        wire    wire_nl01i_CLRN;
        reg     nl00ll;
        reg     nl00Oi;
        reg     nl00Ol;
        reg     nl00OO;
        reg     nl0i1i;
        reg     nl0i1O;
        reg     nl0i0i;
        reg     nl0i0O;
        reg     nl0iii;
        reg     nl0iiO;
        reg     nl0ilO;
        reg     nl0iOl;
        reg     nl0iOO;
        reg     nl0l0i;
        reg     nl0l0O;
        reg     nl0l1O;
        reg     nl0iil;
        reg     nl0ili;
        reg     nl0ill;
        reg     nl0iOi;
        reg     nl0l1l;
        reg     nl0li;
        reg     nl0lO;
        wire    wire_nl0ll_PRN;
        reg     nl0liO;
        reg     nl0lll;
        reg     nl0lii;
        reg     nl0lil;
        reg     nl0lOi;
        reg     nl0llO_clk_prev;
        wire    wire_nl0llO_CLRN;
        wire    wire_nl0llO_PRN;
        reg     nl111i;
        reg     nl1i0l;
        reg     nl1i0O;
        reg     nl1iii;
        reg     nl1iil;
        reg     nl1iiO;
        reg     nl1ili;
        reg     nl1ill;
        reg     nl1ilO;
        reg     nl1iOi;
        reg     nl1iOl;
        reg     nl1iOO;
        reg     nl1l0l;
        reg     nl1l1i;
        reg     nl1l1l;
        reg     nl1l1O;
        reg     nli0O;
        reg     nli0l_clk_prev;
        wire    wire_nli0l_CLRN;
        wire    wire_nli0l_PRN;
        reg     nl0lOl;
        reg     nl0O0i;
        reg     nl0O0l;
        reg     nl0O0O;
        reg     nl0O1l;
        reg     nl0O1O;
        reg     nl0Oii;
        reg     nl0Oil;
        reg     nl0OiO;
        reg     nl0Oli;
        reg     nl0Oll;
        reg     nl0OlO;
        reg     nl0OOi;
        reg     nl0OOl;
        reg     nl0OOO;
        reg     nli11l;
        reg     nli00i;
        reg     nli00l;
        reg     nli00O;
        reg     nli01O;
        reg     nli0ii;
        reg     nli0il;
        reg     nli0iO;
        reg     nli0li;
        reg     nli0ll;
        reg     nli0lO;
        reg     nli0Oi;
        reg     nli0Ol;
        reg     nli0OO;
        reg     nli1OO;
        reg     nlii1i;
        reg     nlii1O;
        wire    wire_nlii1l_CLRN;
        reg     nliii0O;
        reg     nliiiil;
        reg     nliiiiO;
        reg     nliiill;
        reg     nli0i;
        reg     nlili;
        reg     nliiO_clk_prev;
        wire    wire_nliiO_CLRN;
        wire    wire_nliiO_PRN;
        reg     nlii0i;
        reg     nliilO;
        reg     nliiOl;
        reg     nliill;
        reg     nliiOO;
        reg     nlil1l;
        reg     nlil1i_clk_prev;
        wire    wire_nlil1i_CLRN;
        wire    wire_nlil1i_PRN;
        reg     nlili0l;
        reg     nlili1O;
        reg     n010li;
        reg     n010ll;
        reg     n0110i;
        reg     n0110l;
        reg     n0110O;
        reg     n0111i;
        reg     n0111l;
        reg     n0111O;
        reg     n011ii;
        reg     n01i0i;
        reg     n01i0l;
        reg     n01i1i;
        reg     n01i1O;
        reg     n1i01i;
        reg     n1i01l;
        reg     n1i01O;
        reg     n1i0il;
        reg     n1i0li;
        reg     n1OOiO;
        reg     n1OOli;
        reg     n1OOll;
        reg     n1OOlO;
        reg     n1OOOi;
        reg     n1OOOl;
        reg     n1OOOO;
        reg     nili1l;
        reg     nili1O;
        reg     niliil;
        reg     nilill;
        reg     nililO;
        reg     niliOi;
        reg     niliOl;
        reg     niliOO;
        reg     nill0i;
        reg     nill1i;
        reg     nill1l;
        reg     nill1O;
        reg     niO00l;
        reg     niO01i;
        reg     niO01O;
        reg     niO0OO;
        reg     niO1ii;
        reg     niO1il;
        reg     niO1lO;
        reg     niO1Ol;
        reg     niOi0i;
        reg     niOi1l;
        reg     niOi1O;
        reg     niOiiO;
        reg     niOill;
        reg     niOiOi;
        reg     niOiOl;
        reg     niOiOO;
        reg     niOl1i;
        reg     niOl1l;
        reg     nliil1i;
        reg     nliilii;
        reg     nliilil;
        reg     nliiliO;
        reg     nliilli;
        reg     nliilll;
        reg     nliillO;
        reg     nliilOi;
        reg     nliilOl;
        reg     nliilOO;
        reg     nliiOOi;
        reg     nll0iO;
        reg     nll0li;
        reg     nll0ll;
        reg     nll0Oi;
        wire    wire_nll0lO_CLRN;
        reg     nll10l;
        reg     nll10i_clk_prev;
        wire    wire_nll10i_CLRN;
        wire    wire_nll10i_PRN;
        reg     nliOiO;
        reg     nll11l;
        reg     nll11O;
        reg     nll1ii;
        reg     nll10O_clk_prev;
        wire    wire_nll10O_PRN;
        reg     n0O11l;
        reg     n0Oi0i;
        reg     n1010i;
        reg     n1010l;
        reg     n1010O;
        reg     n1011i;
        reg     n1011l;
        reg     n1011O;
        reg     n101ii;
        reg     n101il;
        reg     n101iO;
        reg     n101li;
        reg     n10l0i;
        reg     n10l0l;
        reg     n10l0O;
        reg     n10lii;
        reg     n10lil;
        reg     n10liO;
        reg     n10lli;
        reg     n10lll;
        reg     n10llO;
        reg     n10lOi;
        reg     n10lOl;
        reg     n10lOO;
        reg     n10OlO;
        reg     n10OOi;
        reg     n11OiO;
        reg     n11Oli;
        reg     n11Oll;
        reg     n11OlO;
        reg     n11OOi;
        reg     n11OOl;
        reg     n11OOO;
        reg     n1i11l;
        reg     nl011i;
        reg     nl1l0O;
        reg     nl1Oil;
        reg     nl1OiO;
        reg     nl1Oli;
        reg     nl1Oll;
        reg     nl1OlO;
        reg     nl1OOi;
        reg     nl1OOl;
        reg     nl1OOO;
        reg     nli1lO;
        reg     nli1Oi;
        reg     nli1Ol;
        reg     nliOlOi;
        reg     nliOO0l;
        reg     nliOOiO;
        reg     nliOOli;
        reg     nliOOll;
        reg     nliOOlO;
        reg     nliOOOi;
        reg     nliOOOl;
        reg     nliOOOO;
        reg     nll001i;
        reg     nll001l;
        reg     nll010l;
        reg     nll010O;
        reg     nll01il;
        reg     nll01lO;
        reg     nll01OO;
        reg     nll0i0l;
        reg     nll0i0O;
        reg     nll0i1l;
        reg     nll0ill;
        reg     nll0ilO;
        reg     nll0iOi;
        reg     nll0iOl;
        reg     nll0iOO;
        reg     nll0l0i;
        reg     nll0l0l;
        reg     nll0l0O;
        reg     nll0l1i;
        reg     nll0l1l;
        reg     nll0l1O;
        reg     nll0lii;
        reg     nll0lil;
        reg     nll0liO;
        reg     nll0lli;
        reg     nll0lll;
        reg     nll110i;
        reg     nll110l;
        reg     nll110O;
        reg     nll111i;
        reg     nll111l;
        reg     nll111O;
        reg     nll11ii;
        reg     nll11il;
        reg     nll11iO;
        reg     nll11li;
        reg     nll11ll;
        reg     nll11lO;
        reg     nll11Oi;
        reg     nll11Ol;
        reg     nll11OO;
        reg     nlli0l;
        reg     nlli1O;
        reg     nlliii;
        reg     nlliil;
        reg     nllil0l;
        reg     nllil0O;
        reg     nllil1i;
        reg     nllili;
        reg     nllilii;
        reg     nllilil;
        reg     nlliliO;
        reg     nllilli;
        reg     nllilll;
        reg     nllillO;
        reg     nllilOi;
        reg     nllilOl;
        reg     nllilOO;
        reg     nlliO0i;
        reg     nlliO0l;
        reg     nlliO0O;
        reg     nlliO1i;
        reg     nlliO1l;
        reg     nlliO1O;
        reg     nlliOii;
        reg     nlliOil;
        reg     nlliOiO;
        reg     nlliOli;
        reg     nllO1lO;
        reg     nllO1Oi;
        reg     nllO1Ol;
        reg     nllOi0i;
        reg     nllOi0l;
        reg     nllOi1l;
        reg     nllOi1O;
        reg     nllOO0i;
        reg     nllOO0l;
        reg     nllOO0O;
        reg     nllOO1i;
        reg     nllOO1l;
        reg     nllOO1O;
        reg     nllOOii;
        reg     nllOOil;
        reg     nllOOiO;
        reg     nllOOli;
        reg     nllOOll;
        reg     nllOOlO;
        reg     nllOOOi;
        reg     nllOOOl;
        reg     nllOOOO;
        reg     nlO101i;
        reg     nlO101l;
        reg     nlO110i;
        reg     nlO110l;
        reg     nlO110O;
        reg     nlO111i;
        reg     nlO111l;
        reg     nlO111O;
        reg     nlO11ii;
        reg     nlO11il;
        reg     nlO11iO;
        reg     nlO11li;
        reg     nlO11ll;
        reg     nlO11lO;
        reg     nlO11Oi;
        reg     nlO11Ol;
        reg     nlO11OO;
        reg     nlOi01i;
        reg     nlOi01O;
        reg     nlOi1ll;
        reg     nlOi1lO;
        reg     nlOi1Oi;
        reg     nlOi1Ol;
        reg     nlOi1OO;
        reg     nlOiilO;
        reg     nlOiiOi;
        reg     nlOil0l;
        reg     nlOil0O;
        reg     nlOilii;
        reg     nlOilil;
        reg     nlOiliO;
        reg     nlOilli;
        reg     nlOilll;
        reg     nlOillO;
        reg     nlOilOi;
        reg     nlOilOl;
        reg     nlOilOO;
        reg     nlOiO0i;
        reg     nlOiO0l;
        reg     nlOiO0O;
        reg     nlOiO1i;
        reg     nlOiO1l;
        reg     nlOiO1O;
        reg     nlOiOii;
        reg     nlOiOil;
        reg     nlOiOiO;
        reg     nlOiOli;
        reg     nlOiOll;
        reg     nlOiOlO;
        reg     nlOiOOi;
        reg     nlOiOOl;
        reg     nlOiOOO;
        reg     nlOl10i;
        reg     nlOl11i;
        reg     nlOl11l;
        reg     nlOl11O;
        reg     nlOlOlO;
        reg     nlOO00i;
        reg     nlOO01i;
        reg     nlOO01l;
        reg     nlOO01O;
        reg     nlOO10i;
        reg     nlOO10l;
        reg     nlOO10O;
        reg     nlOO11l;
        reg     nlOO1ii;
        reg     nlOO1il;
        reg     nlOO1iO;
        reg     nlOO1li;
        reg     nlOO1ll;
        reg     nlOO1lO;
        reg     nlOO1Oi;
        reg     nlOO1Ol;
        reg     nlOO1OO;
        reg     nlOOlOO;
        reg     nlliiO_clk_prev;
        wire    wire_nlliiO_CLRN;
        wire    wire_nlliiO_PRN;
        reg     niOO0i;
        reg     niOO0l;
        reg     niOO0O;
        reg     niOO1i;
        reg     niOO1l;
        reg     niOO1O;
        reg     niOOii;
        reg     niOOil;
        reg     niOOiO;
        reg     niOOli;
        reg     niOOll;
        reg     niOOlO;
        reg     niOOOi;
        reg     niOOOl;
        reg     niOOOO;
        reg     nl010l;
        reg     nl011l;
        reg     nl011O;
        reg     nl1i0i;
        reg     nli10l;
        reg     nli10O;
        reg     nli11O;
        reg     nli1ll;
        reg     nlil0i;
        reg     nlil0O;
        reg     nlil1O;
        reg     nlilii;
        reg     nlilOl;
        reg     nliO0l;
        reg     nliO0O;
        reg     nliOii;
        reg     nliOil;
        reg     nll00i;
        reg     nll00l;
        reg     nll01i;
        reg     nll01l;
        reg     nll01O;
        reg     nll0Ol;
        reg     nll11i;
        reg     nll1il;
        reg     nll1iO;
        reg     nll1OO;
        reg     nlli1i;
        reg     nlli1l;
        reg     nllill;
        reg     nlliOi;
        reg     nlliOl;
        reg     nlliOO;
        reg     nlll0i;
        reg     nlll0l;
        reg     nlll0O;
        reg     nlllii;
        reg     nlllil;
        reg     nllliO;
        reg     nlllli;
        reg     nlllll;
        reg     nllOil;
        reg     nllOiO;
        reg     nllOli;
        reg     nllOll;
        reg     nllOlO;
        reg     nllOOi;
        reg     nllOOl;
        reg     nllOOO;
        reg     nlO00i;
        reg     nlO00l;
        reg     nlO00O;
        reg     nlO01i;
        reg     nlO01l;
        reg     nlO01O;
        reg     nlO0ii;
        reg     nlO0il;
        reg     nlO0iO;
        reg     nlO0li;
        reg     nlO0ll;
        reg     nlO0lO;
        reg     nlO0Oi;
        reg     nlO0Ol;
        reg     nlO0OO;
        reg     nlO10i;
        reg     nlO10l;
        reg     nlO10O;
        reg     nlO11i;
        reg     nlO11l;
        reg     nlO11O;
        reg     nlO1ii;
        reg     nlO1il;
        reg     nlO1iO;
        reg     nlO1li;
        reg     nlO1ll;
        reg     nlO1lO;
        reg     nlO1Oi;
        reg     nlO1Ol;
        reg     nlO1OO;
        reg     nlOi1i;
        reg     nlOi1l;
        reg     nlOOii;
        reg     nlOOil;
        reg     nlOOiO;
        reg     nlOOli;
        reg     nlOOOi;
        wire    wire_nlOOlO_CLRN;
        wire    wire_n0000i_dataout;
        wire    wire_n0000l_dataout;
        wire    wire_n0000O_dataout;
        wire    wire_n0001i_dataout;
        wire    wire_n0001l_dataout;
        wire    wire_n0001O_dataout;
        wire    wire_n000i_dataout;
        wire    wire_n000ii_dataout;
        wire    wire_n000il_dataout;
        wire    wire_n000iO_dataout;
        wire    wire_n000l_dataout;
        wire    wire_n000li_dataout;
        wire    wire_n000ll_dataout;
        wire    wire_n000lO_dataout;
        wire    wire_n000O_dataout;
        wire    wire_n000Oi_dataout;
        wire    wire_n000Ol_dataout;
        wire    wire_n000OO_dataout;
        wire    wire_n0011l_dataout;
        wire    wire_n0011O_dataout;
        wire    wire_n001i_dataout;
        wire    wire_n001l_dataout;
        wire    wire_n001ll_dataout;
        wire    wire_n001lO_dataout;
        wire    wire_n001O_dataout;
        wire    wire_n001Oi_dataout;
        wire    wire_n001Ol_dataout;
        wire    wire_n001OO_dataout;
        wire    wire_n00i0i_dataout;
        wire    wire_n00i0l_dataout;
        wire    wire_n00i0O_dataout;
        wire    wire_n00i1i_dataout;
        wire    wire_n00iii_dataout;
        wire    wire_n00iil_dataout;
        wire    wire_n00iiO_dataout;
        wire    wire_n00ili_dataout;
        wire    wire_n00l0i_dataout;
        wire    wire_n00l1O_dataout;
        wire    wire_n00lii_dataout;
        wire    wire_n00lil_dataout;
        wire    wire_n00liO_dataout;
        wire    wire_n00lli_dataout;
        wire    wire_n00lll_dataout;
        wire    wire_n00O1l_dataout;
        wire    wire_n00O1O_dataout;
        wire    wire_n0100i_dataout;
        wire    wire_n0100l_dataout;
        wire    wire_n0100O_dataout;
        wire    wire_n0101i_dataout;
        wire    wire_n0101l_dataout;
        wire    wire_n0101O_dataout;
        wire    wire_n010i_dataout;
        wire    wire_n010ii_dataout;
        wire    wire_n010il_dataout;
        wire    wire_n010iO_dataout;
        wire    wire_n010l_dataout;
        wire    wire_n010lO_dataout;
        wire    wire_n010O_dataout;
        wire    wire_n011iO_dataout;
        wire    wire_n011li_dataout;
        wire    wire_n011ll_dataout;
        wire    wire_n011lO_dataout;
        wire    wire_n011Oi_dataout;
        wire    wire_n011Ol_dataout;
        wire    wire_n011OO_dataout;
        wire    wire_n01i1l_dataout;
        wire    wire_n01ii_dataout;
        wire    wire_n01il_dataout;
        wire    wire_n01iO_dataout;
        wire    wire_n01lii_dataout;
        wire    wire_n01lil_dataout;
        wire    wire_n01liO_dataout;
        wire    wire_n01lll_dataout;
        wire    wire_n01llO_dataout;
        wire    wire_n01Oli_dataout;
        wire    wire_n0i00i_dataout;
        wire    wire_n0i00l_dataout;
        wire    wire_n0i00O_dataout;
        wire    wire_n0i01O_dataout;
        wire    wire_n0iilO_dataout;
        wire    wire_n0iiOi_dataout;
        wire    wire_n0iiOl_dataout;
        wire    wire_n0iiOO_dataout;
        wire    wire_n0il0i_dataout;
        wire    wire_n0il0l_dataout;
        wire    wire_n0il0O_dataout;
        wire    wire_n0il1O_dataout;
        wire    wire_n0ilii_dataout;
        wire    wire_n0ilil_dataout;
        wire    wire_n0iliO_dataout;
        wire    wire_n0illi_dataout;
        wire    wire_n0illl_dataout;
        wire    wire_n0illO_dataout;
        wire    wire_n0l0lO_dataout;
        wire    wire_n0l0Oi_dataout;
        wire    wire_n0lill_dataout;
        wire    wire_n0ll0i_dataout;
        wire    wire_n0ll0l_dataout;
        wire    wire_n0ll0O_dataout;
        wire    wire_n0llii_dataout;
        wire    wire_n0llil_dataout;
        wire    wire_n0lliO_dataout;
        wire    wire_n0lO0i_dataout;
        wire    wire_n0lO0l_dataout;
        wire    wire_n0lO1l_dataout;
        wire    wire_n0lO1O_dataout;
        wire    wire_n0O00i_dataout;
        wire    wire_n0O00l_dataout;
        wire    wire_n0O00O_dataout;
        wire    wire_n0O01i_dataout;
        wire    wire_n0O01l_dataout;
        wire    wire_n0O01O_dataout;
        wire    wire_n0O0ii_dataout;
        wire    wire_n0O0il_dataout;
        wire    wire_n0O1Ol_dataout;
        wire    wire_n0O1OO_dataout;
        wire    wire_n0Oi0l_dataout;
        wire    wire_n0Oi0O_dataout;
        wire    wire_n0OOll_dataout;
        wire    wire_n0OOlO_dataout;
        wire    wire_n0OOOi_dataout;
        wire    wire_n0OOOl_dataout;
        wire    wire_n0OOOO_dataout;
        wire    wire_n1000i_dataout;
        wire    wire_n1000l_dataout;
        wire    wire_n1000O_dataout;
        wire    wire_n1001i_dataout;
        wire    wire_n1001l_dataout;
        wire    wire_n1001O_dataout;
        wire    wire_n100i_dataout;
        wire    wire_n100ii_dataout;
        wire    wire_n100il_dataout;
        wire    wire_n100iO_dataout;
        wire    wire_n100l_dataout;
        wire    wire_n100li_dataout;
        wire    wire_n100ll_dataout;
        wire    wire_n100lO_dataout;
        wire    wire_n100Oi_dataout;
        wire    wire_n100Ol_dataout;
        wire    wire_n100OO_dataout;
        wire    wire_n101l_dataout;
        wire    wire_n101lO_dataout;
        wire    wire_n101O_dataout;
        wire    wire_n101Oi_dataout;
        wire    wire_n101Ol_dataout;
        wire    wire_n101OO_dataout;
        wire    wire_n10i0i_dataout;
        wire    wire_n10i0l_dataout;
        wire    wire_n10i0O_dataout;
        wire    wire_n10i1i_dataout;
        wire    wire_n10i1l_dataout;
        wire    wire_n10i1O_dataout;
        wire    wire_n10iii_dataout;
        wire    wire_n10iil_dataout;
        wire    wire_n10iiO_dataout;
        wire    wire_n10ili_dataout;
        wire    wire_n10ill_dataout;
        wire    wire_n10ilO_dataout;
        wire    wire_n10iOi_dataout;
        wire    wire_n10iOl_dataout;
        wire    wire_n10iOO_dataout;
        wire    wire_n10l1i_dataout;
        wire    wire_n10l1l_dataout;
        wire    wire_n10l1O_dataout;
        wire    wire_n10O0i_dataout;
        wire    wire_n10O0l_dataout;
        wire    wire_n10O0O_dataout;
        wire    wire_n10O1i_dataout;
        wire    wire_n10O1l_dataout;
        wire    wire_n10O1O_dataout;
        wire    wire_n10Oii_dataout;
        wire    wire_n10Oil_dataout;
        wire    wire_n10OiO_dataout;
        wire    wire_n10Oli_dataout;
        wire    wire_n10Oll_dataout;
        wire    wire_n10OOl_dataout;
        wire    wire_n10OOO_dataout;
        wire    wire_n1100i_dataout;
        wire    wire_n1100l_dataout;
        wire    wire_n1100O_dataout;
        wire    wire_n1101O_dataout;
        wire    wire_n110ii_dataout;
        wire    wire_n110iO_dataout;
        wire    wire_n110li_dataout;
        wire    wire_n110ll_dataout;
        wire    wire_n110lO_dataout;
        wire    wire_n110Oi_dataout;
        wire    wire_n110Ol_dataout;
        wire    wire_n110OO_dataout;
        wire    wire_n1110O_dataout;
        wire    wire_n1111O_dataout;
        wire    wire_n111ii_dataout;
        wire    wire_n11i0i_dataout;
        wire    wire_n11i1i_dataout;
        wire    wire_n11i1l_dataout;
        wire    wire_n11i1O_dataout;
        wire    wire_n11ill_dataout;
        wire    wire_n11ilO_dataout;
        wire    wire_n11iOl_dataout;
        wire    wire_n11iOO_dataout;
        wire    wire_n11l0i_dataout;
        wire    wire_n11l0l_dataout;
        wire    wire_n11l0O_dataout;
        wire    wire_n11l1l_dataout;
        wire    wire_n11l1O_dataout;
        wire    wire_n11lii_dataout;
        wire    wire_n11lil_dataout;
        wire    wire_n11liO_dataout;
        wire    wire_n11O0i_dataout;
        wire    wire_n11O0l_dataout;
        wire    wire_n1i0ll_dataout;
        wire    wire_n1i0lO_dataout;
        wire    wire_n1i0Oi_dataout;
        wire    wire_n1i0Ol_dataout;
        wire    wire_n1i0OO_dataout;
        wire    wire_n1i1iO_dataout;
        wire    wire_n1i1li_dataout;
        wire    wire_n1i1ll_dataout;
        wire    wire_n1i1Oi_dataout;
        wire    wire_n1i1Ol_dataout;
        wire    wire_n1i1OO_dataout;
        wire    wire_n1ii0i_dataout;
        wire    wire_n1ii0l_dataout;
        wire    wire_n1ii0O_dataout;
        wire    wire_n1ii1i_dataout;
        wire    wire_n1ii1l_dataout;
        wire    wire_n1ii1O_dataout;
        wire    wire_n1iiii_dataout;
        wire    wire_n1iiil_dataout;
        wire    wire_n1iiiO_dataout;
        wire    wire_n1iili_dataout;
        wire    wire_n1iill_dataout;
        wire    wire_n1iilO_dataout;
        wire    wire_n1iiOi_dataout;
        wire    wire_n1iiOl_dataout;
        wire    wire_n1iiOO_dataout;
        wire    wire_n1il0i_dataout;
        wire    wire_n1il0l_dataout;
        wire    wire_n1il0O_dataout;
        wire    wire_n1il1i_dataout;
        wire    wire_n1il1l_dataout;
        wire    wire_n1il1O_dataout;
        wire    wire_n1ilii_dataout;
        wire    wire_n1ilil_dataout;
        wire    wire_n1iliO_dataout;
        wire    wire_n1illi_dataout;
        wire    wire_n1illl_dataout;
        wire    wire_n1illO_dataout;
        wire    wire_n1ilOi_dataout;
        wire    wire_n1ilOl_dataout;
        wire    wire_n1ilOO_dataout;
        wire    wire_n1iO0i_dataout;
        wire    wire_n1iO0l_dataout;
        wire    wire_n1iO0O_dataout;
        wire    wire_n1iO1i_dataout;
        wire    wire_n1iO1l_dataout;
        wire    wire_n1iO1O_dataout;
        wire    wire_n1iOii_dataout;
        wire    wire_n1iOil_dataout;
        wire    wire_n1iOiO_dataout;
        wire    wire_n1iOli_dataout;
        wire    wire_n1iOll_dataout;
        wire    wire_n1iOlO_dataout;
        wire    wire_n1iOOi_dataout;
        wire    wire_n1iOOl_dataout;
        wire    wire_n1iOOO_dataout;
        wire    wire_n1l00i_dataout;
        wire    wire_n1l00l_dataout;
        wire    wire_n1l00O_dataout;
        wire    wire_n1l01i_dataout;
        wire    wire_n1l01l_dataout;
        wire    wire_n1l01O_dataout;
        wire    wire_n1l0ii_dataout;
        wire    wire_n1l0il_dataout;
        wire    wire_n1l0iO_dataout;
        wire    wire_n1l0li_dataout;
        wire    wire_n1l0ll_dataout;
        wire    wire_n1l0lO_dataout;
        wire    wire_n1l0Oi_dataout;
        wire    wire_n1l0Ol_dataout;
        wire    wire_n1l0OO_dataout;
        wire    wire_n1l10i_dataout;
        wire    wire_n1l10l_dataout;
        wire    wire_n1l10O_dataout;
        wire    wire_n1l11i_dataout;
        wire    wire_n1l11l_dataout;
        wire    wire_n1l11O_dataout;
        wire    wire_n1l1ii_dataout;
        wire    wire_n1l1il_dataout;
        wire    wire_n1l1iO_dataout;
        wire    wire_n1l1l_dataout;
        wire    wire_n1l1li_dataout;
        wire    wire_n1l1ll_dataout;
        wire    wire_n1l1lO_dataout;
        wire    wire_n1l1O_dataout;
        wire    wire_n1l1Oi_dataout;
        wire    wire_n1l1Ol_dataout;
        wire    wire_n1l1OO_dataout;
        wire    wire_n1li0i_dataout;
        wire    wire_n1li0l_dataout;
        wire    wire_n1li0O_dataout;
        wire    wire_n1li1i_dataout;
        wire    wire_n1li1l_dataout;
        wire    wire_n1li1O_dataout;
        wire    wire_n1liii_dataout;
        wire    wire_n1liil_dataout;
        wire    wire_n1liiO_dataout;
        wire    wire_n1lili_dataout;
        wire    wire_n1lill_dataout;
        wire    wire_n1lilO_dataout;
        wire    wire_n1liOi_dataout;
        wire    wire_n1liOl_dataout;
        wire    wire_n1liOO_dataout;
        wire    wire_n1ll0i_dataout;
        wire    wire_n1ll0l_dataout;
        wire    wire_n1ll0O_dataout;
        wire    wire_n1ll1i_dataout;
        wire    wire_n1ll1l_dataout;
        wire    wire_n1ll1O_dataout;
        wire    wire_n1llii_dataout;
        wire    wire_n1llil_dataout;
        wire    wire_n1lliO_dataout;
        wire    wire_n1llli_dataout;
        wire    wire_n1llll_dataout;
        wire    wire_n1lllO_dataout;
        wire    wire_n1llOi_dataout;
        wire    wire_n1llOl_dataout;
        wire    wire_n1llOO_dataout;
        wire    wire_n1lO0i_dataout;
        wire    wire_n1lO0l_dataout;
        wire    wire_n1lO0O_dataout;
        wire    wire_n1lO1i_dataout;
        wire    wire_n1lO1l_dataout;
        wire    wire_n1lO1O_dataout;
        wire    wire_n1lOii_dataout;
        wire    wire_n1lOil_dataout;
        wire    wire_n1lOiO_dataout;
        wire    wire_n1lOli_dataout;
        wire    wire_n1lOll_dataout;
        wire    wire_n1lOlO_dataout;
        wire    wire_n1lOOi_dataout;
        wire    wire_n1lOOl_dataout;
        wire    wire_n1lOOO_dataout;
        wire    wire_n1O00i_dataout;
        wire    wire_n1O00l_dataout;
        wire    wire_n1O00O_dataout;
        wire    wire_n1O01i_dataout;
        wire    wire_n1O01l_dataout;
        wire    wire_n1O01O_dataout;
        wire    wire_n1O0ii_dataout;
        wire    wire_n1O0il_dataout;
        wire    wire_n1O0iO_dataout;
        wire    wire_n1O0l_dataout;
        wire    wire_n1O0li_dataout;
        wire    wire_n1O0ll_dataout;
        wire    wire_n1O0lO_dataout;
        wire    wire_n1O0O_dataout;
        wire    wire_n1O0Oi_dataout;
        wire    wire_n1O0Ol_dataout;
        wire    wire_n1O0OO_dataout;
        wire    wire_n1O10i_dataout;
        wire    wire_n1O10l_dataout;
        wire    wire_n1O10O_dataout;
        wire    wire_n1O11i_dataout;
        wire    wire_n1O11l_dataout;
        wire    wire_n1O11O_dataout;
        wire    wire_n1O1ii_dataout;
        wire    wire_n1O1il_dataout;
        wire    wire_n1O1iO_dataout;
        wire    wire_n1O1li_dataout;
        wire    wire_n1O1ll_dataout;
        wire    wire_n1O1lO_dataout;
        wire    wire_n1O1Oi_dataout;
        wire    wire_n1O1Ol_dataout;
        wire    wire_n1O1OO_dataout;
        wire    wire_n1Oi0l_dataout;
        wire    wire_n1Oi1i_dataout;
        wire    wire_n1Oii_dataout;
        wire    wire_n1Oiil_dataout;
        wire    wire_n1Oil_dataout;
        wire    wire_n1Oili_dataout;
        wire    wire_n1Ol0i_dataout;
        wire    wire_n1Ol0l_dataout;
        wire    wire_n1Ol0O_dataout;
        wire    wire_n1Ol1O_dataout;
        wire    wire_n1Olii_dataout;
        wire    wire_n1Olll_dataout;
        wire    wire_n1OllO_dataout;
        wire    wire_n1OlOi_dataout;
        wire    wire_n1OlOl_dataout;
        wire    wire_n1OlOO_dataout;
        wire    wire_ni01il_dataout;
        wire    wire_ni01iO_dataout;
        wire    wire_ni01li_dataout;
        wire    wire_ni01ll_dataout;
        wire    wire_ni0i0i_dataout;
        wire    wire_ni0i1i_dataout;
        wire    wire_ni0i1l_dataout;
        wire    wire_ni0i1O_dataout;
        wire    wire_ni0iii_dataout;
        wire    wire_ni0iil_dataout;
        wire    wire_ni0iiO_dataout;
        wire    wire_ni0ili_dataout;
        wire    wire_ni0ill_dataout;
        wire    wire_ni0ilO_dataout;
        wire    wire_ni0iOi_dataout;
        wire    wire_ni0iOl_dataout;
        wire    wire_ni0iOO_dataout;
        wire    wire_ni0l1i_dataout;
        wire    wire_ni10il_dataout;
        wire    wire_ni10iO_dataout;
        wire    wire_ni110i_dataout;
        wire    wire_ni110l_dataout;
        wire    wire_ni110O_dataout;
        wire    wire_ni111i_dataout;
        wire    wire_ni111l_dataout;
        wire    wire_ni111O_dataout;
        wire    wire_ni11ii_dataout;
        wire    wire_ni11il_dataout;
        wire    wire_ni11iO_dataout;
        wire    wire_ni11li_dataout;
        wire    wire_ni11ll_dataout;
        wire    wire_niii0i_dataout;
        wire    wire_niii1i_dataout;
        wire    wire_niii1O_dataout;
        wire    wire_niiiOi_dataout;
        wire    wire_niiiOl_dataout;
        wire    wire_niiiOO_dataout;
        wire    wire_niil0i_dataout;
        wire    wire_niil0l_dataout;
        wire    wire_niil0O_dataout;
        wire    wire_niil1i_dataout;
        wire    wire_niil1l_dataout;
        wire    wire_niil1O_dataout;
        wire    wire_niilii_dataout;
        wire    wire_niilil_dataout;
        wire    wire_niiliO_dataout;
        wire    wire_niilli_dataout;
        wire    wire_niilll_dataout;
        wire    wire_niillO_dataout;
        wire    wire_niilOi_dataout;
        wire    wire_niilOl_dataout;
        wire    wire_niilOO_dataout;
        wire    wire_niiO0O_dataout;
        wire    wire_niiO1i_dataout;
        wire    wire_niiO1l_dataout;
        wire    wire_niiO1O_dataout;
        wire    wire_niiOii_dataout;
        wire    wire_niiOil_dataout;
        wire    wire_niiOiO_dataout;
        wire    wire_niiOli_dataout;
        wire    wire_niiOll_dataout;
        wire    wire_niiOlO_dataout;
        wire    wire_nil10l_dataout;
        wire    wire_nil10O_dataout;
        wire    wire_nil1iO_dataout;
        wire    wire_nil1li_dataout;
        wire    wire_nill0O_dataout;
        wire    wire_nillii_dataout;
        wire    wire_nillil_dataout;
        wire    wire_nilliO_dataout;
        wire    wire_nillli_dataout;
        wire    wire_nillll_dataout;
        wire    wire_nilllO_dataout;
        wire    wire_nillOi_dataout;
        wire    wire_nillOl_dataout;
        wire    wire_nillOO_dataout;
        wire    wire_nilO0i_dataout;
        wire    wire_nilO0l_dataout;
        wire    wire_nilO0O_dataout;
        wire    wire_nilO1i_dataout;
        wire    wire_nilO1l_dataout;
        wire    wire_nilO1O_dataout;
        wire    wire_nilOii_dataout;
        wire    wire_nilOil_dataout;
        wire    wire_nilOiO_dataout;
        wire    wire_nilOli_dataout;
        wire    wire_niO0ll_dataout;
        wire    wire_niO1iO_dataout;
        wire    wire_niO1l_dataout;
        wire    wire_niO1li_dataout;
        wire    wire_niO1O_dataout;
        wire    wire_niOi0l_dataout;
        wire    wire_niOi1i_dataout;
        wire    wire_niOilO_dataout;
        wire    wire_nl000i_dataout;
        wire    wire_nl00il_dataout;
        wire    wire_nl00iO_dataout;
        wire    wire_nl010O_dataout;
        wire    wire_nl01ii_dataout;
        wire    wire_nl01il_dataout;
        wire    wire_nl01iO_dataout;
        wire    wire_nl01li_dataout;
        wire    wire_nl01ll_dataout;
        wire    wire_nl01lO_dataout;
        wire    wire_nl01Oi_dataout;
        wire    wire_nl01Ol_dataout;
        wire    wire_nl01OO_dataout;
        wire    wire_nl101i_dataout;
        wire    wire_nl101l_dataout;
        wire    wire_nl110i_dataout;
        wire    wire_nl110l_dataout;
        wire    wire_nl110O_dataout;
        wire    wire_nl111l_dataout;
        wire    wire_nl111O_dataout;
        wire    wire_nl11ii_dataout;
        wire    wire_nl11il_dataout;
        wire    wire_nl11iO_dataout;
        wire    wire_nl11li_dataout;
        wire    wire_nl11ll_dataout;
        wire    wire_nl11lO_dataout;
        wire    wire_nl11Oi_dataout;
        wire    wire_nl11Ol_dataout;
        wire    wire_nl11OO_dataout;
        wire    wire_nl1lii_dataout;
        wire    wire_nl1lil_dataout;
        wire    wire_nl1liO_dataout;
        wire    wire_nl1lli_dataout;
        wire    wire_nl1lll_dataout;
        wire    wire_nl1llO_dataout;
        wire    wire_nl1lOi_dataout;
        wire    wire_nl1lOl_dataout;
        wire    wire_nl1lOO_dataout;
        wire    wire_nl1O0i_dataout;
        wire    wire_nl1O0l_dataout;
        wire    wire_nl1O0O_dataout;
        wire    wire_nl1O1i_dataout;
        wire    wire_nl1O1l_dataout;
        wire    wire_nl1O1O_dataout;
        wire    wire_nl1Oii_dataout;
        wire    wire_nli01i_dataout;
        wire    wire_nli01l_dataout;
        wire    wire_nli1ii_dataout;
        wire    wire_nli1il_dataout;
        wire    wire_nli1l_dataout;
        wire    wire_nlii0l_dataout;
        wire    wire_nlii0O_dataout;
        wire    wire_nliiii_dataout;
        wire    wire_nliiil_dataout;
        wire    wire_nliiiO_dataout;
        wire    wire_nliil1l_dataout;
        wire    wire_nliil1O_dataout;
        wire    wire_nliili_dataout;
        wire    wire_nliiO0i_dataout;
        wire    wire_nliiO0l_dataout;
        wire    wire_nliiO0O_dataout;
        wire    wire_nliiO1i_dataout;
        wire    wire_nliiO1l_dataout;
        wire    wire_nliiO1O_dataout;
        wire    wire_nliiOil_dataout;
        wire    wire_nliiOiO_dataout;
        wire    wire_nliiOli_dataout;
        wire    wire_nlil00i_dataout;
        wire    wire_nlil00l_dataout;
        wire    wire_nlil00O_dataout;
        wire    wire_nlil0ii_dataout;
        wire    wire_nlil0il_dataout;
        wire    wire_nlil0iO_dataout;
        wire    wire_nlil0ll_dataout;
        wire    wire_nlil0lO_dataout;
        wire    wire_nlil0Oi_dataout;
        wire    wire_nlil10l_dataout;
        wire    wire_nlil10O_dataout;
        wire    wire_nlilli_dataout;
        wire    wire_nlilll_dataout;
        wire    wire_nlilOO_dataout;
        wire    wire_nliO1i_dataout;
        wire    wire_nliOll_dataout;
        wire    wire_nliOlO_dataout;
        wire    wire_nliOlOl_dataout;
        wire    wire_nliOlOO_dataout;
        wire    wire_nliOO0i_dataout;
        wire    wire_nliOO0O_dataout;
        wire    wire_nliOO1i_dataout;
        wire    wire_nliOOii_dataout;
        wire    wire_nliOOil_dataout;
        wire    wire_nliOOO_dataout;
        wire    wire_nll000i_dataout;
        wire    wire_nll000l_dataout;
        wire    wire_nll000O_dataout;
        wire    wire_nll001O_dataout;
        wire    wire_nll00ii_dataout;
        wire    wire_nll00il_dataout;
        wire    wire_nll00iO_dataout;
        wire    wire_nll00li_dataout;
        wire    wire_nll00ll_dataout;
        wire    wire_nll00lO_dataout;
        wire    wire_nll00Oi_dataout;
        wire    wire_nll00Ol_dataout;
        wire    wire_nll011i_dataout;
        wire    wire_nll011l_dataout;
        wire    wire_nll011O_dataout;
        wire    wire_nll01ii_dataout;
        wire    wire_nll01iO_dataout;
        wire    wire_nll01li_dataout;
        wire    wire_nll01ll_dataout;
        wire    wire_nll01Oi_dataout;
        wire    wire_nll0i1O_dataout;
        wire    wire_nll0iii_dataout;
        wire    wire_nll0iil_dataout;
        wire    wire_nll0llO_dataout;
        wire    wire_nll0lOi_dataout;
        wire    wire_nll0lOl_dataout;
        wire    wire_nll0lOO_dataout;
        wire    wire_nll0O0i_dataout;
        wire    wire_nll0O0l_dataout;
        wire    wire_nll0O0O_dataout;
        wire    wire_nll0O1i_dataout;
        wire    wire_nll0O1l_dataout;
        wire    wire_nll0O1O_dataout;
        wire    wire_nll0Oii_dataout;
        wire    wire_nll0Oil_dataout;
        wire    wire_nll0OiO_dataout;
        wire    wire_nll0Oli_dataout;
        wire    wire_nll0Oll_dataout;
        wire    wire_nll0OlO_dataout;
        wire    wire_nll0OOi_dataout;
        wire    wire_nll0OOl_dataout;
        wire    wire_nll0OOO_dataout;
        wire    wire_nll100i_dataout;
        wire    wire_nll100l_dataout;
        wire    wire_nll100O_dataout;
        wire    wire_nll101i_dataout;
        wire    wire_nll101l_dataout;
        wire    wire_nll101O_dataout;
        wire    wire_nll10ii_dataout;
        wire    wire_nll10il_dataout;
        wire    wire_nll10iO_dataout;
        wire    wire_nll10li_dataout;
        wire    wire_nll10ll_dataout;
        wire    wire_nll10lO_dataout;
        wire    wire_nll10Oi_dataout;
        wire    wire_nll10Ol_dataout;
        wire    wire_nll10OO_dataout;
        wire    wire_nll1i0i_dataout;
        wire    wire_nll1i0l_dataout;
        wire    wire_nll1i0O_dataout;
        wire    wire_nll1i1i_dataout;
        wire    wire_nll1i1l_dataout;
        wire    wire_nll1i1O_dataout;
        wire    wire_nll1iii_dataout;
        wire    wire_nll1iil_dataout;
        wire    wire_nll1iiO_dataout;
        wire    wire_nll1ili_dataout;
        wire    wire_nll1ill_dataout;
        wire    wire_nll1ilO_dataout;
        wire    wire_nll1iOi_dataout;
        wire    wire_nll1iOl_dataout;
        wire    wire_nll1iOO_dataout;
        wire    wire_nll1l0i_dataout;
        wire    wire_nll1l0l_dataout;
        wire    wire_nll1l0O_dataout;
        wire    wire_nll1l1i_dataout;
        wire    wire_nll1l1l_dataout;
        wire    wire_nll1l1O_dataout;
        wire    wire_nll1li_dataout;
        wire    wire_nll1lii_dataout;
        wire    wire_nll1lil_dataout;
        wire    wire_nll1liO_dataout;
        wire    wire_nll1ll_dataout;
        wire    wire_nll1lli_dataout;
        wire    wire_nll1lll_dataout;
        wire    wire_nll1llO_dataout;
        wire    wire_nll1lO_dataout;
        wire    wire_nll1lOi_dataout;
        wire    wire_nll1lOl_dataout;
        wire    wire_nll1lOO_dataout;
        wire    wire_nll1O0i_dataout;
        wire    wire_nll1O0l_dataout;
        wire    wire_nll1O0O_dataout;
        wire    wire_nll1O1i_dataout;
        wire    wire_nll1O1l_dataout;
        wire    wire_nll1O1O_dataout;
        wire    wire_nll1Oi_dataout;
        wire    wire_nll1Oii_dataout;
        wire    wire_nll1Oil_dataout;
        wire    wire_nll1OiO_dataout;
        wire    wire_nll1Oli_dataout;
        wire    wire_nll1Oll_dataout;
        wire    wire_nll1OlO_dataout;
        wire    wire_nll1OOi_dataout;
        wire    wire_nll1OOl_dataout;
        wire    wire_nll1OOO_dataout;
        wire    wire_nlli00i_dataout;
        wire    wire_nlli00l_dataout;
        wire    wire_nlli00O_dataout;
        wire    wire_nlli01i_dataout;
        wire    wire_nlli01l_dataout;
        wire    wire_nlli01O_dataout;
        wire    wire_nlli0i_dataout;
        wire    wire_nlli0ii_dataout;
        wire    wire_nlli0il_dataout;
        wire    wire_nlli0iO_dataout;
        wire    wire_nlli0li_dataout;
        wire    wire_nlli0ll_dataout;
        wire    wire_nlli0lO_dataout;
        wire    wire_nlli0Oi_dataout;
        wire    wire_nlli0Ol_dataout;
        wire    wire_nlli0OO_dataout;
        wire    wire_nlli10i_dataout;
        wire    wire_nlli10l_dataout;
        wire    wire_nlli10O_dataout;
        wire    wire_nlli11i_dataout;
        wire    wire_nlli11l_dataout;
        wire    wire_nlli11O_dataout;
        wire    wire_nlli1ii_dataout;
        wire    wire_nlli1il_dataout;
        wire    wire_nlli1iO_dataout;
        wire    wire_nlli1li_dataout;
        wire    wire_nlli1ll_dataout;
        wire    wire_nlli1lO_dataout;
        wire    wire_nlli1Oi_dataout;
        wire    wire_nlli1Ol_dataout;
        wire    wire_nlli1OO_dataout;
        wire    wire_nllii0i_dataout;
        wire    wire_nllii0l_dataout;
        wire    wire_nllii0O_dataout;
        wire    wire_nllii1i_dataout;
        wire    wire_nllii1l_dataout;
        wire    wire_nllii1O_dataout;
        wire    wire_nlliiii_dataout;
        wire    wire_nlliiil_dataout;
        wire    wire_nlliiiO_dataout;
        wire    wire_nlliili_dataout;
        wire    wire_nlliill_dataout;
        wire    wire_nlliilO_dataout;
        wire    wire_nlliiOi_dataout;
        wire    wire_nlliiOl_dataout;
        wire    wire_nlliiOO_dataout;
        wire    wire_nllil1l_dataout;
        wire    wire_nllil1O_dataout;
        wire    wire_nlliOll_dataout;
        wire    wire_nlliOlO_dataout;
        wire    wire_nlliOOi_dataout;
        wire    wire_nlliOOl_dataout;
        wire    wire_nlliOOO_dataout;
        wire    wire_nlll00i_dataout;
        wire    wire_nlll00l_dataout;
        wire    wire_nlll00O_dataout;
        wire    wire_nlll01i_dataout;
        wire    wire_nlll01l_dataout;
        wire    wire_nlll01O_dataout;
        wire    wire_nlll0ii_dataout;
        wire    wire_nlll0il_dataout;
        wire    wire_nlll0iO_dataout;
        wire    wire_nlll0li_dataout;
        wire    wire_nlll0ll_dataout;
        wire    wire_nlll0lO_dataout;
        wire    wire_nlll0Oi_dataout;
        wire    wire_nlll0Ol_dataout;
        wire    wire_nlll0OO_dataout;
        wire    wire_nlll10i_dataout;
        wire    wire_nlll10l_dataout;
        wire    wire_nlll10O_dataout;
        wire    wire_nlll11i_dataout;
        wire    wire_nlll11l_dataout;
        wire    wire_nlll11O_dataout;
        wire    wire_nlll1i_dataout;
        wire    wire_nlll1ii_dataout;
        wire    wire_nlll1il_dataout;
        wire    wire_nlll1iO_dataout;
        wire    wire_nlll1li_dataout;
        wire    wire_nlll1ll_dataout;
        wire    wire_nlll1lO_dataout;
        wire    wire_nlll1Oi_dataout;
        wire    wire_nlll1Ol_dataout;
        wire    wire_nlll1OO_dataout;
        wire    wire_nllli0i_dataout;
        wire    wire_nllli0l_dataout;
        wire    wire_nllli0O_dataout;
        wire    wire_nllli1i_dataout;
        wire    wire_nllli1l_dataout;
        wire    wire_nllli1O_dataout;
        wire    wire_nllliii_dataout;
        wire    wire_nllliil_dataout;
        wire    wire_nllliiO_dataout;
        wire    wire_nlllili_dataout;
        wire    wire_nlllill_dataout;
        wire    wire_nlllilO_dataout;
        wire    wire_nllliOi_dataout;
        wire    wire_nllliOl_dataout;
        wire    wire_nllliOO_dataout;
        wire    wire_nllll0i_dataout;
        wire    wire_nllll0l_dataout;
        wire    wire_nllll0O_dataout;
        wire    wire_nllll1i_dataout;
        wire    wire_nllll1l_dataout;
        wire    wire_nllll1O_dataout;
        wire    wire_nllllii_dataout;
        wire    wire_nllllil_dataout;
        wire    wire_nlllliO_dataout;
        wire    wire_nllllli_dataout;
        wire    wire_nllllll_dataout;
        wire    wire_nlllllO_dataout;
        wire    wire_nllllOi_dataout;
        wire    wire_nllllOl_dataout;
        wire    wire_nllllOO_dataout;
        wire    wire_nlllO0i_dataout;
        wire    wire_nlllO0l_dataout;
        wire    wire_nlllO0O_dataout;
        wire    wire_nlllO1i_dataout;
        wire    wire_nlllO1l_dataout;
        wire    wire_nlllO1O_dataout;
        wire    wire_nlllOi_dataout;
        wire    wire_nlllOii_dataout;
        wire    wire_nlllOil_dataout;
        wire    wire_nlllOiO_dataout;
        wire    wire_nlllOl_dataout;
        wire    wire_nlllOli_dataout;
        wire    wire_nlllOll_dataout;
        wire    wire_nlllOlO_dataout;
        wire    wire_nlllOO_dataout;
        wire    wire_nlllOOi_dataout;
        wire    wire_nlllOOl_dataout;
        wire    wire_nlllOOO_dataout;
        wire    wire_nllO01i_dataout;
        wire    wire_nllO01l_dataout;
        wire    wire_nllO0i_dataout;
        wire    wire_nllO0l_dataout;
        wire    wire_nllO10i_dataout;
        wire    wire_nllO11i_dataout;
        wire    wire_nllO11l_dataout;
        wire    wire_nllO11O_dataout;
        wire    wire_nllO1i_dataout;
        wire    wire_nllO1l_dataout;
        wire    wire_nllO1O_dataout;
        wire    wire_nllO1OO_dataout;
        wire    wire_nllOi0O_dataout;
        wire    wire_nllOiii_dataout;
        wire    wire_nllOiil_dataout;
        wire    wire_nllOiiO_dataout;
        wire    wire_nllOili_dataout;
        wire    wire_nllOill_dataout;
        wire    wire_nllOilO_dataout;
        wire    wire_nllOiOi_dataout;
        wire    wire_nllOiOl_dataout;
        wire    wire_nllOiOO_dataout;
        wire    wire_nllOl0l_dataout;
        wire    wire_nllOl0O_dataout;
        wire    wire_nllOl1i_dataout;
        wire    wire_nllOl1l_dataout;
        wire    wire_nllOlii_dataout;
        wire    wire_nllOlil_dataout;
        wire    wire_nllOliO_dataout;
        wire    wire_nllOlli_dataout;
        wire    wire_nllOlll_dataout;
        wire    wire_nllOllO_dataout;
        wire    wire_nlO000i_dataout;
        wire    wire_nlO000l_dataout;
        wire    wire_nlO000O_dataout;
        wire    wire_nlO001i_dataout;
        wire    wire_nlO001l_dataout;
        wire    wire_nlO001O_dataout;
        wire    wire_nlO00il_dataout;
        wire    wire_nlO00iO_dataout;
        wire    wire_nlO00li_dataout;
        wire    wire_nlO00ll_dataout;
        wire    wire_nlO00lO_dataout;
        wire    wire_nlO00Oi_dataout;
        wire    wire_nlO00Ol_dataout;
        wire    wire_nlO00OO_dataout;
        wire    wire_nlO010i_dataout;
        wire    wire_nlO010l_dataout;
        wire    wire_nlO010O_dataout;
        wire    wire_nlO011i_dataout;
        wire    wire_nlO011l_dataout;
        wire    wire_nlO011O_dataout;
        wire    wire_nlO01ii_dataout;
        wire    wire_nlO01il_dataout;
        wire    wire_nlO01iO_dataout;
        wire    wire_nlO01li_dataout;
        wire    wire_nlO01ll_dataout;
        wire    wire_nlO01lO_dataout;
        wire    wire_nlO01Oi_dataout;
        wire    wire_nlO01Ol_dataout;
        wire    wire_nlO01OO_dataout;
        wire    wire_nlO0i0i_dataout;
        wire    wire_nlO0i0l_dataout;
        wire    wire_nlO0i0O_dataout;
        wire    wire_nlO0i1i_dataout;
        wire    wire_nlO0i1l_dataout;
        wire    wire_nlO0i1O_dataout;
        wire    wire_nlO0iii_dataout;
        wire    wire_nlO0iil_dataout;
        wire    wire_nlO0iiO_dataout;
        wire    wire_nlO0ili_dataout;
        wire    wire_nlO0ill_dataout;
        wire    wire_nlO0ilO_dataout;
        wire    wire_nlO0iOi_dataout;
        wire    wire_nlO0iOl_dataout;
        wire    wire_nlO0iOO_dataout;
        wire    wire_nlO0l0i_dataout;
        wire    wire_nlO0l0l_dataout;
        wire    wire_nlO0l0O_dataout;
        wire    wire_nlO0l1i_dataout;
        wire    wire_nlO0l1l_dataout;
        wire    wire_nlO0l1O_dataout;
        wire    wire_nlO0lii_dataout;
        wire    wire_nlO0lil_dataout;
        wire    wire_nlO0liO_dataout;
        wire    wire_nlO0Oll_dataout;
        wire    wire_nlO0OlO_dataout;
        wire    wire_nlO0OOl_dataout;
        wire    wire_nlO0OOO_dataout;
        wire    wire_nlO100i_dataout;
        wire    wire_nlO100l_dataout;
        wire    wire_nlO100O_dataout;
        wire    wire_nlO101O_dataout;
        wire    wire_nlO10ii_dataout;
        wire    wire_nlO10il_dataout;
        wire    wire_nlO10iO_dataout;
        wire    wire_nlO10li_dataout;
        wire    wire_nlO10ll_dataout;
        wire    wire_nlO10lO_dataout;
        wire    wire_nlO10Oi_dataout;
        wire    wire_nlO10Ol_dataout;
        wire    wire_nlO10OO_dataout;
        wire    wire_nlO1i0i_dataout;
        wire    wire_nlO1i0l_dataout;
        wire    wire_nlO1i0O_dataout;
        wire    wire_nlO1i1i_dataout;
        wire    wire_nlO1i1l_dataout;
        wire    wire_nlO1i1O_dataout;
        wire    wire_nlO1iii_dataout;
        wire    wire_nlO1iil_dataout;
        wire    wire_nlO1iiO_dataout;
        wire    wire_nlO1ili_dataout;
        wire    wire_nlO1ill_dataout;
        wire    wire_nlO1ilO_dataout;
        wire    wire_nlO1iOi_dataout;
        wire    wire_nlO1iOl_dataout;
        wire    wire_nlO1iOO_dataout;
        wire    wire_nlO1l0i_dataout;
        wire    wire_nlO1l0l_dataout;
        wire    wire_nlO1l0O_dataout;
        wire    wire_nlO1l1i_dataout;
        wire    wire_nlO1l1l_dataout;
        wire    wire_nlO1l1O_dataout;
        wire    wire_nlO1lii_dataout;
        wire    wire_nlO1lil_dataout;
        wire    wire_nlO1liO_dataout;
        wire    wire_nlO1lli_dataout;
        wire    wire_nlO1lll_dataout;
        wire    wire_nlO1llO_dataout;
        wire    wire_nlO1lOi_dataout;
        wire    wire_nlO1lOl_dataout;
        wire    wire_nlO1lOO_dataout;
        wire    wire_nlO1O0i_dataout;
        wire    wire_nlO1O0l_dataout;
        wire    wire_nlO1O0O_dataout;
        wire    wire_nlO1O1i_dataout;
        wire    wire_nlO1O1l_dataout;
        wire    wire_nlO1O1O_dataout;
        wire    wire_nlO1Oii_dataout;
        wire    wire_nlO1Oil_dataout;
        wire    wire_nlO1OiO_dataout;
        wire    wire_nlO1Oli_dataout;
        wire    wire_nlO1Oll_dataout;
        wire    wire_nlO1OlO_dataout;
        wire    wire_nlO1OOi_dataout;
        wire    wire_nlO1OOl_dataout;
        wire    wire_nlO1OOO_dataout;
        wire    wire_nlOi00i_dataout;
        wire    wire_nlOi00l_dataout;
        wire    wire_nlOi00O_dataout;
        wire    wire_nlOi0ii_dataout;
        wire    wire_nlOi0il_dataout;
        wire    wire_nlOi0iO_dataout;
        wire    wire_nlOi0li_dataout;
        wire    wire_nlOi0ll_dataout;
        wire    wire_nlOi10i_dataout;
        wire    wire_nlOi10l_dataout;
        wire    wire_nlOi10O_dataout;
        wire    wire_nlOi11O_dataout;
        wire    wire_nlOi1O_dataout;
        wire    wire_nlOiiOl_dataout;
        wire    wire_nlOiiOO_dataout;
        wire    wire_nlOil1i_dataout;
        wire    wire_nlOl00i_dataout;
        wire    wire_nlOl00l_dataout;
        wire    wire_nlOl00O_dataout;
        wire    wire_nlOl01i_dataout;
        wire    wire_nlOl01l_dataout;
        wire    wire_nlOl01O_dataout;
        wire    wire_nlOl0i_dataout;
        wire    wire_nlOl0ii_dataout;
        wire    wire_nlOl0il_dataout;
        wire    wire_nlOl0iO_dataout;
        wire    wire_nlOl0l_dataout;
        wire    wire_nlOl0li_dataout;
        wire    wire_nlOl0ll_dataout;
        wire    wire_nlOl0lO_dataout;
        wire    wire_nlOl0O_dataout;
        wire    wire_nlOl0Oi_dataout;
        wire    wire_nlOl0Ol_dataout;
        wire    wire_nlOl0OO_dataout;
        wire    wire_nlOl10l_dataout;
        wire    wire_nlOl10O_dataout;
        wire    wire_nlOl1i_dataout;
        wire    wire_nlOl1ii_dataout;
        wire    wire_nlOl1il_dataout;
        wire    wire_nlOl1iO_dataout;
        wire    wire_nlOl1l_dataout;
        wire    wire_nlOl1li_dataout;
        wire    wire_nlOl1ll_dataout;
        wire    wire_nlOl1lO_dataout;
        wire    wire_nlOl1O_dataout;
        wire    wire_nlOl1Oi_dataout;
        wire    wire_nlOl1Ol_dataout;
        wire    wire_nlOl1OO_dataout;
        wire    wire_nlOli0i_dataout;
        wire    wire_nlOli0l_dataout;
        wire    wire_nlOli0O_dataout;
        wire    wire_nlOli1i_dataout;
        wire    wire_nlOli1l_dataout;
        wire    wire_nlOli1O_dataout;
        wire    wire_nlOlii_dataout;
        wire    wire_nlOliii_dataout;
        wire    wire_nlOliil_dataout;
        wire    wire_nlOlil_dataout;
        wire    wire_nlOlilO_dataout;
        wire    wire_nlOliO_dataout;
        wire    wire_nlOliOi_dataout;
        wire    wire_nlOlli_dataout;
        wire    wire_nlOllii_dataout;
        wire    wire_nlOllil_dataout;
        wire    wire_nlOlliO_dataout;
        wire    wire_nlOlll_dataout;
        wire    wire_nlOllli_dataout;
        wire    wire_nlOllll_dataout;
        wire    wire_nlOlllO_dataout;
        wire    wire_nlOllO_dataout;
        wire    wire_nlOllOi_dataout;
        wire    wire_nlOllOl_dataout;
        wire    wire_nlOllOO_dataout;
        wire    wire_nlOlO0i_dataout;
        wire    wire_nlOlO0l_dataout;
        wire    wire_nlOlO0O_dataout;
        wire    wire_nlOlO1i_dataout;
        wire    wire_nlOlO1l_dataout;
        wire    wire_nlOlO1O_dataout;
        wire    wire_nlOlOi_dataout;
        wire    wire_nlOlOii_dataout;
        wire    wire_nlOlOil_dataout;
        wire    wire_nlOlOiO_dataout;
        wire    wire_nlOlOl_dataout;
        wire    wire_nlOlOli_dataout;
        wire    wire_nlOlOOi_dataout;
        wire    wire_nlOO00l_dataout;
        wire    wire_nlOO00O_dataout;
        wire    wire_nlOO0ii_dataout;
        wire    wire_nlOO0il_dataout;
        wire    wire_nlOO0iO_dataout;
        wire    wire_nlOO0li_dataout;
        wire    wire_nlOO0ll_dataout;
        wire    wire_nlOO0lO_dataout;
        wire    wire_nlOO0Oi_dataout;
        wire    wire_nlOO0Ol_dataout;
        wire    wire_nlOO0OO_dataout;
        wire    wire_nlOO11O_dataout;
        wire    wire_nlOOi0i_dataout;
        wire    wire_nlOOi0l_dataout;
        wire    wire_nlOOi0O_dataout;
        wire    wire_nlOOi1i_dataout;
        wire    wire_nlOOi1l_dataout;
        wire    wire_nlOOi1O_dataout;
        wire    wire_nlOOiii_dataout;
        wire    wire_nlOOiil_dataout;
        wire    wire_nlOOiiO_dataout;
        wire    wire_nlOOili_dataout;
        wire    wire_nlOOill_dataout;
        wire    wire_nlOOilO_dataout;
        wire    wire_nlOOiOi_dataout;
        wire    wire_nlOOiOl_dataout;
        wire    wire_nlOOiOO_dataout;
        wire    wire_nlOOl0i_dataout;
        wire    wire_nlOOl0l_dataout;
        wire    wire_nlOOl0O_dataout;
        wire    wire_nlOOl1i_dataout;
        wire    wire_nlOOl1l_dataout;
        wire    wire_nlOOl1O_dataout;
        wire    wire_nlOOlii_dataout;
        wire    wire_nlOOlil_dataout;
        wire    wire_nlOOliO_dataout;
        wire    wire_nlOOlli_dataout;
        wire    wire_nlOOlll_dataout;
        wire    wire_nlOOllO_dataout;
        wire    wire_nlOOlOi_dataout;
        wire    wire_nlOOlOl_dataout;
        wire    wire_nlOOO0O_dataout;
        wire    wire_nlOOO1i_dataout;
        wire    wire_nlOOO1l_dataout;
        wire    wire_nlOOOii_dataout;
        wire    wire_nlOOOl_dataout;
        wire    wire_nlOOOO_dataout;
        wire    wire_nlOOOOl_dataout;
        wire  [6:0]   wire_n00i1l_o;
        wire  [3:0]   wire_n00ii_o;
        wire  [1:0]   wire_n00O0i_o;
        wire  [3:0]   wire_n01li_o;
        wire  [3:0]   wire_n0i0ii_o;
        wire  [3:0]   wire_n0il1i_o;
        wire  [4:0]   wire_n0ilOl_o;
        wire  [4:0]   wire_n0iO0l_o;
        wire  [2:0]   wire_n100O_o;
        wire  [0:0]   wire_n111i_o;
        wire  [2:0]   wire_n1l0i_o;
        wire  [4:0]   wire_n1OiO_o;
        wire  [3:0]   wire_ni01lO_o;
        wire  [3:0]   wire_ni0i0l_o;
        wire  [4:0]   wire_ni0l1O_o;
        wire  [4:0]   wire_ni0lil_o;
        wire  [6:0]   wire_niiO0i_o;
        wire  [5:0]   wire_nliiOii_o;
        wire  [2:0]   wire_nliiOll_o;
        wire  [5:0]   wire_nlil0li_o;
        wire  [2:0]   wire_nlil0Ol_o;
        wire  [2:0]   wire_nll00OO_o;
        wire  [20:0]   wire_nll010i_o;
        wire  [7:0]   wire_nllO0O_o;
        wire  [20:0]   wire_nllO10l_o;
        wire  [1:0]   wire_nllOl1O_o;
        wire  [1:0]   wire_nllOlOi_o;
        wire  [1:0]   wire_n010Oi_o;
        wire  [1:0]   wire_n0lilO_o;
        wire  [1:0]   wire_niO0lO_o;
        wire  [1:0]   wire_niOi0O_o;
        wire  wire_n00i1O_o;
        wire  wire_n0i0il_o;
        wire  wire_n0il1l_o;
        wire  wire_n0iOiO_o;
        wire  wire_n0l1li_o;
        wire  wire_ni01Oi_o;
        wire  wire_ni0i0O_o;
        wire  wire_ni0llO_o;
        wire  wire_ni0OOl_o;
        wire  wire_niiO0l_o;
        wire  wire_nlll1O_o;
        wire  wire_nl100i_o;
        wire  wire_nl100l_o;
        wire  wire_nl100O_o;
        wire  wire_nl101O_o;
        wire  wire_nl10ii_o;
        wire  wire_nl10il_o;
        wire  wire_nl10iO_o;
        wire  wire_nl10li_o;
        wire  wire_nl10ll_o;
        wire  wire_nl10lO_o;
        wire  wire_nl10Oi_o;
        wire  wire_nl10Ol_o;
        wire  wire_nl10OO_o;
        wire  wire_nl1i1i_o;
        wire  wire_nl1i1l_o;
        wire  wire_nl1i1O_o;
        wire  wire_n00ill_o;
        wire  wire_n00iOi_o;
        wire  wire_n00iOO_o;
        wire  wire_n00l1l_o;
        wire  wire_n1101i_o;
        wire  wire_n1110i_o;
        wire  wire_n1111i_o;
        wire  wire_n111il_o;
        wire  wire_n111li_o;
        wire  wire_n111lO_o;
        wire  wire_n111Ol_o;
        wire  wire_n1Oi0O_o;
        wire  wire_n1OiiO_o;
        wire  wire_n1Oill_o;
        wire  wire_n1OiOl_o;
        wire  wire_n1Ol1i_o;
        wire  wire_ni101l_o;
        wire  wire_ni11lO_o;
        wire  wire_ni11Oi_o;
        wire  wire_ni11OO_o;
        wire  wire_niiOOi_o;
        wire  wire_niiOOO_o;
        wire  wire_nil10i_o;
        wire  wire_nil11l_o;
        wire  wire_nlO0lli_o;
        wire  wire_nlO0llO_o;
        wire  wire_nlO0lOl_o;
        wire  wire_nlO0O0l_o;
        wire  wire_nlO0O1i_o;
        wire  wire_nlO0O1O_o;
        wire  wire_nlO0Oii_o;
        wire  wire_nlO0OiO_o;
        wire  wire_nlOi0i_o;
        wire  wire_nlOi0O_o;
        wire  wire_nlOiil_o;
        wire  wire_nlOili_o;
        wire  wire_nlOilO_o;
        wire  wire_nlOOO0i_o;
        wire  wire_nlOOOil_o;
        wire  wire_nlOOOli_o;
        wire  wire_nlOOOlO_o;
        wire  wire_nlOOOOO_o;
        wire  nl0O00i;
        wire  nl0O00l;
        wire  nl0O00O;
        wire  nl0O01i;
        wire  nl0O01l;
        wire  nl0O01O;
        wire  nl0O0ii;
        wire  nl0O0il;
        wire  nl0O0iO;
        wire  nl0O0li;
        wire  nl0O0ll;
        wire  nl0O0lO;
        wire  nl0O0Oi;
        wire  nl0O0Ol;
        wire  nl0O0OO;
        wire  nl0O10i;
        wire  nl0O10l;
        wire  nl0O10O;
        wire  nl0O11O;
        wire  nl0O1ii;
        wire  nl0O1il;
        wire  nl0O1iO;
        wire  nl0O1li;
        wire  nl0O1ll;
        wire  nl0O1lO;
        wire  nl0O1Oi;
        wire  nl0O1Ol;
        wire  nl0O1OO;
        wire  nl0Oi0i;
        wire  nl0Oi0l;
        wire  nl0Oi0O;
        wire  nl0Oi1i;
        wire  nl0Oi1l;
        wire  nl0Oi1O;
        wire  nl0Oiii;
        wire  nl0Oiil;
        wire  nl0OiiO;
        wire  nl0Oili;
        wire  nl0Oill;
        wire  nl0OilO;
        wire  nl0OiOi;
        wire  nl0OiOl;
        wire  nl0OiOO;
        wire  nl0Ol0i;
        wire  nl0Ol0l;
        wire  nl0Ol0O;
        wire  nl0Ol1i;
        wire  nl0Ol1l;
        wire  nl0Ol1O;
        wire  nl0Olii;
        wire  nl0Olil;
        wire  nl0OliO;
        wire  nl0Olli;
        wire  nl0Olll;
        wire  nl0OllO;
        wire  nl0OlOi;
        wire  nl0OlOl;
        wire  nl0OlOO;
        wire  nl0OO0i;
        wire  nl0OO0l;
        wire  nl0OO0O;
        wire  nl0OO1i;
        wire  nl0OO1l;
        wire  nl0OO1O;
        wire  nl0OOii;
        wire  nl0OOil;
        wire  nl0OOiO;
        wire  nl0OOli;
        wire  nl0OOll;
        wire  nl0OOlO;
        wire  nl0OOOi;
        wire  nl0OOOl;
        wire  nl0OOOO;
        wire  nli000l;
        wire  nli000O;
        wire  nli001i;
        wire  nli001l;
        wire  nli00ii;
        wire  nli00il;
        wire  nli00iO;
        wire  nli00li;
        wire  nli00ll;
        wire  nli00lO;
        wire  nli00Oi;
        wire  nli00Ol;
        wire  nli00OO;
        wire  nli010l;
        wire  nli010O;
        wire  nli011i;
        wire  nli01ii;
        wire  nli01il;
        wire  nli01iO;
        wire  nli01li;
        wire  nli01ll;
        wire  nli01lO;
        wire  nli01Oi;
        wire  nli01Ol;
        wire  nli01OO;
        wire  nli0i0i;
        wire  nli0i0l;
        wire  nli0i0O;
        wire  nli0i1i;
        wire  nli0i1l;
        wire  nli0i1O;
        wire  nli0iii;
        wire  nli0iil;
        wire  nli0iiO;
        wire  nli0ili;
        wire  nli0ill;
        wire  nli0ilO;
        wire  nli0iOi;
        wire  nli0iOl;
        wire  nli0iOO;
        wire  nli0l0O;
        wire  nli0l1i;
        wire  nli0l1l;
        wire  nli0l1O;
        wire  nli0lOO;
        wire  nli0O0O;
        wire  nli0O1i;
        wire  nli0Oll;
        wire  nli100i;
        wire  nli100l;
        wire  nli100O;
        wire  nli101i;
        wire  nli101l;
        wire  nli101O;
        wire  nli10ii;
        wire  nli10il;
        wire  nli10iO;
        wire  nli10li;
        wire  nli10ll;
        wire  nli10lO;
        wire  nli10Oi;
        wire  nli10Ol;
        wire  nli10OO;
        wire  nli110i;
        wire  nli110l;
        wire  nli110O;
        wire  nli111i;
        wire  nli111l;
        wire  nli111O;
        wire  nli11ii;
        wire  nli11il;
        wire  nli11iO;
        wire  nli11li;
        wire  nli11ll;
        wire  nli11lO;
        wire  nli11Oi;
        wire  nli11Ol;
        wire  nli11OO;
        wire  nli1i0i;
        wire  nli1i0l;
        wire  nli1i0O;
        wire  nli1i1i;
        wire  nli1i1l;
        wire  nli1i1O;
        wire  nli1iii;
        wire  nli1iil;
        wire  nli1iiO;
        wire  nli1ili;
        wire  nli1ill;
        wire  nli1ilO;
        wire  nli1iOi;
        wire  nli1iOl;
        wire  nli1iOO;
        wire  nli1l0i;
        wire  nli1l0l;
        wire  nli1l0O;
        wire  nli1l1i;
        wire  nli1l1l;
        wire  nli1l1O;
        wire  nli1lii;
        wire  nli1lil;
        wire  nli1liO;
        wire  nli1lli;
        wire  nli1lll;
        wire  nli1lOl;
        wire  nli1lOO;
        wire  nli1O0i;
        wire  nli1O0l;
        wire  nli1O1i;
        wire  nli1O1l;
        wire  nli1O1O;
        wire  nli1OiO;
        wire  nli1Oli;
        wire  nli1Oll;
        wire  nli1OOO;
        wire  nlii00i;
        wire  nlii0iO;
        wire  nlii0li;
        wire  nlii0ll;
        wire  nlii0lO;
        wire  nlii11i;
        wire  nlii1il;
        wire  nlii1Oi;
 
        altera_std_synchronizer   n1i10i
        (
        .clk(wire_nl00l_clkout),
        .din(nll0i1l),
        .dout(wire_n1i10i_dout),
        .reset_n((~ nlii0li)));
        defparam
                n1i10i.depth = 3;
        altera_std_synchronizer   n1i10O
        (
        .clk(wire_nl00l_clkout),
        .din(nlilOl),
        .dout(wire_n1i10O_dout),
        .reset_n((~ nlii0li)));
        defparam
                n1i10O.depth = 3;
        altera_std_synchronizer   n1i11O
        (
        .clk(wire_nl00l_clkout),
        .din(nll001l),
        .dout(wire_n1i11O_dout),
        .reset_n((~ nlii0li)));
        defparam
                n1i11O.depth = 3;
        altera_std_synchronizer   n1i1ii
        (
        .clk(wire_nl00l_clkout),
        .din(nliO0l),
        .dout(wire_n1i1ii_dout),
        .reset_n((~ nlii0li)));
        defparam
                n1i1ii.depth = 3;
        altera_std_synchronizer   nlili0O
        (
        .clk(wire_nl0ii_clkout),
        .din(nliO0l),
        .dout(wire_nlili0O_dout),
        .reset_n((~ nlili1O)));
        defparam
                nlili0O.depth = 3;
        altera_std_synchronizer   nliliii
        (
        .clk(wire_nl0ii_clkout),
        .din(nliOii),
        .dout(wire_nliliii_dout),
        .reset_n((~ nlili1O)));
        defparam
                nliliii.depth = 3;
        altera_std_synchronizer   nliliil
        (
        .clk(wire_nl0ii_clkout),
        .din(nlilOl),
        .dout(wire_nliliil_dout),
        .reset_n((~ nlili1O)));
        defparam
                nliliil.depth = 3;
        altera_std_synchronizer   nliliiO
        (
        .clk(wire_nl0ii_clkout),
        .din(nliOil),
        .dout(wire_nliliiO_dout),
        .reset_n((~ nlili1O)));
        defparam
                nliliiO.depth = 3;
        altera_std_synchronizer_bundle   n01ill
        (
        .clk(wire_nl00l_clkout),
        .din({nl010i, nl011O}),
        .dout(wire_n01ill_dout),
        .reset_n((~ nlii0ll)));
        defparam
                n01ill.depth = 3,
                n01ill.width = 2;
        altera_std_synchronizer_bundle   n01ilO
        (
        .clk(wire_nl0ii_clkout),
        .din({nl010i, nl011O}),
        .dout(wire_n01ilO_dout),
        .reset_n((~ nlili1O)));
        defparam
                n01ilO.depth = 3,
                n01ilO.width = 2;
        altera_std_synchronizer_bundle   n1i10l
        (
        .clk(wire_nl00l_clkout),
        .din({nll0lli, nll0liO, nll0lil, nll0lii, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0i0O}),
        .dout(wire_n1i10l_dout),
        .reset_n((~ nlii0li)));
        defparam
                n1i10l.depth = 3,
                n1i10l.width = 16;
        altpll   nl01O
        (
        .activeclock(),
        .areset(gxb_pwrdn_in),
        .clk(wire_nl01O_clk),
        .clkbad(),
        .clkloss(),
        .enable0(),
        .enable1(),
        .extclk(),
        .fbout(),
        .fref(wire_nl01O_fref),
        .icdrclk(wire_nl01O_icdrclk),
        .inclk({1'b0, ref_clk}),
        .locked(wire_nl01O_locked),
        .phasedone(),
        .scandataout(),
        .scandone(),
        .sclkout0(),
        .sclkout1(),
        .vcooverrange(),
        .vcounderrange(),
        .clkena(),
        .clkswitch(),
        .configupdate(),
        .extclkena(),
        .fbin(),
        .pfdena(),
        .phasecounterselect(),
        .phasestep(),
        .phaseupdown(),
        .pllena(),
        .scanaclr(),
        .scanclk(),
        .scanclkena(),
        .scandata(),
        .scanread(),
        .scanwrite()
        );
        defparam
                nl01O.bandwidth = 0,
                nl01O.bandwidth_type = "HIGH",
                nl01O.c0_high = 0,
                nl01O.c0_initial = 0,
                nl01O.c0_low = 0,
                nl01O.c0_mode = "BYPASS",
                nl01O.c0_ph = 0,
                nl01O.c0_test_source = 5,
                nl01O.c1_high = 0,
                nl01O.c1_initial = 0,
                nl01O.c1_low = 0,
                nl01O.c1_mode = "BYPASS",
                nl01O.c1_ph = 0,
                nl01O.c1_test_source = 5,
                nl01O.c1_use_casc_in = "OFF",
                nl01O.c2_high = 0,
                nl01O.c2_initial = 0,
                nl01O.c2_low = 0,
                nl01O.c2_mode = "BYPASS",
                nl01O.c2_ph = 0,
                nl01O.c2_test_source = 5,
                nl01O.c2_use_casc_in = "OFF",
                nl01O.c3_high = 0,
                nl01O.c3_initial = 0,
                nl01O.c3_low = 0,
                nl01O.c3_mode = "BYPASS",
                nl01O.c3_ph = 0,
                nl01O.c3_test_source = 5,
                nl01O.c3_use_casc_in = "OFF",
                nl01O.c4_high = 0,
                nl01O.c4_initial = 0,
                nl01O.c4_low = 0,
                nl01O.c4_mode = "BYPASS",
                nl01O.c4_ph = 0,
                nl01O.c4_test_source = 5,
                nl01O.c4_use_casc_in = "OFF",
                nl01O.c5_high = 0,
                nl01O.c5_initial = 0,
                nl01O.c5_low = 0,
                nl01O.c5_mode = "BYPASS",
                nl01O.c5_ph = 0,
                nl01O.c5_test_source = 5,
                nl01O.c5_use_casc_in = "OFF",
                nl01O.c6_high = 0,
                nl01O.c6_initial = 0,
                nl01O.c6_low = 0,
                nl01O.c6_mode = "BYPASS",
                nl01O.c6_ph = 0,
                nl01O.c6_test_source = 5,
                nl01O.c6_use_casc_in = "OFF",
                nl01O.c7_high = 0,
                nl01O.c7_initial = 0,
                nl01O.c7_low = 0,
                nl01O.c7_mode = "BYPASS",
                nl01O.c7_ph = 0,
                nl01O.c7_test_source = 5,
                nl01O.c7_use_casc_in = "OFF",
                nl01O.c8_high = 0,
                nl01O.c8_initial = 0,
                nl01O.c8_low = 0,
                nl01O.c8_mode = "BYPASS",
                nl01O.c8_ph = 0,
                nl01O.c8_test_source = 5,
                nl01O.c8_use_casc_in = "OFF",
                nl01O.c9_high = 0,
                nl01O.c9_initial = 0,
                nl01O.c9_low = 0,
                nl01O.c9_mode = "BYPASS",
                nl01O.c9_ph = 0,
                nl01O.c9_test_source = 5,
                nl01O.c9_use_casc_in = "OFF",
                nl01O.charge_pump_current = 2,
                nl01O.charge_pump_current_bits = 9999,
                nl01O.clk0_counter = "G0",
                nl01O.clk0_divide_by = 1,
                nl01O.clk0_duty_cycle = 50,
                nl01O.clk0_multiply_by = 5,
                nl01O.clk0_output_frequency = 0,
                nl01O.clk0_phase_shift = "0",
                nl01O.clk0_time_delay = "0",
                nl01O.clk0_use_even_counter_mode = "OFF",
                nl01O.clk0_use_even_counter_value = "OFF",
                nl01O.clk1_counter = "G0",
                nl01O.clk1_divide_by = 5,
                nl01O.clk1_duty_cycle = 50,
                nl01O.clk1_multiply_by = 5,
                nl01O.clk1_output_frequency = 0,
                nl01O.clk1_phase_shift = "0",
                nl01O.clk1_time_delay = "0",
                nl01O.clk1_use_even_counter_mode = "OFF",
                nl01O.clk1_use_even_counter_value = "OFF",
                nl01O.clk2_counter = "G0",
                nl01O.clk2_divide_by = 5,
                nl01O.clk2_duty_cycle = 20,
                nl01O.clk2_multiply_by = 5,
                nl01O.clk2_output_frequency = 0,
                nl01O.clk2_phase_shift = "0",
                nl01O.clk2_time_delay = "0",
                nl01O.clk2_use_even_counter_mode = "OFF",
                nl01O.clk2_use_even_counter_value = "OFF",
                nl01O.clk3_counter = "G0",
                nl01O.clk3_divide_by = 1,
                nl01O.clk3_duty_cycle = 50,
                nl01O.clk3_multiply_by = 1,
                nl01O.clk3_phase_shift = "0",
                nl01O.clk3_time_delay = "0",
                nl01O.clk3_use_even_counter_mode = "OFF",
                nl01O.clk3_use_even_counter_value = "OFF",
                nl01O.clk4_counter = "G0",
                nl01O.clk4_divide_by = 1,
                nl01O.clk4_duty_cycle = 50,
                nl01O.clk4_multiply_by = 1,
                nl01O.clk4_phase_shift = "0",
                nl01O.clk4_time_delay = "0",
                nl01O.clk4_use_even_counter_mode = "OFF",
                nl01O.clk4_use_even_counter_value = "OFF",
                nl01O.clk5_counter = "G0",
                nl01O.clk5_divide_by = 1,
                nl01O.clk5_duty_cycle = 50,
                nl01O.clk5_multiply_by = 1,
                nl01O.clk5_phase_shift = "0",
                nl01O.clk5_time_delay = "0",
                nl01O.clk5_use_even_counter_mode = "OFF",
                nl01O.clk5_use_even_counter_value = "OFF",
                nl01O.clk6_counter = "E0",
                nl01O.clk6_divide_by = 0,
                nl01O.clk6_duty_cycle = 50,
                nl01O.clk6_multiply_by = 0,
                nl01O.clk6_phase_shift = "0",
                nl01O.clk6_use_even_counter_mode = "OFF",
                nl01O.clk6_use_even_counter_value = "OFF",
                nl01O.clk7_counter = "E1",
                nl01O.clk7_divide_by = 0,
                nl01O.clk7_duty_cycle = 50,
                nl01O.clk7_multiply_by = 0,
                nl01O.clk7_phase_shift = "0",
                nl01O.clk7_use_even_counter_mode = "OFF",
                nl01O.clk7_use_even_counter_value = "OFF",
                nl01O.clk8_counter = "E2",
                nl01O.clk8_divide_by = 0,
                nl01O.clk8_duty_cycle = 50,
                nl01O.clk8_multiply_by = 0,
                nl01O.clk8_phase_shift = "0",
                nl01O.clk8_use_even_counter_mode = "OFF",
                nl01O.clk8_use_even_counter_value = "OFF",
                nl01O.clk9_counter = "E3",
                nl01O.clk9_divide_by = 0,
                nl01O.clk9_duty_cycle = 50,
                nl01O.clk9_multiply_by = 0,
                nl01O.clk9_phase_shift = "0",
                nl01O.clk9_use_even_counter_mode = "OFF",
                nl01O.clk9_use_even_counter_value = "OFF",
                nl01O.compensate_clock = "CLK0",
                nl01O.down_spread = "0",
                nl01O.dpa_divide_by = 1,
                nl01O.dpa_divider = 0,
                nl01O.dpa_multiply_by = 5,
                nl01O.e0_high = 1,
                nl01O.e0_initial = 1,
                nl01O.e0_low = 1,
                nl01O.e0_mode = "BYPASS",
                nl01O.e0_ph = 0,
                nl01O.e0_time_delay = 0,
                nl01O.e1_high = 1,
                nl01O.e1_initial = 1,
                nl01O.e1_low = 1,
                nl01O.e1_mode = "BYPASS",
                nl01O.e1_ph = 0,
                nl01O.e1_time_delay = 0,
                nl01O.e2_high = 1,
                nl01O.e2_initial = 1,
                nl01O.e2_low = 1,
                nl01O.e2_mode = "BYPASS",
                nl01O.e2_ph = 0,
                nl01O.e2_time_delay = 0,
                nl01O.e3_high = 1,
                nl01O.e3_initial = 1,
                nl01O.e3_low = 1,
                nl01O.e3_mode = "BYPASS",
                nl01O.e3_ph = 0,
                nl01O.e3_time_delay = 0,
                nl01O.enable0_counter = "L0",
                nl01O.enable1_counter = "L0",
                nl01O.enable_switch_over_counter = "OFF",
                nl01O.extclk0_counter = "E0",
                nl01O.extclk0_divide_by = 1,
                nl01O.extclk0_duty_cycle = 50,
                nl01O.extclk0_multiply_by = 1,
                nl01O.extclk0_phase_shift = "0",
                nl01O.extclk0_time_delay = "0",
                nl01O.extclk1_counter = "E1",
                nl01O.extclk1_divide_by = 1,
                nl01O.extclk1_duty_cycle = 50,
                nl01O.extclk1_multiply_by = 1,
                nl01O.extclk1_phase_shift = "0",
                nl01O.extclk1_time_delay = "0",
                nl01O.extclk2_counter = "E2",
                nl01O.extclk2_divide_by = 1,
                nl01O.extclk2_duty_cycle = 50,
                nl01O.extclk2_multiply_by = 1,
                nl01O.extclk2_phase_shift = "0",
                nl01O.extclk2_time_delay = "0",
                nl01O.extclk3_counter = "E3",
                nl01O.extclk3_divide_by = 1,
                nl01O.extclk3_duty_cycle = 50,
                nl01O.extclk3_multiply_by = 1,
                nl01O.extclk3_phase_shift = "0",
                nl01O.extclk3_time_delay = "0",
                nl01O.feedback_source = "EXTCLK0",
                nl01O.g0_high = 1,
                nl01O.g0_initial = 1,
                nl01O.g0_low = 1,
                nl01O.g0_mode = "BYPASS",
                nl01O.g0_ph = 0,
                nl01O.g0_time_delay = 0,
                nl01O.g1_high = 1,
                nl01O.g1_initial = 1,
                nl01O.g1_low = 1,
                nl01O.g1_mode = "BYPASS",
                nl01O.g1_ph = 0,
                nl01O.g1_time_delay = 0,
                nl01O.g2_high = 1,
                nl01O.g2_initial = 1,
                nl01O.g2_low = 1,
                nl01O.g2_mode = "BYPASS",
                nl01O.g2_ph = 0,
                nl01O.g2_time_delay = 0,
                nl01O.g3_high = 1,
                nl01O.g3_initial = 1,
                nl01O.g3_low = 1,
                nl01O.g3_mode = "BYPASS",
                nl01O.g3_ph = 0,
                nl01O.g3_time_delay = 0,
                nl01O.gate_lock_counter = 0,
                nl01O.gate_lock_signal = "NO",
                nl01O.inclk0_input_frequency = 8000,
                nl01O.inclk1_input_frequency = 0,
                nl01O.intended_device_family = "CYCLONEIVGX",
                nl01O.invalid_lock_multiplier = 5,
                nl01O.l0_high = 1,
                nl01O.l0_initial = 1,
                nl01O.l0_low = 1,
                nl01O.l0_mode = "BYPASS",
                nl01O.l0_ph = 0,
                nl01O.l0_time_delay = 0,
                nl01O.l1_high = 1,
                nl01O.l1_initial = 1,
                nl01O.l1_low = 1,
                nl01O.l1_mode = "BYPASS",
                nl01O.l1_ph = 0,
                nl01O.l1_time_delay = 0,
                nl01O.lock_high = 1,
                nl01O.lock_low = 1,
                nl01O.lock_window_ui = " 0.05",
                nl01O.loop_filter_c = 5,
                nl01O.loop_filter_c_bits = 9999,
                nl01O.loop_filter_r = " 1.000000",
                nl01O.loop_filter_r_bits = 9999,
                nl01O.m = 0,
                nl01O.m2 = 1,
                nl01O.m_initial = 0,
                nl01O.m_ph = 0,
                nl01O.m_test_source = 5,
                nl01O.m_time_delay = 0,
                nl01O.n = 1,
                nl01O.n2 = 1,
                nl01O.n_time_delay = 0,
                nl01O.operation_mode = "no_compensation",
                nl01O.pfd_max = 0,
                nl01O.pfd_min = 0,
                nl01O.pll_type = "AUTO",
                nl01O.port_activeclock = "PORT_CONNECTIVITY",
                nl01O.port_areset = "PORT_CONNECTIVITY",
                nl01O.port_clk0 = "PORT_CONNECTIVITY",
                nl01O.port_clk1 = "PORT_CONNECTIVITY",
                nl01O.port_clk2 = "PORT_CONNECTIVITY",
                nl01O.port_clk3 = "PORT_CONNECTIVITY",
                nl01O.port_clk4 = "PORT_CONNECTIVITY",
                nl01O.port_clk5 = "PORT_CONNECTIVITY",
                nl01O.port_clk6 = "PORT_UNUSED",
                nl01O.port_clk7 = "PORT_UNUSED",
                nl01O.port_clk8 = "PORT_UNUSED",
                nl01O.port_clk9 = "PORT_UNUSED",
                nl01O.port_clkbad0 = "PORT_CONNECTIVITY",
                nl01O.port_clkbad1 = "PORT_CONNECTIVITY",
                nl01O.port_clkena0 = "PORT_CONNECTIVITY",
                nl01O.port_clkena1 = "PORT_CONNECTIVITY",
                nl01O.port_clkena2 = "PORT_CONNECTIVITY",
                nl01O.port_clkena3 = "PORT_CONNECTIVITY",
                nl01O.port_clkena4 = "PORT_CONNECTIVITY",
                nl01O.port_clkena5 = "PORT_CONNECTIVITY",
                nl01O.port_clkloss = "PORT_CONNECTIVITY",
                nl01O.port_clkswitch = "PORT_CONNECTIVITY",
                nl01O.port_configupdate = "PORT_CONNECTIVITY",
                nl01O.port_enable0 = "PORT_CONNECTIVITY",
                nl01O.port_enable1 = "PORT_CONNECTIVITY",
                nl01O.port_extclk0 = "PORT_CONNECTIVITY",
                nl01O.port_extclk1 = "PORT_CONNECTIVITY",
                nl01O.port_extclk2 = "PORT_CONNECTIVITY",
                nl01O.port_extclk3 = "PORT_CONNECTIVITY",
                nl01O.port_extclkena0 = "PORT_CONNECTIVITY",
                nl01O.port_extclkena1 = "PORT_CONNECTIVITY",
                nl01O.port_extclkena2 = "PORT_CONNECTIVITY",
                nl01O.port_extclkena3 = "PORT_CONNECTIVITY",
                nl01O.port_fbin = "PORT_CONNECTIVITY",
                nl01O.port_fbout = "PORT_CONNECTIVITY",
                nl01O.port_inclk0 = "PORT_CONNECTIVITY",
                nl01O.port_inclk1 = "PORT_CONNECTIVITY",
                nl01O.port_locked = "PORT_CONNECTIVITY",
                nl01O.port_pfdena = "PORT_CONNECTIVITY",
                nl01O.port_phasecounterselect = "PORT_CONNECTIVITY",
                nl01O.port_phasedone = "PORT_CONNECTIVITY",
                nl01O.port_phasestep = "PORT_CONNECTIVITY",
                nl01O.port_phaseupdown = "PORT_CONNECTIVITY",
                nl01O.port_pllena = "PORT_CONNECTIVITY",
                nl01O.port_scanaclr = "PORT_CONNECTIVITY",
                nl01O.port_scanclk = "PORT_CONNECTIVITY",
                nl01O.port_scanclkena = "PORT_CONNECTIVITY",
                nl01O.port_scandata = "PORT_CONNECTIVITY",
                nl01O.port_scandataout = "PORT_CONNECTIVITY",
                nl01O.port_scandone = "PORT_CONNECTIVITY",
                nl01O.port_scanread = "PORT_CONNECTIVITY",
                nl01O.port_scanwrite = "PORT_CONNECTIVITY",
                nl01O.port_sclkout0 = "PORT_CONNECTIVITY",
                nl01O.port_sclkout1 = "PORT_CONNECTIVITY",
                nl01O.port_vcooverrange = "PORT_CONNECTIVITY",
                nl01O.port_vcounderrange = "PORT_CONNECTIVITY",
                nl01O.primary_clock = "INCLK0",
                nl01O.qualify_conf_done = "OFF",
                nl01O.scan_chain = "LONG",
                nl01O.sclkout0_phase_shift = "0",
                nl01O.sclkout1_phase_shift = "0",
                nl01O.self_reset_on_gated_loss_lock = "OFF",
                nl01O.self_reset_on_loss_lock = "OFF",
                nl01O.sim_gate_lock_device_behavior = "OFF",
                nl01O.skip_vco = "OFF",
                nl01O.spread_frequency = 0,
                nl01O.ss = 1,
                nl01O.switch_over_counter = 0,
                nl01O.switch_over_on_gated_lock = "OFF",
                nl01O.switch_over_on_lossclk = "OFF",
                nl01O.switch_over_type = "AUTO",
                nl01O.using_fbmimicbidir_port = "OFF",
                nl01O.valid_lock_multiplier = 1,
                nl01O.vco_center = 0,
                nl01O.vco_divide_by = 0,
                nl01O.vco_frequency_control = "AUTO",
                nl01O.vco_max = 0,
                nl01O.vco_min = 0,
                nl01O.vco_multiply_by = 0,
                nl01O.vco_phase_shift_step = 0,
                nl01O.vco_post_scale = 0,
                nl01O.width_clock = 6,
                nl01O.width_phasecounterselect = 4;
        altsyncram   n00OOO
        (
        .aclr0(1'b0),
        .aclr1(1'b0),
        .address_a({n0i1ll, n0i1li, n0i1iO, n0i10i}),
        .address_b({n0ii0i, n0ii1O, n0ii1l, n0i0lO}),
        .addressstall_a(1'b0),
        .addressstall_b(1'b0),
        .byteena_a({1'b1}),
        .byteena_b({1'b1}),
        .clock0(wire_nl0ii_clkout),
        .clock1(wire_nl00l_clkout),
        .clocken0(1'b1),
        .clocken1(1'b1),
        .clocken2(1'b1),
        .clocken3(1'b1),
        .data_a({n01O0O, n01O0l, n01O0i, n01O1O, n01O1l, n01O1i, n01lOO, n01lOl, n01lOi, n01l0O}),
        .data_b({10{1'b1}}),
        .eccstatus(),
        .q_a(),
        .q_b(wire_n00OOO_q_b),
        .rden_a(1'b1),
        .rden_b(1'b1),
        .wren_a(n01Oii),
        .wren_b(1'b0));
        defparam
                n00OOO.address_aclr_a = "NONE",
                n00OOO.address_aclr_b = "NONE",
                n00OOO.address_reg_b = "CLOCK1",
                n00OOO.byte_size = 8,
                n00OOO.byteena_aclr_a = "NONE",
                n00OOO.byteena_aclr_b = "NONE",
                n00OOO.byteena_reg_b = "CLOCK1",
                n00OOO.clock_enable_core_a = "USE_INPUT_CLKEN",
                n00OOO.clock_enable_core_b = "USE_INPUT_CLKEN",
                n00OOO.clock_enable_input_a = "NORMAL",
                n00OOO.clock_enable_input_b = "NORMAL",
                n00OOO.clock_enable_output_a = "NORMAL",
                n00OOO.clock_enable_output_b = "NORMAL",
                n00OOO.ecc_pipeline_stage_enabled = "FALSE",
                n00OOO.enable_ecc = "FALSE",
                n00OOO.indata_aclr_a = "NONE",
                n00OOO.indata_aclr_b = "NONE",
                n00OOO.indata_reg_b = "CLOCK1",
                n00OOO.init_file_layout = "PORT_A",
                n00OOO.intended_device_family = "CYCLONEIVGX",
                n00OOO.numwords_a = 16,
                n00OOO.numwords_b = 16,
                n00OOO.operation_mode = "DUAL_PORT",
                n00OOO.outdata_aclr_a = "NONE",
                n00OOO.outdata_aclr_b = "NONE",
                n00OOO.outdata_reg_a = "UNREGISTERED",
                n00OOO.outdata_reg_b = "UNREGISTERED",
                n00OOO.ram_block_type = "AUTO",
                n00OOO.rdcontrol_aclr_b = "NONE",
                n00OOO.rdcontrol_reg_b = "CLOCK1",
                n00OOO.read_during_write_mode_mixed_ports = "DONT_CARE",
                n00OOO.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
                n00OOO.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
                n00OOO.width_a = 10,
                n00OOO.width_b = 10,
                n00OOO.width_byteena_a = 1,
                n00OOO.width_byteena_b = 1,
                n00OOO.width_eccstatus = 3,
                n00OOO.widthad_a = 4,
                n00OOO.widthad_b = 4,
                n00OOO.wrcontrol_aclr_a = "NONE",
                n00OOO.wrcontrol_aclr_b = "NONE",
                n00OOO.wrcontrol_wraddress_reg_b = "CLOCK1",
                n00OOO.lpm_hint = "WIDTH_BYTEENA=1";
        altsyncram   ni1O0i
        (
        .aclr0(1'b0),
        .aclr1(1'b0),
        .address_a({ni1OOO, ni1OOl, ni1OOi, ni1Oil}),
        .address_b({ni00iO, ni00il, ni00ii, ni001l}),
        .addressstall_a(1'b0),
        .addressstall_b(1'b0),
        .byteena_a({1'b1}),
        .byteena_b({1'b1}),
        .clock0(wire_nl00l_clkout),
        .clock1(wire_nl00l_clkout),
        .clocken0(1'b1),
        .clocken1(1'b1),
        .clocken2(1'b1),
        .clocken3(1'b1),
        .data_a({nill0i, nill1O, nill1l, nill1i, niliOO, niliOl, niliOi, nililO, nilill, niliil}),
        .data_b({10{1'b1}}),
        .eccstatus(),
        .q_a(),
        .q_b(wire_ni1O0i_q_b),
        .rden_a(1'b1),
        .rden_b(1'b1),
        .wren_a(nli1l1O),
        .wren_b(1'b0));
        defparam
                ni1O0i.address_aclr_a = "NONE",
                ni1O0i.address_aclr_b = "NONE",
                ni1O0i.address_reg_b = "CLOCK1",
                ni1O0i.byte_size = 8,
                ni1O0i.byteena_aclr_a = "NONE",
                ni1O0i.byteena_aclr_b = "NONE",
                ni1O0i.byteena_reg_b = "CLOCK1",
                ni1O0i.clock_enable_core_a = "USE_INPUT_CLKEN",
                ni1O0i.clock_enable_core_b = "USE_INPUT_CLKEN",
                ni1O0i.clock_enable_input_a = "NORMAL",
                ni1O0i.clock_enable_input_b = "NORMAL",
                ni1O0i.clock_enable_output_a = "NORMAL",
                ni1O0i.clock_enable_output_b = "NORMAL",
                ni1O0i.ecc_pipeline_stage_enabled = "FALSE",
                ni1O0i.enable_ecc = "FALSE",
                ni1O0i.indata_aclr_a = "NONE",
                ni1O0i.indata_aclr_b = "NONE",
                ni1O0i.indata_reg_b = "CLOCK1",
                ni1O0i.init_file_layout = "PORT_A",
                ni1O0i.intended_device_family = "CYCLONEIVGX",
                ni1O0i.numwords_a = 16,
                ni1O0i.numwords_b = 16,
                ni1O0i.operation_mode = "DUAL_PORT",
                ni1O0i.outdata_aclr_a = "NONE",
                ni1O0i.outdata_aclr_b = "NONE",
                ni1O0i.outdata_reg_a = "UNREGISTERED",
                ni1O0i.outdata_reg_b = "UNREGISTERED",
                ni1O0i.ram_block_type = "AUTO",
                ni1O0i.rdcontrol_aclr_b = "NONE",
                ni1O0i.rdcontrol_reg_b = "CLOCK1",
                ni1O0i.read_during_write_mode_mixed_ports = "DONT_CARE",
                ni1O0i.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
                ni1O0i.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
                ni1O0i.width_a = 10,
                ni1O0i.width_b = 10,
                ni1O0i.width_byteena_a = 1,
                ni1O0i.width_byteena_b = 1,
                ni1O0i.width_eccstatus = 3,
                ni1O0i.widthad_a = 4,
                ni1O0i.widthad_b = 4,
                ni1O0i.wrcontrol_aclr_a = "NONE",
                ni1O0i.wrcontrol_aclr_b = "NONE",
                ni1O0i.wrcontrol_wraddress_reg_b = "CLOCK1",
                ni1O0i.lpm_hint = "WIDTH_BYTEENA=1";
        cycloneiv_hssi_calibration_block   nl0iO
        (
        .calibrationstatus(),
        .clk(gxb_cal_blk_clk),
        .nonusertocmu(wire_nl0iO_nonusertocmu),
        .powerdn(1'b0),
        .testctrl()
        );
        cycloneiv_hssi_cmu   nl0il
        (
        .adet({4{1'b0}}),
        .alignstatus(),
        .coreclkout(),
        .digitaltestout(),
        .dpclk(reconfig_clk),
        .dpriodisable(reconfig_togxb[1]),
        .dpriodisableout(wire_nl0il_dpriodisableout),
        .dprioin(reconfig_togxb[0]),
        .dprioload(reconfig_togxb[2]),
        .dpriooe(),
        .dprioout(wire_nl0il_dprioout),
        .enabledeskew(),
        .fiforesetrd(),
        .fixedclk({{3{1'b0}}, (reconfig_clk & ((~ nl0lO) & (~ nl0li)))}),
        .nonuserfromcal(wire_nl0iO_nonusertocmu),
        .quadreset(gxb_pwrdn_in),
        .quadresetout(wire_nl0il_quadresetout),
        .rdalign({4{1'b0}}),
        .rdenablesync(1'b0),
        .recovclk(1'b0),
        .refclkout(),
        .rxanalogreset({{3{1'b0}}, ((~ reconfig_togxb[3]) & n1l1i)}),
        .rxanalogresetout(wire_nl0il_rxanalogresetout),
        .rxcrupowerdown(wire_nl0il_rxcrupowerdown),
        .rxctrl({4{1'b0}}),
        .rxctrlout(),
        .rxdatain({32{1'b0}}),
        .rxdataout(),
        .rxdatavalid({4{1'b0}}),
        .rxdigitalreset({{3{1'b0}}, nliii0O}),
        .rxdigitalresetout(wire_nl0il_rxdigitalresetout),
        .rxibpowerdown(wire_nl0il_rxibpowerdown),
        .rxpcsdprioin({{1200{1'b0}}, wire_nl0ii_dprioout[399:0]}),
        .rxpcsdprioout(wire_nl0il_rxpcsdprioout),
        .rxphfifox4byteselout(),
        .rxphfifox4rdenableout(),
        .rxphfifox4wrclkout(),
        .rxphfifox4wrenableout(),
        .rxpmadprioin({{900{1'b0}}, wire_nl00O_dprioout[299:0]}),
        .rxpmadprioout(wire_nl0il_rxpmadprioout),
        .rxpowerdown({4{1'b0}}),
        .rxrunningdisp({4{1'b0}}),
        .syncstatus({4{1'b0}}),
        .testout(),
        .txanalogresetout(wire_nl0il_txanalogresetout),
        .txctrl({4{1'b0}}),
        .txctrlout(),
        .txdatain({32{1'b0}}),
        .txdataout(),
        .txdetectrxpowerdown(wire_nl0il_txdetectrxpowerdown),
        .txdigitalreset({{3{1'b0}}, nliiiiO}),
        .txdigitalresetout(wire_nl0il_txdigitalresetout),
        .txdividerpowerdown(wire_nl0il_txdividerpowerdown),
        .txobpowerdown(wire_nl0il_txobpowerdown),
        .txpcsdprioin({{450{1'b0}}, wire_nl00l_dprioout[149:0]}),
        .txpcsdprioout(wire_nl0il_txpcsdprioout),
        .txphfifox4byteselout(),
        .txphfifox4rdclkout(),
        .txphfifox4rdenableout(),
        .txphfifox4wrenableout(),
        .txpmadprioin({{900{1'b0}}, wire_nl00i_dprioout[299:0]}),
        .txpmadprioout(wire_nl0il_txpmadprioout),
        .pmacramtest(),
        .refclkdig(),
        .rxcoreclk(),
        .rxphfifordenable(),
        .rxphfiforeset(),
        .rxphfifowrdisable(),
        .scanclk(),
        .scanmode(),
        .scanshift(),
        .testin(),
        .txclk(),
        .txcoreclk(),
        .txphfiforddisable(),
        .txphfiforeset(),
        .txphfifowrenable()
        );
        defparam
                nl0il.auto_spd_deassert_ph_fifo_rst_count = 8,
                nl0il.auto_spd_phystatus_notify_count = 0,
                nl0il.devaddr = 1,
                nl0il.dprio_config_mode = 6'h01,
                nl0il.in_xaui_mode = "false",
                nl0il.lpm_type = "cycloneiv_hssi_cmu",
                nl0il.portaddr = 1,
                nl0il.rx0_channel_bonding = "none",
                nl0il.rx0_clk1_mux_select = "recovered clock",
                nl0il.rx0_clk2_mux_select = "recovered clock",
                nl0il.rx0_ph_fifo_reg_mode = "false",
                nl0il.rx0_rd_clk_mux_select = "core clock",
                nl0il.rx0_recovered_clk_mux_select = "recovered clock",
                nl0il.rx0_reset_clock_output_during_digital_reset = "false",
                nl0il.rx0_use_double_data_mode = "false",
                nl0il.tx0_channel_bonding = "none",
                nl0il.tx0_rd_clk_mux_select = "central",
                nl0il.tx0_reset_clock_output_during_digital_reset = "false",
                nl0il.tx0_use_double_data_mode = "false",
                nl0il.tx0_wr_clk_mux_select = "core_clk",
                nl0il.use_coreclk_out_post_divider = "false",
                nl0il.use_deskew_fifo = "false";
        cycloneiv_hssi_rx_pcs   nl0ii
        (
        .a1a2size(1'b0),
        .a1a2sizeout(),
        .a1detect(),
        .a2detect(),
        .adetectdeskew(),
        .alignstatus(1'b0),
        .alignstatussync(1'b0),
        .alignstatussyncout(),
        .bistdone(),
        .bisterr(),
        .bitslipboundaryselectout(),
        .byteorderalignstatus(),
        .cdrctrlearlyeios(),
        .cdrctrllocktorefcl(reconfig_togxb[3]),
        .cdrctrllocktorefclkout(wire_nl0ii_cdrctrllocktorefclkout),
        .clkout(wire_nl0ii_clkout),
        .coreclk(wire_nl0ii_clkout),
        .coreclkout(),
        .ctrldetect(wire_nl0ii_ctrldetect),
        .datain({wire_nl00O_recoverdataout[9:0]}),
        .dataout(wire_nl0ii_dataout),
        .dataoutfull(),
        .digitalreset(wire_nl0il_rxdigitalresetout[0]),
        .disperr(wire_nl0ii_disperr),
        .dpriodisable(wire_nl0il_dpriodisableout),
        .dprioin({wire_nl0il_rxpcsdprioout[399:0]}),
        .dprioout(wire_nl0ii_dprioout),
        .enabledeskew(1'b0),
        .enabyteord(1'b0),
        .enapatternalign(1'b0),
        .errdetect(wire_nl0ii_errdetect),
        .fifordin(1'b0),
        .fifordout(),
        .fiforesetrd(1'b0),
        .hipdataout(),
        .hipdatavalid(),
        .hipelecidle(),
        .hipphydonestatus(),
        .hipstatus(),
        .invpol(1'b0),
        .k1detect(),
        .k2detect(),
        .masterclk(1'b0),
        .parallelfdbk({20{1'b0}}),
        .patterndetect(wire_nl0ii_patterndetect),
        .phfifooverflow(),
        .phfifordenable(1'b1),
        .phfifordenableout(),
        .phfiforeset(1'b0),
        .phfiforesetout(),
        .phfifounderflow(),
        .phfifowrdisable(1'b0),
        .phfifowrdisableout(),
        .pipebufferstat(),
        .pipedatavalid(),
        .pipeelecidle(),
        .pipephydonestatus(),
        .pipepowerdown({2{1'b0}}),
        .pipepowerstate({4{1'b0}}),
        .pipestatetransdoneout(),
        .pipestatus(),
        .prbscidenable(1'b0),
        .quadreset(wire_nl0il_quadresetout),
        .rdalign(),
        .recoveredclk(wire_nl00O_clockout),
        .revbitorderwa(1'b0),
        .revparallelfdbkdata(),
        .rlv(wire_nl0ii_rlv),
        .rmfifodatadeleted(),
        .rmfifodatainserted(),
        .rmfifoempty(),
        .rmfifofull(),
        .rmfifordena(1'b0),
        .rmfiforeset(1'b0),
        .rmfifowrena(1'b0),
        .runningdisp(wire_nl0ii_runningdisp),
        .rxdetectvalid(1'b0),
        .rxfound({2{1'b0}}),
        .signaldetect(),
        .signaldetected(wire_nl00O_signaldetect),
        .syncstatus(wire_nl0ii_syncstatus),
        .syncstatusdeskew(),
        .xauidelcondmetout(),
        .xauififoovrout(),
        .xauiinsertincompleteout(),
        .xauilatencycompout(),
        .xgmctrldet(),
        .xgmctrlin(1'b0),
        .xgmdatain({8{1'b0}}),
        .xgmdataout(),
        .xgmdatavalid(),
        .xgmrunningdisp(),
        .bitslip(),
        .elecidleinfersel(),
        .grayelecidleinferselfromtx(),
        .hip8b10binvpolarity(),
        .hipelecidleinfersel(),
        .hippowerdown(),
        .localrefclk(),
        .phfifox4bytesel(),
        .phfifox4rdenable(),
        .phfifox4wrclk(),
        .phfifox4wrenable(),
        .pipe8b10binvpolarity(),
        .pipeenrevparallellpbkfromtx(),
        .pmatestbusin(),
        .powerdn(),
        .refclk(),
        .revbyteorderwa(),
        .wareset(),
        .xauidelcondmet(),
        .xauififoovr(),
        .xauiinsertincomplete(),
        .xauilatencycomp()
        );
        defparam
                nl0ii.align_pattern = "1111100",
                nl0ii.align_pattern_length = 7,
                nl0ii.allow_align_polarity_inversion = "false",
                nl0ii.allow_pipe_polarity_inversion = "false",
                nl0ii.auto_spd_deassert_ph_fifo_rst_count = 8,
                nl0ii.auto_spd_phystatus_notify_count = 0,
                nl0ii.bit_slip_enable = "false",
                nl0ii.byte_order_mode = "none",
                nl0ii.byte_order_pad_pattern = "0",
                nl0ii.byte_order_pattern = "0",
                nl0ii.byte_order_pld_ctrl_enable = "false",
                nl0ii.cdrctrl_bypass_ppm_detector_cycle = 1000,
                nl0ii.cdrctrl_enable = "false",
                nl0ii.cdrctrl_mask_cycle = 800,
                nl0ii.cdrctrl_min_lock_to_ref_cycle = 63,
                nl0ii.cdrctrl_rxvalid_mask = "false",
                nl0ii.channel_bonding = "none",
                nl0ii.channel_number = 0,
                nl0ii.channel_width = 8,
                nl0ii.clk1_mux_select = "recovered clock",
                nl0ii.clk2_mux_select = "recovered clock",
                nl0ii.core_clock_0ppm = "false",
                nl0ii.datapath_low_latency_mode = "false",
                nl0ii.datapath_protocol = "basic",
                nl0ii.dec_8b_10b_compatibility_mode = "true",
                nl0ii.dec_8b_10b_mode = "normal",
                nl0ii.deskew_pattern = "0",
                nl0ii.disable_auto_idle_insertion = "true",
                nl0ii.disable_running_disp_in_word_align = "false",
                nl0ii.disallow_kchar_after_pattern_ordered_set = "false",
                nl0ii.dprio_config_mode = 6'h01,
                nl0ii.elec_idle_infer_enable = "false",
                nl0ii.elec_idle_num_com_detect = 3,
                nl0ii.enable_bit_reversal = "false",
                nl0ii.enable_self_test_mode = "false",
                nl0ii.force_signal_detect_dig = "true",
                nl0ii.hip_enable = "false",
                nl0ii.infiniband_invalid_code = 0,
                nl0ii.insert_pad_on_underflow = "false",
                nl0ii.lpm_type = "cycloneiv_hssi_rx_pcs",
                nl0ii.num_align_code_groups_in_ordered_set = 1,
                nl0ii.num_align_cons_good_data = 4,
                nl0ii.num_align_cons_pat = 3,
                nl0ii.num_align_loss_sync_error = 4,
                nl0ii.ph_fifo_low_latency_enable = "true",
                nl0ii.ph_fifo_reg_mode = "false",
                nl0ii.protocol_hint = "gige",
                nl0ii.rate_match_back_to_back = "true",
                nl0ii.rate_match_delete_threshold = 13,
                nl0ii.rate_match_empty_threshold = 5,
                nl0ii.rate_match_fifo_mode = "false",
                nl0ii.rate_match_full_threshold = 20,
                nl0ii.rate_match_insert_threshold = 11,
                nl0ii.rate_match_ordered_set_based = "true",
                nl0ii.rate_match_pattern1 = "10100010010101111100",
                nl0ii.rate_match_pattern2 = "10101011011010000011",
                nl0ii.rate_match_pattern_size = 20,
                nl0ii.rate_match_reset_enable = "false",
                nl0ii.rate_match_skip_set_based = "false",
                nl0ii.rate_match_start_threshold = 7,
                nl0ii.rd_clk_mux_select = "core clock",
                nl0ii.recovered_clk_mux_select = "recovered clock",
                nl0ii.run_length = 5,
                nl0ii.run_length_enable = "true",
                nl0ii.rx_detect_bypass = "false",
                nl0ii.rx_phfifo_wait_cnt = 15,
                nl0ii.rxstatus_error_report_mode = 0,
                nl0ii.self_test_mode = "incremental",
                nl0ii.use_alignment_state_machine = "true",
                nl0ii.use_deskew_fifo = "false",
                nl0ii.use_double_data_mode = "false",
                nl0ii.use_parallel_loopback = "false";
        cycloneiv_hssi_rx_pma   nl00O
        (
        .analogtestbus(),
        .clockout(wire_nl00O_clockout),
        .crupowerdn(wire_nl0il_rxcrupowerdown[0]),
        .datain(rxp),
        .datastrobeout(),
        .deserclock(wire_nl01O_icdrclk),
        .diagnosticlpbkout(wire_nl00O_diagnosticlpbkout),
        .dpriodisable(wire_nl0il_dpriodisableout),
        .dprioin({wire_nl0il_rxpmadprioout[299:0]}),
        .dprioout(wire_nl00O_dprioout),
        .freqlocked(wire_nl00O_freqlocked),
        .locktodata(1'b0),
        .locktoref(wire_nl0ii_cdrctrllocktorefclkout),
        .locktorefout(),
        .powerdn(wire_nl0il_rxibpowerdown[0]),
        .ppmdetectrefclk(wire_nl01O_fref),
        .recoverdataout(wire_nl00O_recoverdataout),
        .reverselpbkout(wire_nl00O_reverselpbkout),
        .rxpmareset(wire_nl0il_rxanalogresetout[0]),
        .seriallpbkin(wire_nl00i_seriallpbkout),
        .signaldetect(wire_nl00O_signaldetect),
        .testbussel({1'b0, {2{1'b1}}, 1'b0}),
        .dpashift()
        );
        defparam
                nl00O.allow_serial_loopback = "false",
                nl00O.channel_number = 0,
                nl00O.common_mode = "0.82V",
                nl00O.deserialization_factor = 10,
                nl00O.dprio_config_mode = 6'h01,
                nl00O.effective_data_rate = "1250.0 Mbps",
                nl00O.enable_local_divider = "false",
                nl00O.enable_ltd = "false",
                nl00O.enable_ltr = "false",
                nl00O.enable_second_order_loop = "false",
                nl00O.eq_dc_gain = 0,
                nl00O.eq_setting = 1,
                nl00O.force_signal_detect = "true",
                nl00O.logical_channel_address = 0,
                nl00O.loop_1_digital_filter = 8,
                nl00O.lpm_type = "cycloneiv_hssi_rx_pma",
                nl00O.offset_cancellation = 1,
                nl00O.ppm_gen1_2_xcnt_en = 1,
                nl00O.ppm_post_eidle = 0,
                nl00O.ppmselect = 8,
                nl00O.protocol_hint = "gige",
                nl00O.signal_detect_hysteresis = 8,
                nl00O.signal_detect_hysteresis_valid_threshold = 14,
                nl00O.signal_detect_loss_threshold = 1,
                nl00O.termination = "OCT 100 Ohms",
                nl00O.use_external_termination = "false";
        cycloneiv_hssi_tx_pcs   nl00l
        (
        .clkout(wire_nl00l_clkout),
        .coreclk(wire_nl00l_clkout),
        .coreclkout(),
        .ctrlenable({1'b0, n1i1lO}),
        .datain({{12{1'b0}}, n1i0iO, n1i0il, n1i0ii, n1i00O, n1i00l, n1i00i, n1i01O, n1i01l}),
        .datainfull({22{1'b0}}),
        .dataout(wire_nl00l_dataout),
        .detectrxloop(1'b0),
        .digitalreset(wire_nl0il_txdigitalresetout[0]),
        .dpriodisable(wire_nl0il_dpriodisableout),
        .dprioin({wire_nl0il_txpcsdprioout[149:0]}),
        .dprioout(wire_nl00l_dprioout),
        .enrevparallellpbk(1'b0),
        .forcedisp({2{1'b0}}),
        .forceelecidleout(),
        .grayelecidleinferselout(),
        .hiptxclkout(),
        .invpol(1'b0),
        .localrefclk(wire_nl00i_clockout),
        .parallelfdbkout(),
        .phfifooverflow(),
        .phfiforddisable(1'b0),
        .phfiforddisableout(),
        .phfiforeset(1'b0),
        .phfiforesetout(),
        .phfifounderflow(),
        .phfifowrenable(1'b1),
        .phfifowrenableout(),
        .pipeenrevparallellpbkout(),
        .pipepowerdownout(),
        .pipepowerstateout(),
        .pipestatetransdone(1'b0),
        .powerdn({2{1'b0}}),
        .quadreset(wire_nl0il_quadresetout),
        .rdenablesync(),
        .revparallelfdbk({20{1'b0}}),
        .txdetectrx(wire_nl00l_txdetectrx),
        .xgmctrlenable(),
        .xgmdataout(),
        .bitslipboundaryselect(),
        .dispval(),
        .elecidleinfersel(),
        .forceelecidle(),
        .hipdatain(),
        .hipdetectrxloop(),
        .hipelecidleinfersel(),
        .hipforceelecidle(),
        .hippowerdn(),
        .phfifox4bytesel(),
        .phfifox4rdclk(),
        .phfifox4rdenable(),
        .phfifox4wrenable(),
        .pipetxswing(),
        .prbscidenable(),
        .refclk(),
        .xgmctrl(),
        .xgmdatain()
        );
        defparam
                nl00l.allow_polarity_inversion = "false",
                nl00l.bitslip_enable = "false",
                nl00l.channel_bonding = "none",
                nl00l.channel_number = 0,
                nl00l.channel_width = 8,
                nl00l.core_clock_0ppm = "false",
                nl00l.datapath_low_latency_mode = "false",
                nl00l.datapath_protocol = "basic",
                nl00l.disable_ph_low_latency_mode = "false",
                nl00l.disparity_mode = "none",
                nl00l.dprio_config_mode = 6'h01,
                nl00l.elec_idle_delay = 6,
                nl00l.enable_bit_reversal = "false",
                nl00l.enable_idle_selection = "true",
                nl00l.enable_reverse_parallel_loopback = "false",
                nl00l.enable_self_test_mode = "false",
                nl00l.enc_8b_10b_compatibility_mode = "true",
                nl00l.enc_8b_10b_mode = "normal",
                nl00l.hip_enable = "false",
                nl00l.lpm_type = "cycloneiv_hssi_tx_pcs",
                nl00l.ph_fifo_reg_mode = "false",
                nl00l.prbs_cid_pattern = "false",
                nl00l.protocol_hint = "gige",
                nl00l.refclk_select = "local",
                nl00l.self_test_mode = "incremental",
                nl00l.use_double_data_mode = "false",
                nl00l.wr_clk_mux_select = "core_clk";
        cycloneiv_hssi_tx_pma   nl00i
        (
        .cgbpowerdn(wire_nl0il_txdividerpowerdown[0]),
        .clockout(wire_nl00i_clockout),
        .datain({wire_nl00l_dataout[9:0]}),
        .dataout(wire_nl00i_dataout),
        .detectrxpowerdown(wire_nl0il_txdetectrxpowerdown[0]),
        .diagnosticlpbkin(wire_nl00O_diagnosticlpbkout),
        .dpriodisable(wire_nl0il_dpriodisableout),
        .dprioin({wire_nl0il_txpmadprioout[299:0]}),
        .dprioout(wire_nl00i_dprioout),
        .fastrefclk0in(wire_nl01O_clk[0]),
        .forceelecidle(1'b0),
        .powerdn(wire_nl0il_txobpowerdown[0]),
        .refclk0in(wire_nl01O_clk[1]),
        .refclk0inpulse(wire_nl01O_clk[2]),
        .reverselpbkin(wire_nl00O_reverselpbkout),
        .rxdetecten(wire_nl00l_txdetectrx),
        .rxdetectvalidout(),
        .rxfoundout(),
        .seriallpbkout(wire_nl00i_seriallpbkout),
        .txpmareset(wire_nl0il_txanalogresetout[0]),
        .rxdetectclk()
        );
        defparam
                nl00i.channel_number = 0,
                nl00i.common_mode = "0.65V",
                nl00i.dprio_config_mode = 6'h01,
                nl00i.effective_data_rate = "1250.0 Mbps",
                nl00i.enable_diagnostic_loopback = "false",
                nl00i.enable_reverse_serial_loopback = "false",
                nl00i.logical_channel_address = 0,
                nl00i.lpm_type = "cycloneiv_hssi_tx_pma",
                nl00i.preemp_tap_1 = 1,
                nl00i.protocol_hint = "gige",
                nl00i.rx_detect = 0,
                nl00i.serialization_factor = 10,
                nl00i.slew_rate = "medium",
                nl00i.termination = "OCT 100 Ohms",
                nl00i.use_external_termination = "false",
                nl00i.use_rx_detect = "false",
                nl00i.vod_selection = 1;
        initial
                nli000i55 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli000i55 <= nli000i56;
        event nli000i55_event;
        initial
                #1 ->nli000i55_event;
        always @(nli000i55_event)
                nli000i55 <= {1{1'b1}};
        initial
                nli000i56 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli000i56 <= nli000i55;
        initial
                nli001O57 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli001O57 <= nli001O58;
        event nli001O57_event;
        initial
                #1 ->nli001O57_event;
        always @(nli001O57_event)
                nli001O57 <= {1{1'b1}};
        initial
                nli001O58 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli001O58 <= nli001O57;
        initial
                nli010i59 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli010i59 <= nli010i60;
        event nli010i59_event;
        initial
                #1 ->nli010i59_event;
        always @(nli010i59_event)
                nli010i59 <= {1{1'b1}};
        initial
                nli010i60 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli010i60 <= nli010i59;
        initial
                nli011l63 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli011l63 <= nli011l64;
        event nli011l63_event;
        initial
                #1 ->nli011l63_event;
        always @(nli011l63_event)
                nli011l63 <= {1{1'b1}};
        initial
                nli011l64 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli011l64 <= nli011l63;
        initial
                nli011O61 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli011O61 <= nli011O62;
        event nli011O61_event;
        initial
                #1 ->nli011O61_event;
        always @(nli011O61_event)
                nli011O61 <= {1{1'b1}};
        initial
                nli011O62 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli011O62 <= nli011O61;
        initial
                nli0l0i53 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0l0i53 <= nli0l0i54;
        event nli0l0i53_event;
        initial
                #1 ->nli0l0i53_event;
        always @(nli0l0i53_event)
                nli0l0i53 <= {1{1'b1}};
        initial
                nli0l0i54 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0l0i54 <= nli0l0i53;
        initial
                nli0lii51 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lii51 <= nli0lii52;
        event nli0lii51_event;
        initial
                #1 ->nli0lii51_event;
        always @(nli0lii51_event)
                nli0lii51 <= {1{1'b1}};
        initial
                nli0lii52 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lii52 <= nli0lii51;
        initial
                nli0liO49 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0liO49 <= nli0liO50;
        event nli0liO49_event;
        initial
                #1 ->nli0liO49_event;
        always @(nli0liO49_event)
                nli0liO49 <= {1{1'b1}};
        initial
                nli0liO50 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0liO50 <= nli0liO49;
        initial
                nli0lll47 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lll47 <= nli0lll48;
        event nli0lll47_event;
        initial
                #1 ->nli0lll47_event;
        always @(nli0lll47_event)
                nli0lll47 <= {1{1'b1}};
        initial
                nli0lll48 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lll48 <= nli0lll47;
        initial
                nli0lOi45 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lOi45 <= nli0lOi46;
        event nli0lOi45_event;
        initial
                #1 ->nli0lOi45_event;
        always @(nli0lOi45_event)
                nli0lOi45 <= {1{1'b1}};
        initial
                nli0lOi46 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0lOi46 <= nli0lOi45;
        initial
                nli0O0i41 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0O0i41 <= nli0O0i42;
        event nli0O0i41_event;
        initial
                #1 ->nli0O0i41_event;
        always @(nli0O0i41_event)
                nli0O0i41 <= {1{1'b1}};
        initial
                nli0O0i42 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0O0i42 <= nli0O0i41;
        initial
                nli0O1l43 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0O1l43 <= nli0O1l44;
        event nli0O1l43_event;
        initial
                #1 ->nli0O1l43_event;
        always @(nli0O1l43_event)
                nli0O1l43 <= {1{1'b1}};
        initial
                nli0O1l44 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0O1l44 <= nli0O1l43;
        initial
                nli0Oii39 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0Oii39 <= nli0Oii40;
        event nli0Oii39_event;
        initial
                #1 ->nli0Oii39_event;
        always @(nli0Oii39_event)
                nli0Oii39 <= {1{1'b1}};
        initial
                nli0Oii40 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0Oii40 <= nli0Oii39;
        initial
                nli0OiO37 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OiO37 <= nli0OiO38;
        event nli0OiO37_event;
        initial
                #1 ->nli0OiO37_event;
        always @(nli0OiO37_event)
                nli0OiO37 <= {1{1'b1}};
        initial
                nli0OiO38 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OiO38 <= nli0OiO37;
        initial
                nli0OlO35 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OlO35 <= nli0OlO36;
        event nli0OlO35_event;
        initial
                #1 ->nli0OlO35_event;
        always @(nli0OlO35_event)
                nli0OlO35 <= {1{1'b1}};
        initial
                nli0OlO36 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OlO36 <= nli0OlO35;
        initial
                nli0OOl33 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OOl33 <= nli0OOl34;
        event nli0OOl33_event;
        initial
                #1 ->nli0OOl33_event;
        always @(nli0OOl33_event)
                nli0OOl33 <= {1{1'b1}};
        initial
                nli0OOl34 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli0OOl34 <= nli0OOl33;
        initial
                nli1llO79 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1llO79 <= nli1llO80;
        event nli1llO79_event;
        initial
                #1 ->nli1llO79_event;
        always @(nli1llO79_event)
                nli1llO79 <= {1{1'b1}};
        initial
                nli1llO80 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1llO80 <= nli1llO79;
        initial
                nli1lOi77 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1lOi77 <= nli1lOi78;
        event nli1lOi77_event;
        initial
                #1 ->nli1lOi77_event;
        always @(nli1lOi77_event)
                nli1lOi77 <= {1{1'b1}};
        initial
                nli1lOi78 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1lOi78 <= nli1lOi77;
        initial
                nli1O0O75 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1O0O75 <= nli1O0O76;
        event nli1O0O75_event;
        initial
                #1 ->nli1O0O75_event;
        always @(nli1O0O75_event)
                nli1O0O75 <= {1{1'b1}};
        initial
                nli1O0O76 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1O0O76 <= nli1O0O75;
        initial
                nli1Oii73 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1Oii73 <= nli1Oii74;
        event nli1Oii73_event;
        initial
                #1 ->nli1Oii73_event;
        always @(nli1Oii73_event)
                nli1Oii73 <= {1{1'b1}};
        initial
                nli1Oii74 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1Oii74 <= nli1Oii73;
        initial
                nli1Oil71 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1Oil71 <= nli1Oil72;
        event nli1Oil71_event;
        initial
                #1 ->nli1Oil71_event;
        always @(nli1Oil71_event)
                nli1Oil71 <= {1{1'b1}};
        initial
                nli1Oil72 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1Oil72 <= nli1Oil71;
        initial
                nli1OlO69 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OlO69 <= nli1OlO70;
        event nli1OlO69_event;
        initial
                #1 ->nli1OlO69_event;
        always @(nli1OlO69_event)
                nli1OlO69 <= {1{1'b1}};
        initial
                nli1OlO70 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OlO70 <= nli1OlO69;
        initial
                nli1OOi67 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OOi67 <= nli1OOi68;
        event nli1OOi67_event;
        initial
                #1 ->nli1OOi67_event;
        always @(nli1OOi67_event)
                nli1OOi67 <= {1{1'b1}};
        initial
                nli1OOi68 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OOi68 <= nli1OOi67;
        initial
                nli1OOl65 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OOl65 <= nli1OOl66;
        event nli1OOl65_event;
        initial
                #1 ->nli1OOl65_event;
        always @(nli1OOl65_event)
                nli1OOl65 <= {1{1'b1}};
        initial
                nli1OOl66 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nli1OOl66 <= nli1OOl65;
        initial
                nlii00l13 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii00l13 <= nlii00l14;
        event nlii00l13_event;
        initial
                #1 ->nlii00l13_event;
        always @(nlii00l13_event)
                nlii00l13 <= {1{1'b1}};
        initial
                nlii00l14 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii00l14 <= nlii00l13;
        initial
                nlii01i19 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01i19 <= nlii01i20;
        event nlii01i19_event;
        initial
                #1 ->nlii01i19_event;
        always @(nlii01i19_event)
                nlii01i19 <= {1{1'b1}};
        initial
                nlii01i20 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01i20 <= nlii01i19;
        initial
                nlii01l17 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01l17 <= nlii01l18;
        event nlii01l17_event;
        initial
                #1 ->nlii01l17_event;
        always @(nlii01l17_event)
                nlii01l17 <= {1{1'b1}};
        initial
                nlii01l18 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01l18 <= nlii01l17;
        initial
                nlii01O15 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01O15 <= nlii01O16;
        event nlii01O15_event;
        initial
                #1 ->nlii01O15_event;
        always @(nlii01O15_event)
                nlii01O15 <= {1{1'b1}};
        initial
                nlii01O16 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii01O16 <= nlii01O15;
        initial
                nlii0ii11 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0ii11 <= nlii0ii12;
        event nlii0ii11_event;
        initial
                #1 ->nlii0ii11_event;
        always @(nlii0ii11_event)
                nlii0ii11 <= {1{1'b1}};
        initial
                nlii0ii12 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0ii12 <= nlii0ii11;
        initial
                nlii0il10 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0il10 <= nlii0il9;
        initial
                nlii0il9 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0il9 <= nlii0il10;
        event nlii0il9_event;
        initial
                #1 ->nlii0il9_event;
        always @(nlii0il9_event)
                nlii0il9 <= {1{1'b1}};
        initial
                nlii0Oi7 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0Oi7 <= nlii0Oi8;
        event nlii0Oi7_event;
        initial
                #1 ->nlii0Oi7_event;
        always @(nlii0Oi7_event)
                nlii0Oi7 <= {1{1'b1}};
        initial
                nlii0Oi8 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0Oi8 <= nlii0Oi7;
        initial
                nlii0Ol5 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0Ol5 <= nlii0Ol6;
        event nlii0Ol5_event;
        initial
                #1 ->nlii0Ol5_event;
        always @(nlii0Ol5_event)
                nlii0Ol5 <= {1{1'b1}};
        initial
                nlii0Ol6 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0Ol6 <= nlii0Ol5;
        initial
                nlii0OO3 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0OO3 <= nlii0OO4;
        event nlii0OO3_event;
        initial
                #1 ->nlii0OO3_event;
        always @(nlii0OO3_event)
                nlii0OO3 <= {1{1'b1}};
        initial
                nlii0OO4 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii0OO4 <= nlii0OO3;
        initial
                nlii10i29 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii10i29 <= nlii10i30;
        event nlii10i29_event;
        initial
                #1 ->nlii10i29_event;
        always @(nlii10i29_event)
                nlii10i29 <= {1{1'b1}};
        initial
                nlii10i30 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii10i30 <= nlii10i29;
        initial
                nlii10O27 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii10O27 <= nlii10O28;
        event nlii10O27_event;
        initial
                #1 ->nlii10O27_event;
        always @(nlii10O27_event)
                nlii10O27 <= {1{1'b1}};
        initial
                nlii10O28 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii10O28 <= nlii10O27;
        initial
                nlii11l31 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii11l31 <= nlii11l32;
        event nlii11l31_event;
        initial
                #1 ->nlii11l31_event;
        always @(nlii11l31_event)
                nlii11l31 <= {1{1'b1}};
        initial
                nlii11l32 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii11l32 <= nlii11l31;
        initial
                nlii1iO25 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1iO25 <= nlii1iO26;
        event nlii1iO25_event;
        initial
                #1 ->nlii1iO25_event;
        always @(nlii1iO25_event)
                nlii1iO25 <= {1{1'b1}};
        initial
                nlii1iO26 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1iO26 <= nlii1iO25;
        initial
                nlii1ll23 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1ll23 <= nlii1ll24;
        event nlii1ll23_event;
        initial
                #1 ->nlii1ll23_event;
        always @(nlii1ll23_event)
                nlii1ll23 <= {1{1'b1}};
        initial
                nlii1ll24 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1ll24 <= nlii1ll23;
        initial
                nlii1Ol21 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1Ol21 <= nlii1Ol22;
        event nlii1Ol21_event;
        initial
                #1 ->nlii1Ol21_event;
        always @(nlii1Ol21_event)
                nlii1Ol21 <= {1{1'b1}};
        initial
                nlii1Ol22 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nlii1Ol22 <= nlii1Ol21;
        initial
                nliii1l1 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nliii1l1 <= nliii1l2;
        event nliii1l1_event;
        initial
                #1 ->nliii1l1_event;
        always @(nliii1l1_event)
                nliii1l1 <= {1{1'b1}};
        initial
                nliii1l2 = 0;
        always @ ( posedge wire_nl0ii_clkout)
                  nliii1l2 <= nliii1l1;
        initial
        begin
                n00iO = 0;
                n011l = 0;
                n011O = 0;
                n01ll = 0;
                n01Ol = 0;
                n01OO = 0;
                n10ii = 0;
                n10il = 0;
                n11OO = 0;
                n1i1l = 0;
                n1l1i = 0;
                n1O0i = 0;
        end
        always @ ( posedge clk or  posedge n110l)
        begin
                if (n110l == 1'b1)
                begin
                        n00iO <= 1;
                        n011l <= 1;
                        n011O <= 1;
                        n01ll <= 1;
                        n01Ol <= 1;
                        n01OO <= 1;
                        n10ii <= 1;
                        n10il <= 1;
                        n11OO <= 1;
                        n1i1l <= 1;
                        n1l1i <= 1;
                        n1O0i <= 1;
                end
                else
                begin
                        n00iO <= wire_n001i_dataout;
                        n011l <= wire_n010l_dataout;
                        n011O <= wire_n010O_dataout;
                        n01ll <= wire_n010i_dataout;
                        n01Ol <= wire_n001l_dataout;
                        n01OO <= wire_n001O_dataout;
                        n10ii <= wire_n101l_dataout;
                        n10il <= nli000l;
                        n11OO <= wire_n101O_dataout;
                        n1i1l <= nli00ii;
                        n1l1i <= nli00li;
                        n1O0i <= nli00Oi;
                end
        end
        initial
        begin
                n00ll = 0;
                n01lO = 0;
                n101i = 0;
                n10lO = 0;
                n1i0O = 0;
                n1iiO = 0;
                n1ill = 0;
                n1iOO = 0;
                n1l0O = 0;
                n1lii = 0;
                n1llO = 0;
                n1O1i = 0;
                n1O1l = 0;
                n1O1O = 0;
                n1Oll = 0;
                n1OlO = 0;
        end
        always @ ( posedge clk or  posedge n110l)
        begin
                if (n110l == 1'b1)
                begin
                        n00ll <= 0;
                        n01lO <= 0;
                        n101i <= 0;
                        n10lO <= 0;
                        n1i0O <= 0;
                        n1iiO <= 0;
                        n1ill <= 0;
                        n1iOO <= 0;
                        n1l0O <= 0;
                        n1lii <= 0;
                        n1llO <= 0;
                        n1O1i <= 0;
                        n1O1l <= 0;
                        n1O1O <= 0;
                        n1Oll <= 0;
                        n1OlO <= 0;
                end
                else
                begin
                        n00ll <= nli0i1O;
                        n01lO <= nlii00i;
                        n101i <= ((~ nli000O) & (((~ nli000l) & n10il) | n101i));
                        n10lO <= nlii00i;
                        n1i0O <= nlii00i;
                        n1iiO <= ((~ nli00il) & (n1iiO | ((~ nli00ii) & n1i1l)));
                        n1ill <= wire_n1l1l_dataout;
                        n1iOO <= wire_n1l1O_dataout;
                        n1l0O <= nlii00i;
                        n1lii <= ((~ nli00ll) & (n1lii | ((~ nli00li) & n1l1i)));
                        n1llO <= wire_n1O0l_dataout;
                        n1O1i <= wire_n1O0O_dataout;
                        n1O1l <= wire_n1Oii_dataout;
                        n1O1O <= wire_n1Oil_dataout;
                        n1Oll <= nli0i0l;
                        n1OlO <= ((~ nli00Ol) & (n1OlO | ((~ nli00Oi) & n1O0i)));
                end
        end
        initial
        begin
                n00Oii = 0;
                n00Oll = 0;
                n00OOl = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge n0O0Oi)
        begin
                if (n0O0Oi == 1'b1)
                begin
                        n00Oii <= 1;
                        n00Oll <= 1;
                        n00OOl <= 1;
                end
                else
                begin
                        n00Oii <= wire_n00l1l_o;
                        n00Oll <= n00OOl;
                        n00OOl <= nl010i;
                end
        end
        event n00Oii_event;
        event n00Oll_event;
        event n00OOl_event;
        initial
                #1 ->n00Oii_event;
        initial
                #1 ->n00Oll_event;
        initial
                #1 ->n00OOl_event;
        always @(n00Oii_event)
                n00Oii <= 1;
        always @(n00Oll_event)
                n00Oll <= 1;
        always @(n00OOl_event)
                n00OOl <= 1;
        initial
        begin
                n01iil = 0;
                n01ili = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge nlilOl)
        begin
                if (nlilOl == 1'b1)
                begin
                        n01iil <= 1;
                        n01ili <= 1;
                end
                else
                begin
                        n01iil <= n01ili;
                        n01ili <= nlii0iO;
                end
        end
        event n01iil_event;
        event n01ili_event;
        initial
                #1 ->n01iil_event;
        initial
                #1 ->n01ili_event;
        always @(n01iil_event)
                n01iil <= 1;
        always @(n01ili_event)
                n01ili <= 1;
        initial
        begin
                n0i01l = 0;
                n0i10i = 0;
                n0i10l = 0;
                n0i11i = 0;
                n0i11l = 0;
                n0i11O = 0;
                n0i1iO = 0;
                n0i1li = 0;
                n0i1ll = 0;
                n0i1Ol = 0;
                n0i1OO = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge n0O0Oi)
        begin
                if (n0O0Oi == 1'b1)
                begin
                        n0i01l <= 0;
                        n0i10i <= 0;
                        n0i10l <= 0;
                        n0i11i <= 0;
                        n0i11l <= 0;
                        n0i11O <= 0;
                        n0i1iO <= 0;
                        n0i1li <= 0;
                        n0i1ll <= 0;
                        n0i1Ol <= 0;
                        n0i1OO <= 0;
                end
                else if  (n01Oii == 1'b1)
                begin
                        n0i01l <= wire_n0i00O_dataout;
                        n0i10i <= n0i1Oi;
                        n0i10l <= (n0i1Ol ^ n0i1Oi);
                        n0i11i <= (n0i1OO ^ n0i1Ol);
                        n0i11l <= (n0i01l ^ n0i1OO);
                        n0i11O <= n0i01l;
                        n0i1iO <= n0i1Ol;
                        n0i1li <= n0i1OO;
                        n0i1ll <= n0i01l;
                        n0i1Ol <= wire_n0i00i_dataout;
                        n0i1OO <= wire_n0i00l_dataout;
                end
        end
        initial
        begin
                n0i0l = 0;
                n0iii = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge nli0iil)
        begin
                if (nli0iil == 1'b1)
                begin
                        n0i0l <= 1;
                        n0iii <= 1;
                end
                else
                begin
                        n0i0l <= n0iii;
                        n0iii <= nlii0iO;
                end
        end
        event n0i0l_event;
        event n0iii_event;
        initial
                #1 ->n0i0l_event;
        initial
                #1 ->n0iii_event;
        always @(n0i0l_event)
                n0i0l <= 1;
        always @(n0iii_event)
                n0iii <= 1;
        initial
        begin
                n0i1Oi = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge n0O0Oi)
        begin
                if (n0O0Oi == 1'b1)
                begin
                        n0i1Oi <= 1;
                end
                else if  (n01Oii == 1'b1)
                begin
                        n0i1Oi <= wire_n0i01O_dataout;
                end
        end
        event n0i1Oi_event;
        initial
                #1 ->n0i1Oi_event;
        always @(n0i1Oi_event)
                n0i1Oi <= 1;
        initial
        begin
                n0ii0O = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0ii0O <= 1;
                end
                else if  (nli10Oi == 1'b1)
                begin
                        n0ii0O <= wire_n0iilO_dataout;
                end
        end
        event n0ii0O_event;
        initial
                #1 ->n0ii0O_event;
        always @(n0ii0O_event)
                n0ii0O <= 1;
        initial
        begin
                n0i0iO = 0;
                n0i0li = 0;
                n0i0ll = 0;
                n0i0lO = 0;
                n0i0Oi = 0;
                n0ii0i = 0;
                n0ii1l = 0;
                n0ii1O = 0;
                n0iiil = 0;
                n0iiiO = 0;
                n0iill = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0i0iO <= 0;
                        n0i0li <= 0;
                        n0i0ll <= 0;
                        n0i0lO <= 0;
                        n0i0Oi <= 0;
                        n0ii0i <= 0;
                        n0ii1l <= 0;
                        n0ii1O <= 0;
                        n0iiil <= 0;
                        n0iiiO <= 0;
                        n0iill <= 0;
                end
                else if  (nli10Oi == 1'b1)
                begin
                        n0i0iO <= (n0iiiO ^ n0iiil);
                        n0i0li <= (n0iill ^ n0iiiO);
                        n0i0ll <= n0iill;
                        n0i0lO <= n0ii0O;
                        n0i0Oi <= (n0iiil ^ n0ii0O);
                        n0ii0i <= n0iill;
                        n0ii1l <= n0iiil;
                        n0ii1O <= n0iiiO;
                        n0iiil <= wire_n0iiOi_dataout;
                        n0iiiO <= wire_n0iiOl_dataout;
                        n0iill <= wire_n0iiOO_dataout;
                end
        end
        initial
        begin
                n0iOii = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0iOii <= 0;
                end
                else if  (n0iO0i == 1'b0)
                begin
                        n0iOii <= nlii0lO;
                end
        end
        initial
        begin
                n0iO0i = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0iO0i <= 1;
                end
                else if  (nlil1il == 1'b1)
                begin
                        n0iO0i <= wire_n0iOiO_o;
                end
        end
        event n0iO0i_event;
        initial
                #1 ->n0iO0i_event;
        always @(n0iO0i_event)
                n0iO0i <= 1;
        initial
        begin
                n0010i = 0;
                n0010l = 0;
                n0010O = 0;
                n0011i = 0;
                n001ii = 0;
                n001il = 0;
                n001iO = 0;
                n001li = 0;
                n00lOO = 0;
                n00O0l = 0;
                n00O0O = 0;
                n00O1i = 0;
                n00Oil = 0;
                n00OiO = 0;
                n00Oli = 0;
                n00OlO = 0;
                n01l0l = 0;
                n01l0O = 0;
                n01lOi = 0;
                n01lOl = 0;
                n01lOO = 0;
                n01O0i = 0;
                n01O0l = 0;
                n01O0O = 0;
                n01O1i = 0;
                n01O1l = 0;
                n01O1O = 0;
                n01Oii = 0;
                n01OiO = 0;
                n01OOO = 0;
                n0ilOi = 0;
                n0ilOO = 0;
                n0iO1i = 0;
                n0iO1l = 0;
                n0l01i = 0;
                n0l01O = 0;
                n0l11l = 0;
                n0l1iO = 0;
                n0l1ll = 0;
                n0l1lO = 0;
                n0l1Oi = 0;
                n0l1Ol = 0;
                n0l1OO = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge n0O0Oi)
        begin
                if (n0O0Oi == 1'b1)
                begin
                        n0010i <= 0;
                        n0010l <= 0;
                        n0010O <= 0;
                        n0011i <= 0;
                        n001ii <= 0;
                        n001il <= 0;
                        n001iO <= 0;
                        n001li <= 0;
                        n00lOO <= 0;
                        n00O0l <= 0;
                        n00O0O <= 0;
                        n00O1i <= 0;
                        n00Oil <= 0;
                        n00OiO <= 0;
                        n00Oli <= 0;
                        n00OlO <= 0;
                        n01l0l <= 0;
                        n01l0O <= 0;
                        n01lOi <= 0;
                        n01lOl <= 0;
                        n01lOO <= 0;
                        n01O0i <= 0;
                        n01O0l <= 0;
                        n01O0O <= 0;
                        n01O1i <= 0;
                        n01O1l <= 0;
                        n01O1O <= 0;
                        n01Oii <= 0;
                        n01OiO <= 0;
                        n01OOO <= 0;
                        n0ilOi <= 0;
                        n0ilOO <= 0;
                        n0iO1i <= 0;
                        n0iO1l <= 0;
                        n0l01i <= 0;
                        n0l01O <= 0;
                        n0l11l <= 0;
                        n0l1iO <= 0;
                        n0l1ll <= 0;
                        n0l1lO <= 0;
                        n0l1Oi <= 0;
                        n0l1Ol <= 0;
                        n0l1OO <= 0;
                end
                else
                begin
                        n0010i <= wire_n001lO_dataout;
                        n0010l <= wire_n001Oi_dataout;
                        n0010O <= wire_n001Ol_dataout;
                        n0011i <= wire_n001ll_dataout;
                        n001ii <= wire_n001OO_dataout;
                        n001il <= wire_n0001i_dataout;
                        n001iO <= wire_n0001l_dataout;
                        n001li <= wire_n00O1l_dataout;
                        n00lOO <= wire_n00O1O_dataout;
                        n00O0l <= wire_n00iOi_o;
                        n00O0O <= wire_n00iOO_o;
                        n00O1i <= wire_n00ill_o;
                        n00Oil <= n00OiO;
                        n00OiO <= nlilOl;
                        n00Oli <= n00OlO;
                        n00OlO <= nl011O;
                        n01l0l <= wire_n01lil_dataout;
                        n01l0O <= nlOiiOi;
                        n01lOi <= nlOil0l;
                        n01lOl <= nlOil0O;
                        n01lOO <= nlOilii;
                        n01O0i <= nlOilll;
                        n01O0l <= nli101i;
                        n01O0O <= (nlOiOOi | n01OOO);
                        n01O1i <= nlOilil;
                        n01O1l <= nlOiliO;
                        n01O1O <= nlOilli;
                        n01Oii <= wire_n01Oli_dataout;
                        n01OiO <= wire_n0011l_dataout;
                        n01OOO <= wire_n01lii_dataout;
                        n0ilOi <= wire_n0iO0l_o[1];
                        n0ilOO <= wire_n0iO0l_o[2];
                        n0iO1i <= wire_n0iO0l_o[3];
                        n0iO1l <= wire_n0iO0l_o[4];
                        n0l01i <= n0i0li;
                        n0l01O <= n0i0ll;
                        n0l11l <= wire_n0l1li_o;
                        n0l1iO <= (((n0l01O ^ n0l1Ol) ^ n0l01i) ^ n0l1OO);
                        n0l1ll <= ((n0l01O ^ n0l1OO) ^ n0l01i);
                        n0l1lO <= (n0l01O ^ n0l01i);
                        n0l1Oi <= n0l01O;
                        n0l1Ol <= n0i0Oi;
                        n0l1OO <= n0i0iO;
                end
        end
        initial
        begin
                n0iOil = 0;
                n0iOli = 0;
                n0iOll = 0;
                n0iOlO = 0;
                n0iOOi = 0;
                n0iOOl = 0;
                n0iOOO = 0;
                n0l0ll = 0;
                n0l11i = 0;
                n0li0O = 0;
                n0liil = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0iOil <= 0;
                        n0iOli <= 0;
                        n0iOll <= 0;
                        n0iOlO <= 0;
                        n0iOOi <= 0;
                        n0iOOl <= 0;
                        n0iOOO <= 0;
                        n0l0ll <= 0;
                        n0l11i <= 0;
                        n0li0O <= 0;
                        n0liil <= 0;
                end
                else
                begin
                        n0iOil <= (((n0l11i ^ n0iOOi) ^ n0iOOO) ^ n0iOOl);
                        n0iOli <= ((n0l11i ^ n0iOOl) ^ n0iOOO);
                        n0iOll <= (n0l11i ^ n0iOOO);
                        n0iOlO <= n0l11i;
                        n0iOOi <= n0i10l;
                        n0iOOl <= n0i11i;
                        n0iOOO <= n0i11l;
                        n0l0ll <= n0liil;
                        n0l11i <= n0i11O;
                        n0li0O <= wire_n0l0lO_dataout;
                        n0liil <= nlOl11i;
                end
        end
        initial
        begin
                n0lili = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge n0O0lO)
        begin
                if (n0O0lO == 1'b1)
                begin
                        n0lili <= 0;
                end
                else if  (n0Oi1i == 1'b1)
                begin
                        n0lili <= wire_n0lill_dataout;
                end
        end
        initial
        begin
                n0liOi = 0;
                n0liOl = 0;
                n0liOO = 0;
                n0ll1i = 0;
                n0ll1l = 0;
                n0ll1O = 0;
                n0llli = 0;
                n0llll = 0;
                n0lllO = 0;
                n0llOi = 0;
                n0llOl = 0;
                n0llOO = 0;
                n0O10i = 0;
                n0O10l = 0;
                n0O10O = 0;
                n0O11O = 0;
                n0O1ii = 0;
                n0O1il = 0;
                n0O1iO = 0;
                n0O1li = 0;
                n0O1ll = 0;
                n0O1Oi = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0ll)
        begin
                if (nlii0ll == 1'b1)
                begin
                        n0liOi <= 0;
                        n0liOl <= 0;
                        n0liOO <= 0;
                        n0ll1i <= 0;
                        n0ll1l <= 0;
                        n0ll1O <= 0;
                        n0llli <= 0;
                        n0llll <= 0;
                        n0lllO <= 0;
                        n0llOi <= 0;
                        n0llOl <= 0;
                        n0llOO <= 0;
                        n0O10i <= 0;
                        n0O10l <= 0;
                        n0O10O <= 0;
                        n0O11O <= 0;
                        n0O1ii <= 0;
                        n0O1il <= 0;
                        n0O1iO <= 0;
                        n0O1li <= 0;
                        n0O1ll <= 0;
                        n0O1Oi <= 0;
                end
                else if  (nlil1il == 1'b1)
                begin
                        n0liOi <= wire_n0ll0l_dataout;
                        n0liOl <= wire_n0ll0O_dataout;
                        n0liOO <= wire_n0llii_dataout;
                        n0ll1i <= wire_n0llil_dataout;
                        n0ll1l <= wire_n0lliO_dataout;
                        n0ll1O <= wire_n0illO_dataout;
                        n0llli <= wire_n0ll0i_dataout;
                        n0llll <= wire_n0illl_dataout;
                        n0lllO <= wire_n0lO1l_dataout;
                        n0llOi <= wire_n0lO1O_dataout;
                        n0llOl <= wire_n0lO0i_dataout;
                        n0llOO <= wire_n0lO0l_dataout;
                        n0O10i <= wire_n0O1OO_dataout;
                        n0O10l <= wire_n0O01i_dataout;
                        n0O10O <= wire_n0O01l_dataout;
                        n0O11O <= wire_n0O1Ol_dataout;
                        n0O1ii <= wire_n0O01O_dataout;
                        n0O1il <= wire_n0O00i_dataout;
                        n0O1iO <= wire_n0O00l_dataout;
                        n0O1li <= wire_n0O00O_dataout;
                        n0O1ll <= wire_n0O0ii_dataout;
                        n0O1Oi <= wire_n0O0il_dataout;
                end
        end
        initial
        begin
                n0O0ll = 0;
                n0O0Oi = 0;
                n0Oiil = 0;
                n101ll = 0;
                nlOi01l = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge nlili1O)
        begin
                if (nlili1O == 1'b1)
                begin
                        n0O0ll <= 1;
                        n0O0Oi <= 1;
                        n0Oiil <= 1;
                        n101ll <= 1;
                        nlOi01l <= 1;
                end
                else
                begin
                        n0O0ll <= (~ (wire_n01ilO_dout[1] & (~ wire_n01ilO_dout[0])));
                        n0O0Oi <= ((nlili1O | n0O11l) | n01iil);
                        n0Oiil <= wire_n01ilO_dout[1];
                        n101ll <= wire_n100OO_dataout;
                        nlOi01l <= wire_nlOi0ll_dataout;
                end
        end
        event n0O0ll_event;
        event n0O0Oi_event;
        event n0Oiil_event;
        event n101ll_event;
        event nlOi01l_event;
        initial
                #1 ->n0O0ll_event;
        initial
                #1 ->n0O0Oi_event;
        initial
                #1 ->n0Oiil_event;
        initial
                #1 ->n101ll_event;
        initial
                #1 ->nlOi01l_event;
        always @(n0O0ll_event)
                n0O0ll <= 1;
        always @(n0O0Oi_event)
                n0O0Oi <= 1;
        always @(n0Oiil_event)
                n0Oiil <= 1;
        always @(n101ll_event)
                n101ll <= 1;
        always @(nlOi01l_event)
                nlOi01l <= 1;
        initial
        begin
                n0lO0O = 0;
                n0lO1i = 0;
                n0O0iO = 0;
                n0O11i = 0;
                n0Oi1i = 0;
                n0Oili = 0;
                nlil01i = 0;
                nlil01l = 0;
                nlil01O = 0;
                nlil10i = 0;
                nlil1li = 0;
                nlil1ll = 0;
                nlil1lO = 0;
                nlil1Oi = 0;
                nlil1Ol = 0;
                nlil1OO = 0;
                nlili1i = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0ll)
        begin
                if (nlii0ll == 1'b1)
                begin
                        n0lO0O <= 0;
                        n0lO1i <= 0;
                        n0O0iO <= 0;
                        n0O11i <= 0;
                        n0Oi1i <= 0;
                        n0Oili <= 0;
                        nlil01i <= 0;
                        nlil01l <= 0;
                        nlil01O <= 0;
                        nlil10i <= 0;
                        nlil1li <= 0;
                        nlil1ll <= 0;
                        nlil1lO <= 0;
                        nlil1Oi <= 0;
                        nlil1Ol <= 0;
                        nlil1OO <= 0;
                        nlili1i <= 0;
                end
                else
                begin
                        n0lO0O <= (~ (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])));
                        n0lO1i <= n0lO0O;
                        n0O0iO <= (~ nli10OO);
                        n0O11i <= (~ ((~ (n0Oili ^ wire_n01ill_dout[0])) & (~ (n0OilO ^ wire_n01ill_dout[1]))));
                        n0Oi1i <= wire_n0Oi0l_dataout;
                        n0Oili <= wire_n01ill_dout[0];
                        nlil01i <= wire_nlil0lO_dataout;
                        nlil01l <= wire_nlil0Oi_dataout;
                        nlil01O <= nlili1i;
                        nlil10i <= wire_nlil00i_dataout;
                        nlil1li <= wire_nlil00l_dataout;
                        nlil1ll <= wire_nlil00O_dataout;
                        nlil1lO <= wire_nlil0ii_dataout;
                        nlil1Oi <= wire_nlil0il_dataout;
                        nlil1Ol <= wire_nlil0iO_dataout;
                        nlil1OO <= wire_nlil0ll_dataout;
                        nlili1i <= nl011O;
                end
        end
        initial
        begin
                n0O0li = 0;
                n0O0lO = 0;
                n0OilO = 0;
                nlil0OO = 0;
                nlil1il = 0;
                nlili1l = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0ll)
        begin
                if (nlii0ll == 1'b1)
                begin
                        n0O0li <= 1;
                        n0O0lO <= 1;
                        n0OilO <= 1;
                        nlil0OO <= 1;
                        nlil1il <= 1;
                        nlili1l <= 1;
                end
                else
                begin
                        n0O0li <= nli10OO;
                        n0O0lO <= ((nlii0ll | n0O11i) | n01i0O);
                        n0OilO <= wire_n01ill_dout[1];
                        nlil0OO <= nlili1l;
                        nlil1il <= wire_nlil10l_dataout;
                        nlili1l <= nl010i;
                end
        end
        event n0O0li_event;
        event n0O0lO_event;
        event n0OilO_event;
        event nlil0OO_event;
        event nlil1il_event;
        event nlili1l_event;
        initial
                #1 ->n0O0li_event;
        initial
                #1 ->n0O0lO_event;
        initial
                #1 ->n0OilO_event;
        initial
                #1 ->nlil0OO_event;
        initial
                #1 ->nlil1il_event;
        initial
                #1 ->nlili1l_event;
        always @(n0O0li_event)
                n0O0li <= 1;
        always @(n0O0lO_event)
                n0O0lO <= 1;
        always @(n0OilO_event)
                n0OilO <= 1;
        always @(nlil0OO_event)
                nlil0OO <= 1;
        always @(nlil1il_event)
                nlil1il <= 1;
        always @(nlili1l_event)
                nlili1l <= 1;
        initial
        begin
                n01i0O = 0;
                n01iii = 0;
                n0OiOi = 0;
                n0OiOl = 0;
                n0OiOO = 0;
                n0Ol1l = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlilOl)
        begin
                if (nlilOl == 1'b1)
                begin
                        n01i0O <= 1;
                        n01iii <= 1;
                        n0OiOi <= 1;
                        n0OiOl <= 1;
                        n0OiOO <= 1;
                        n0Ol1l <= 1;
                end
                else
                begin
                        n01i0O <= n01iii;
                        n01iii <= nlii0iO;
                        n0OiOi <= n0OiOl;
                        n0OiOl <= nlii0iO;
                        n0OiOO <= n0Ol1l;
                        n0Ol1l <= nlii0iO;
                end
        end
        event n01i0O_event;
        event n01iii_event;
        event n0OiOi_event;
        event n0OiOl_event;
        event n0OiOO_event;
        event n0Ol1l_event;
        initial
                #1 ->n01i0O_event;
        initial
                #1 ->n01iii_event;
        initial
                #1 ->n0OiOi_event;
        initial
                #1 ->n0OiOl_event;
        initial
                #1 ->n0OiOO_event;
        initial
                #1 ->n0Ol1l_event;
        always @(n01i0O_event)
                n01i0O <= 1;
        always @(n01iii_event)
                n01iii <= 1;
        always @(n0OiOi_event)
                n0OiOi <= 1;
        always @(n0OiOl_event)
                n0OiOl <= 1;
        always @(n0OiOO_event)
                n0OiOO <= 1;
        always @(n0Ol1l_event)
                n0Ol1l <= 1;
        initial
        begin
                n0Ol0i = 0;
                n0Ol0l = 0;
                n0Ol0O = 0;
                n0Ol1O = 0;
                n0Olii = 0;
                n0Olil = 0;
                n0OliO = 0;
                n0Olli = 0;
                n0Olll = 0;
                n0OO1l = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0li)
        begin
                if (nlii0li == 1'b1)
                begin
                        n0Ol0i <= 0;
                        n0Ol0l <= 0;
                        n0Ol0O <= 0;
                        n0Ol1O <= 0;
                        n0Olii <= 0;
                        n0Olil <= 0;
                        n0OliO <= 0;
                        n0Olli <= 0;
                        n0Olll <= 0;
                        n0OO1l <= 0;
                end
                else if  (niO1ii == 1'b1)
                begin
                        n0Ol0i <= n0OlOO;
                        n0Ol0l <= n0OO1O;
                        n0Ol0O <= n0OO0i;
                        n0Ol1O <= n0OllO;
                        n0Olii <= n0OO0l;
                        n0Olil <= n0OO0O;
                        n0OliO <= n0OOii;
                        n0Olli <= n0OOil;
                        n0Olll <= n0OOiO;
                        n0OO1l <= (ni1lOi | ni1llO);
                end
        end
        initial
        begin
                n110l = 0;
                n11ii = 0;
                nl010i = 0;
                nllllO = 0;
                nlOOll = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        n110l <= 1;
                        n11ii <= 1;
                        nl010i <= 1;
                        nllllO <= 1;
                        nlOOll <= 1;
                end
                else
                begin
                        n110l <= n11ii;
                        n11ii <= nlii0iO;
                        nl010i <= wire_nl01il_dataout;
                        nllllO <= (~ nlOOli);
                        nlOOll <= wire_nlOilO_o;
                end
        end
        event n110l_event;
        event n11ii_event;
        event nl010i_event;
        event nllllO_event;
        event nlOOll_event;
        initial
                #1 ->n110l_event;
        initial
                #1 ->n11ii_event;
        initial
                #1 ->nl010i_event;
        initial
                #1 ->nllllO_event;
        initial
                #1 ->nlOOll_event;
        always @(n110l_event)
                n110l <= 1;
        always @(n11ii_event)
                n11ii <= 1;
        always @(nl010i_event)
                nl010i <= 1;
        always @(nllllO_event)
                nllllO <= 1;
        always @(nlOOll_event)
                nlOOll <= 1;
        initial
        begin
                n11il = 0;
                n11iO = 0;
                n11li = 0;
                n11ll = 0;
                n11lO = 0;
                n11Ol = 0;
        end
        always @ ( posedge clk or  negedge wire_n11Oi_CLRN)
        begin
                if (wire_n11Oi_CLRN == 1'b0)
                begin
                        n11il <= 0;
                        n11iO <= 0;
                        n11li <= 0;
                        n11ll <= 0;
                        n11lO <= 0;
                        n11Ol <= 0;
                end
                else
                begin
                        n11il <= reconfig_busy;
                        n11iO <= ((~ n1l1i) & wire_nl00O_freqlocked);
                        n11li <= wire_nli1l_dataout;
                        n11ll <= n11li;
                        n11lO <= n11il;
                        n11Ol <= n11iO;
                end
        end
        assign
                wire_n11Oi_CLRN = (nli000i56 ^ nli000i55);
        initial
        begin
                ni00ll = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0i)
        begin
                if (nili0i == 1'b1)
                begin
                        ni00ll <= 1;
                end
                else if  (nii0Ol == 1'b1)
                begin
                        ni00ll <= wire_ni0i1i_dataout;
                end
        end
        event ni00ll_event;
        initial
                #1 ->ni00ll_event;
        always @(ni00ll_event)
                ni00ll <= 1;
        initial
        begin
                ni001i = 0;
                ni001l = 0;
                ni001O = 0;
                ni00ii = 0;
                ni00il = 0;
                ni00iO = 0;
                ni00lO = 0;
                ni00Oi = 0;
                ni00OO = 0;
                ni01Ol = 0;
                ni01OO = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0i)
        begin
                if (nili0i == 1'b1)
                begin
                        ni001i <= 0;
                        ni001l <= 0;
                        ni001O <= 0;
                        ni00ii <= 0;
                        ni00il <= 0;
                        ni00iO <= 0;
                        ni00lO <= 0;
                        ni00Oi <= 0;
                        ni00OO <= 0;
                        ni01Ol <= 0;
                        ni01OO <= 0;
                end
                else if  (nii0Ol == 1'b1)
                begin
                        ni001i <= ni00OO;
                        ni001l <= ni00ll;
                        ni001O <= (ni00lO ^ ni00ll);
                        ni00ii <= ni00lO;
                        ni00il <= ni00Oi;
                        ni00iO <= ni00OO;
                        ni00lO <= wire_ni0i1l_dataout;
                        ni00Oi <= wire_ni0i1O_dataout;
                        ni00OO <= wire_ni0i0i_dataout;
                        ni01Ol <= (ni00Oi ^ ni00lO);
                        ni01OO <= (ni00OO ^ ni00Oi);
                end
        end
        initial
        begin
                ni010i = 0;
                ni010l = 0;
                ni01ii = 0;
                ni1O0l = 0;
                ni1O0O = 0;
                ni1Oii = 0;
                ni1Oil = 0;
                ni1OiO = 0;
                ni1OOi = 0;
                ni1OOl = 0;
                ni1OOO = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0l)
        begin
                if (nili0l == 1'b1)
                begin
                        ni010i <= 0;
                        ni010l <= 0;
                        ni01ii <= 0;
                        ni1O0l <= 0;
                        ni1O0O <= 0;
                        ni1Oii <= 0;
                        ni1Oil <= 0;
                        ni1OiO <= 0;
                        ni1OOi <= 0;
                        ni1OOl <= 0;
                        ni1OOO <= 0;
                end
                else if  (nli1iii == 1'b1)
                begin
                        ni010i <= wire_ni01iO_dataout;
                        ni010l <= wire_ni01li_dataout;
                        ni01ii <= wire_ni01ll_dataout;
                        ni1O0l <= (ni010l ^ ni010i);
                        ni1O0O <= (ni01ii ^ ni010l);
                        ni1Oii <= ni01ii;
                        ni1Oil <= ni011l;
                        ni1OiO <= (ni010i ^ ni011l);
                        ni1OOi <= ni010i;
                        ni1OOl <= ni010l;
                        ni1OOO <= ni01ii;
                end
        end
        initial
        begin
                ni011l = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0l)
        begin
                if (nili0l == 1'b1)
                begin
                        ni011l <= 1;
                end
                else if  (nli1iii == 1'b1)
                begin
                        ni011l <= wire_ni01il_dataout;
                end
        end
        event ni011l_event;
        initial
                #1 ->ni011l_event;
        always @(ni011l_event)
                ni011l <= 1;
        initial
        begin
                ni0lli = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0i)
        begin
                if (nili0i == 1'b1)
                begin
                        ni0lli <= 0;
                end
                else if  (ni0lii == 1'b0)
                begin
                        ni0lli <= nlii0lO;
                end
        end
        initial
        begin
                ni0l0i = 0;
                ni0l0l = 0;
                ni0l0O = 0;
                ni0l1l = 0;
                ni0O0O = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0l)
        begin
                if (nili0l == 1'b1)
                begin
                        ni0l0i <= 0;
                        ni0l0l <= 0;
                        ni0l0O <= 0;
                        ni0l1l <= 0;
                        ni0O0O <= 0;
                end
                else if  (nliil0l == 1'b1)
                begin
                        ni0l0i <= wire_ni0lil_o[2];
                        ni0l0l <= wire_ni0lil_o[3];
                        ni0l0O <= wire_ni0lil_o[4];
                        ni0l1l <= wire_ni0lil_o[1];
                        ni0O0O <= wire_ni0OOl_o;
                end
        end
        initial
        begin
                ni1i1l = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0li)
        begin
                if (nlii0li == 1'b1)
                begin
                        ni1i1l <= 1;
                end
                else if  (nliil0l == 1'b1)
                begin
                        ni1i1l <= wire_ni101l_o;
                end
        end
        event ni1i1l_event;
        initial
                #1 ->ni1i1l_event;
        always @(ni1i1l_event)
                ni1i1l <= 1;
        initial
        begin
                ni0OOi = 0;
                ni0OOO = 0;
                nii10i = 0;
                nii10l = 0;
                nii11i = 0;
                nii11l = 0;
                nii11O = 0;
                nii1ii = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0l)
        begin
                if (nili0l == 1'b1)
                begin
                        ni0OOi <= 0;
                        ni0OOO <= 0;
                        nii10i <= 0;
                        nii10l <= 0;
                        nii11i <= 0;
                        nii11l <= 0;
                        nii11O <= 0;
                        nii1ii <= 0;
                end
                else
                begin
                        ni0OOi <= (((nii1ii ^ nii11O) ^ nii10l) ^ nii10i);
                        ni0OOO <= ((nii1ii ^ nii10i) ^ nii10l);
                        nii10i <= ni01Ol;
                        nii10l <= ni01OO;
                        nii11i <= (nii1ii ^ nii10l);
                        nii11l <= nii1ii;
                        nii11O <= ni001O;
                        nii1ii <= ni001i;
                end
        end
        initial
        begin
                ni0lll = 0;
                ni0lOi = 0;
                ni0lOl = 0;
                ni0lOO = 0;
                ni0O0i = 0;
                ni0O1i = 0;
                ni0O1l = 0;
                ni0O1O = 0;
                nii00l = 0;
                nii00O = 0;
                nii0ii = 0;
                nii0il = 0;
                nii0iO = 0;
                nii0li = 0;
                nii0ll = 0;
                nii0lO = 0;
                nii0Oi = 0;
                nii0Ol = 0;
                nii0OO = 0;
                niii0l = 0;
                niii0O = 0;
                niii1l = 0;
                niiiii = 0;
                niiiil = 0;
                niiiiO = 0;
                niiili = 0;
                niiill = 0;
                niiilO = 0;
                nil00i = 0;
                nil01l = 0;
                nil01O = 0;
                nil0ii = 0;
                nil1Ol = 0;
                nil1OO = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0i)
        begin
                if (nili0i == 1'b1)
                begin
                        ni0lll <= 0;
                        ni0lOi <= 0;
                        ni0lOl <= 0;
                        ni0lOO <= 0;
                        ni0O0i <= 0;
                        ni0O1i <= 0;
                        ni0O1l <= 0;
                        ni0O1O <= 0;
                        nii00l <= 0;
                        nii00O <= 0;
                        nii0ii <= 0;
                        nii0il <= 0;
                        nii0iO <= 0;
                        nii0li <= 0;
                        nii0ll <= 0;
                        nii0lO <= 0;
                        nii0Oi <= 0;
                        nii0Ol <= 0;
                        nii0OO <= 0;
                        niii0l <= 0;
                        niii0O <= 0;
                        niii1l <= 0;
                        niiiii <= 0;
                        niiiil <= 0;
                        niiiiO <= 0;
                        niiili <= 0;
                        niiill <= 0;
                        niiilO <= 0;
                        nil00i <= 0;
                        nil01l <= 0;
                        nil01O <= 0;
                        nil0ii <= 0;
                        nil1Ol <= 0;
                        nil1OO <= 0;
                end
                else
                begin
                        ni0lll <= (((ni0O0i ^ ni0O1i) ^ ni0O1O) ^ ni0O1l);
                        ni0lOi <= ((ni0O0i ^ ni0O1l) ^ ni0O1O);
                        ni0lOl <= (ni0O0i ^ ni0O1O);
                        ni0lOO <= ni0O0i;
                        ni0O0i <= ni1Oii;
                        ni0O1i <= ni1OiO;
                        ni0O1l <= ni1O0l;
                        ni0O1O <= ni1O0O;
                        nii00l <= wire_ni0iOO_dataout;
                        nii00O <= wire_ni0iii_dataout;
                        nii0ii <= wire_ni0iil_dataout;
                        nii0il <= wire_ni0iiO_dataout;
                        nii0iO <= wire_ni0ili_dataout;
                        nii0li <= wire_ni0ill_dataout;
                        nii0ll <= wire_ni0ilO_dataout;
                        nii0lO <= wire_ni0iOi_dataout;
                        nii0Oi <= wire_ni0iOl_dataout;
                        nii0Ol <= wire_niii1i_dataout;
                        nii0OO <= wire_niii1O_dataout;
                        niii0l <= wire_ni0l1i_dataout;
                        niii0O <= wire_niiiOl_dataout;
                        niii1l <= wire_niiiOi_dataout;
                        niiiii <= wire_niiiOO_dataout;
                        niiiil <= wire_niil1i_dataout;
                        niiiiO <= wire_niil1l_dataout;
                        niiili <= wire_niil1O_dataout;
                        niiill <= wire_niil0i_dataout;
                        niiilO <= wire_niiOOi_o;
                        nil00i <= nil0ii;
                        nil01l <= nil01O;
                        nil01O <= n0OiOO;
                        nil0ii <= nl011O;
                        nil1Ol <= wire_niiOOO_o;
                        nil1OO <= wire_nil11l_o;
                end
        end
        initial
        begin
                ni0lii = 0;
                nil00l = 0;
                nil01i = 0;
                nil0iO = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nili0i)
        begin
                if (nili0i == 1'b1)
                begin
                        ni0lii <= 1;
                        nil00l <= 1;
                        nil01i <= 1;
                        nil0iO <= 1;
                end
                else
                begin
                        ni0lii <= wire_ni0llO_o;
                        nil00l <= nil0iO;
                        nil01i <= wire_nil10i_o;
                        nil0iO <= nl010i;
                end
        end
        event ni0lii_event;
        event nil00l_event;
        event nil01i_event;
        event nil0iO_event;
        initial
                #1 ->ni0lii_event;
        initial
                #1 ->nil00l_event;
        initial
                #1 ->nil01i_event;
        initial
                #1 ->nil0iO_event;
        always @(ni0lii_event)
                ni0lii <= 1;
        always @(nil00l_event)
                nil00l <= 1;
        always @(nil01i_event)
                nil01i <= 1;
        always @(nil0iO_event)
                nil0iO <= 1;
        initial
        begin
                n011il = 0;
                n1i00i = 0;
                n1i00l = 0;
                n1i00O = 0;
                n1i0ii = 0;
                n1i0iO = 0;
                n1i1il = 0;
                n1i1lO = 0;
                nili0i = 0;
                nili0l = 0;
                niO00i = 0;
                niO01l = 0;
                niO0ii = 0;
                niO1ll = 0;
                niO1Oi = 0;
                niO1OO = 0;
                nliil0l = 0;
                nliiOlO = 0;
                nliiOOl = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0li)
        begin
                if (nlii0li == 1'b1)
                begin
                        n011il <= 1;
                        n1i00i <= 1;
                        n1i00l <= 1;
                        n1i00O <= 1;
                        n1i0ii <= 1;
                        n1i0iO <= 1;
                        n1i1il <= 1;
                        n1i1lO <= 1;
                        nili0i <= 1;
                        nili0l <= 1;
                        niO00i <= 1;
                        niO01l <= 1;
                        niO0ii <= 1;
                        niO1ll <= 1;
                        niO1Oi <= 1;
                        niO1OO <= 1;
                        nliil0l <= 1;
                        nliiOlO <= 1;
                        nliiOOl <= 1;
                end
                else
                begin
                        n011il <= wire_n010iO_dataout;
                        n1i00i <= wire_n1i0Ol_dataout;
                        n1i00l <= wire_n1i0OO_dataout;
                        n1i00O <= wire_n1ii1i_dataout;
                        n1i0ii <= wire_n1ii1l_dataout;
                        n1i0iO <= wire_n1ii0i_dataout;
                        n1i1il <= wire_n1i1Oi_dataout;
                        n1i1lO <= wire_n1i0ll_dataout;
                        nili0i <= ((nlii0li | nili1O) | n0OiOO);
                        nili0l <= ((nlii0li | nili1l) | n0OiOi);
                        niO00i <= niO0ii;
                        niO01l <= niO00i;
                        niO0ii <= nl010i;
                        niO1ll <= niO1Oi;
                        niO1Oi <= niO1OO;
                        niO1OO <= nl010i;
                        nliil0l <= wire_nliil1l_dataout;
                        nliiOlO <= nliiOOl;
                        nliiOOl <= nl010i;
                end
        end
        event n011il_event;
        event n1i00i_event;
        event n1i00l_event;
        event n1i00O_event;
        event n1i0ii_event;
        event n1i0iO_event;
        event n1i1il_event;
        event n1i1lO_event;
        event nili0i_event;
        event nili0l_event;
        event niO00i_event;
        event niO01l_event;
        event niO0ii_event;
        event niO1ll_event;
        event niO1Oi_event;
        event niO1OO_event;
        event nliil0l_event;
        event nliiOlO_event;
        event nliiOOl_event;
        initial
                #1 ->n011il_event;
        initial
                #1 ->n1i00i_event;
        initial
                #1 ->n1i00l_event;
        initial
                #1 ->n1i00O_event;
        initial
                #1 ->n1i0ii_event;
        initial
                #1 ->n1i0iO_event;
        initial
                #1 ->n1i1il_event;
        initial
                #1 ->n1i1lO_event;
        initial
                #1 ->nili0i_event;
        initial
                #1 ->nili0l_event;
        initial
                #1 ->niO00i_event;
        initial
                #1 ->niO01l_event;
        initial
                #1 ->niO0ii_event;
        initial
                #1 ->niO1ll_event;
        initial
                #1 ->niO1Oi_event;
        initial
                #1 ->niO1OO_event;
        initial
                #1 ->nliil0l_event;
        initial
                #1 ->nliiOlO_event;
        initial
                #1 ->nliiOOl_event;
        always @(n011il_event)
                n011il <= 1;
        always @(n1i00i_event)
                n1i00i <= 1;
        always @(n1i00l_event)
                n1i00l <= 1;
        always @(n1i00O_event)
                n1i00O <= 1;
        always @(n1i0ii_event)
                n1i0ii <= 1;
        always @(n1i0iO_event)
                n1i0iO <= 1;
        always @(n1i1il_event)
                n1i1il <= 1;
        always @(n1i1lO_event)
                n1i1lO <= 1;
        always @(nili0i_event)
                nili0i <= 1;
        always @(nili0l_event)
                nili0l <= 1;
        always @(niO00i_event)
                niO00i <= 1;
        always @(niO01l_event)
                niO01l <= 1;
        always @(niO0ii_event)
                niO0ii <= 1;
        always @(niO1ll_event)
                niO1ll <= 1;
        always @(niO1Oi_event)
                niO1Oi <= 1;
        always @(niO1OO_event)
                niO1OO <= 1;
        always @(nliil0l_event)
                nliil0l <= 1;
        always @(nliiOlO_event)
                nliiOlO <= 1;
        always @(nliiOOl_event)
                nliiOOl <= 1;
        initial
        begin
                n0OllO = 0;
                n0OlOl = 0;
                n0OlOO = 0;
                n0OO0i = 0;
                n0OO0l = 0;
                n0OO0O = 0;
                n0OO1O = 0;
                n0OOii = 0;
                n0OOil = 0;
                n0OOiO = 0;
                n0OOli = 0;
                ni10Ol = 0;
                ni10OO = 0;
                ni1i0i = 0;
                ni1i0l = 0;
                ni1i0O = 0;
                ni1i1O = 0;
                ni1iii = 0;
                ni1iil = 0;
                ni1iiO = 0;
                ni1ili = 0;
                ni1ill = 0;
                ni1ilO = 0;
                ni1iOi = 0;
                ni1iOl = 0;
                ni1iOO = 0;
                ni1l0i = 0;
                ni1l0l = 0;
                ni1l0O = 0;
                ni1l1i = 0;
                ni1l1l = 0;
                ni1l1O = 0;
                ni1lii = 0;
                ni1lil = 0;
                ni1liO = 0;
                ni1lli = 0;
                ni1lll = 0;
                ni1llO = 0;
                ni1lOi = 0;
                ni1lOl = 0;
                ni1lOO = 0;
                ni1O1i = 0;
                ni1O1l = 0;
                ni1O1O = 0;
                nill0l = 0;
                nilOOi = 0;
                nilOOl = 0;
                nilOOO = 0;
                niO0il = 0;
                niO0li = 0;
                niO10i = 0;
                niO10l = 0;
                niO10O = 0;
                niO11i = 0;
                niO11l = 0;
                niO11O = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nlii0li)
        begin
                if (nlii0li == 1'b1)
                begin
                        n0OllO <= 0;
                        n0OlOl <= 0;
                        n0OlOO <= 0;
                        n0OO0i <= 0;
                        n0OO0l <= 0;
                        n0OO0O <= 0;
                        n0OO1O <= 0;
                        n0OOii <= 0;
                        n0OOil <= 0;
                        n0OOiO <= 0;
                        n0OOli <= 0;
                        ni10Ol <= 0;
                        ni10OO <= 0;
                        ni1i0i <= 0;
                        ni1i0l <= 0;
                        ni1i0O <= 0;
                        ni1i1O <= 0;
                        ni1iii <= 0;
                        ni1iil <= 0;
                        ni1iiO <= 0;
                        ni1ili <= 0;
                        ni1ill <= 0;
                        ni1ilO <= 0;
                        ni1iOi <= 0;
                        ni1iOl <= 0;
                        ni1iOO <= 0;
                        ni1l0i <= 0;
                        ni1l0l <= 0;
                        ni1l0O <= 0;
                        ni1l1i <= 0;
                        ni1l1l <= 0;
                        ni1l1O <= 0;
                        ni1lii <= 0;
                        ni1lil <= 0;
                        ni1liO <= 0;
                        ni1lli <= 0;
                        ni1lll <= 0;
                        ni1llO <= 0;
                        ni1lOi <= 0;
                        ni1lOl <= 0;
                        ni1lOO <= 0;
                        ni1O1i <= 0;
                        ni1O1l <= 0;
                        ni1O1O <= 0;
                        nill0l <= 0;
                        nilOOi <= 0;
                        nilOOl <= 0;
                        nilOOO <= 0;
                        niO0il <= 0;
                        niO0li <= 0;
                        niO10i <= 0;
                        niO10l <= 0;
                        niO10O <= 0;
                        niO11i <= 0;
                        niO11l <= 0;
                        niO11O <= 0;
                end
                else if  (nliil0l == 1'b1)
                begin
                        n0OllO <= n0OlOl;
                        n0OlOl <= nli1i1l;
                        n0OlOO <= wire_n0OOll_dataout;
                        n0OO0i <= wire_n0OOOi_dataout;
                        n0OO0l <= wire_n0OOOl_dataout;
                        n0OO0O <= wire_n0OOOO_dataout;
                        n0OO1O <= wire_n0OOlO_dataout;
                        n0OOii <= wire_ni111i_dataout;
                        n0OOil <= wire_ni111l_dataout;
                        n0OOiO <= wire_ni111O_dataout;
                        n0OOli <= wire_ni11lO_o;
                        ni10Ol <= wire_ni11Oi_o;
                        ni10OO <= wire_ni11OO_o;
                        ni1i0i <= ni1ilO;
                        ni1i0l <= ni1iOi;
                        ni1i0O <= ni1iOl;
                        ni1i1O <= ni1ill;
                        ni1iii <= ni1iOO;
                        ni1iil <= ni1l1i;
                        ni1iiO <= ni1l1l;
                        ni1ili <= ni1l1O;
                        ni1ill <= ni1iOO;
                        ni1ilO <= ni1l1i;
                        ni1iOi <= ni1l1l;
                        ni1iOl <= ni1l1O;
                        ni1iOO <= ni1lOO;
                        ni1l0i <= ni1lil;
                        ni1l0l <= ni1liO;
                        ni1l0O <= ni1lli;
                        ni1l1i <= ni1O1i;
                        ni1l1l <= ni1O1l;
                        ni1l1O <= ni1O1O;
                        ni1lii <= ni1lll;
                        ni1lil <= ni1lOO;
                        ni1liO <= ni1O1i;
                        ni1lli <= ni1O1l;
                        ni1lll <= ni1O1O;
                        ni1llO <= ni1lOi;
                        ni1lOi <= mii_tx_err;
                        ni1lOl <= mii_tx_en;
                        ni1lOO <= mii_tx_d[0];
                        ni1O1i <= mii_tx_d[1];
                        ni1O1l <= mii_tx_d[2];
                        ni1O1O <= mii_tx_d[3];
                        nill0l <= gmii_tx_d[0];
                        nilOOi <= gmii_tx_d[1];
                        nilOOl <= gmii_tx_d[2];
                        nilOOO <= gmii_tx_d[3];
                        niO0il <= wire_niOi1i_dataout;
                        niO0li <= niO0il;
                        niO10i <= gmii_tx_d[7];
                        niO10l <= gmii_tx_en;
                        niO10O <= gmii_tx_err;
                        niO11i <= gmii_tx_d[4];
                        niO11l <= gmii_tx_d[5];
                        niO11O <= gmii_tx_d[6];
                end
        end
        initial
        begin
                n0O1i = 0;
                niO0O = 0;
                niOiO = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  negedge wire_niOil_PRN)
        begin
                if (wire_niOil_PRN == 1'b0)
                begin
                        n0O1i <= 1;
                        niO0O <= 1;
                        niOiO <= 1;
                end
                else
                begin
                        n0O1i <= (~ ((((((((((((((((((((nl10i & ((nl1ii & ((nl10l & (nl10O & (nl1il & nlii1Oi))) & (nlii1ll24 ^ nlii1ll23))) & (nlii1iO26 ^ nlii1iO25))) & (~ n0lil)) | ((nl10i & (nl10O & ((nl1il & nlii1il) & (nlii10O28 ^ nlii10O27)))) & (nlii10i30 ^ nlii10i29))) | (~ (nlii11l32 ^ nlii11l31))) | (((~ nl10i) & (nl10O & ((nl1il & nlii11i) & (nli0OOl34 ^ nli0OOl33)))) & (nli0OlO36 ^ nli0OlO35))) | ((~ nl10i) & ((~ nl10O) & ((nl1il & nli0Oll) & (nli0OiO38 ^ nli0OiO37))))) | (~ (nli0Oii40 ^ nli0Oii39))) | (((~ nl10i) & ((~ nl10O) & (nl1il & nli0O0O))) & (nli0O0i42 ^ nli0O0i41))) | (~ (nli0O1l44 ^ nli0O1l43))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0O1i)))) | ((nl11O & (((~ nl10i) & ((~ nl10O) & ((nl1il & nli0lOO) & (nli0lOi46 ^ nli0lOi45)))) & (nli0lll48 ^ nli0lll47))) & (nli0liO50 ^ nli0liO49))) | (~ (nli0lii52 ^ nli0lii51))) | ((nl11O & (((~ nl10i) & ((~ nl10O) & (nl1il & nli0l0O))) & (nli0l0i54 ^ nli0l0i53))) & n0lil)) | ((nl11O & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0l1O)))) & ((nl1ii & nli0l1l) | ((~ nl1ii) & nli0l1i)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOO)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOl)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOi)))) | ((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0ilO))))) | ((((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0ill)))) & n0lil) & nli0ili)) | (((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iiO)))) & nli0ili)));
                        niO0O <= nl10l;
                        niOiO <= nl1ii;
                end
        end
        assign
                wire_niOil_PRN = ((nlii01i20 ^ nlii01i19) & (~ n0i0l));
        event n0O1i_event;
        event niO0O_event;
        event niOiO_event;
        initial
                #1 ->n0O1i_event;
        initial
                #1 ->niO0O_event;
        initial
                #1 ->niOiO_event;
        always @(n0O1i_event)
                n0O1i <= 1;
        always @(niO0O_event)
                niO0O <= 1;
        always @(niOiO_event)
                niOiO <= 1;
        initial
        begin
                nl00ii = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl00ii <= 0;
                end
                else if  (wire_nl000O_ENA == 1'b1)
                begin
                        nl00ii <= nlO01i;
                end
        end
        assign
                wire_nl000O_ENA = (nli1lil & nlO1OO);
        initial
        begin
                n0lil = 0;
                niO1i = 0;
                niOii = 0;
                niOli = 0;
                niOll = 0;
                niOlO = 0;
                niOOi = 0;
                niOOl = 0;
                niOOO = 0;
                nl01l = 0;
                nl10i = 0;
                nl10l = 0;
                nl10O = 0;
                nl11i = 0;
                nl11l = 0;
                nl11O = 0;
                nl1ii = 0;
                nl1il = 0;
                nl1iO = 0;
                nl1li = 0;
                nl1ll = 0;
                nl1lO = 0;
                nl1Oi = 0;
                nl1Ol = 0;
                nl1OO = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  negedge wire_nl01i_CLRN)
        begin
                if (wire_nl01i_CLRN == 1'b0)
                begin
                        n0lil <= 0;
                        niO1i <= 0;
                        niOii <= 0;
                        niOli <= 0;
                        niOll <= 0;
                        niOlO <= 0;
                        niOOi <= 0;
                        niOOl <= 0;
                        niOOO <= 0;
                        nl01l <= 0;
                        nl10i <= 0;
                        nl10l <= 0;
                        nl10O <= 0;
                        nl11i <= 0;
                        nl11l <= 0;
                        nl11O <= 0;
                        nl1ii <= 0;
                        nl1il <= 0;
                        nl1iO <= 0;
                        nl1li <= 0;
                        nl1ll <= 0;
                        nl1lO <= 0;
                        nl1Oi <= 0;
                        nl1Ol <= 0;
                        nl1OO <= 0;
                end
                else
                begin
                        n0lil <= wire_niO1l_dataout;
                        niO1i <= nl1il;
                        niOii <= nl10O;
                        niOli <= nl1iO;
                        niOll <= nl1li;
                        niOlO <= nl1ll;
                        niOOi <= nl1lO;
                        niOOl <= nl1Oi;
                        niOOO <= nl1Ol;
                        nl01l <= wire_nl0ii_dataout[7];
                        nl10i <= wire_nl0ii_patterndetect[0];
                        nl10l <= wire_nl0ii_errdetect[0];
                        nl10O <= wire_nl0ii_ctrldetect[0];
                        nl11i <= nl1OO;
                        nl11l <= nl01l;
                        nl11O <= wire_nl0ii_runningdisp[0];
                        nl1ii <= wire_nl0ii_disperr[0];
                        nl1il <= wire_nl0ii_syncstatus[0];
                        nl1iO <= wire_nl0ii_dataout[0];
                        nl1li <= wire_nl0ii_dataout[1];
                        nl1ll <= wire_nl0ii_dataout[2];
                        nl1lO <= wire_nl0ii_dataout[3];
                        nl1Oi <= wire_nl0ii_dataout[4];
                        nl1Ol <= wire_nl0ii_dataout[5];
                        nl1OO <= wire_nl0ii_dataout[6];
                end
        end
        assign
                wire_nl01i_CLRN = ((nlii01l18 ^ nlii01l17) & (~ n0i0l));
        initial
        begin
                nl00ll = 0;
                nl00Oi = 0;
                nl00Ol = 0;
                nl00OO = 0;
                nl0i1i = 0;
                nl0i1O = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl00ll <= 0;
                        nl00Oi <= 0;
                        nl00Ol <= 0;
                        nl00OO <= 0;
                        nl0i1i <= 0;
                        nl0i1O <= 0;
                end
                else if  (nli1lli == 1'b1)
                begin
                        nl00ll <= nlO01i;
                        nl00Oi <= nlO01l;
                        nl00Ol <= nlO01O;
                        nl00OO <= nlO00i;
                        nl0i1i <= nlO00l;
                        nl0i1O <= nlO00O;
                end
        end
        initial
        begin
                nl0i0i = 0;
                nl0i0O = 0;
                nl0iii = 0;
                nl0iiO = 0;
                nl0ilO = 0;
                nl0iOl = 0;
                nl0iOO = 0;
                nl0l0i = 0;
                nl0l0O = 0;
                nl0l1O = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl0i0i <= 0;
                        nl0i0O <= 0;
                        nl0iii <= 0;
                        nl0iiO <= 0;
                        nl0ilO <= 0;
                        nl0iOl <= 0;
                        nl0iOO <= 0;
                        nl0l0i <= 0;
                        nl0l0O <= 0;
                        nl0l1O <= 0;
                end
                else if  (nli1O1i == 1'b1)
                begin
                        nl0i0i <= nlO01l;
                        nl0i0O <= nlO01O;
                        nl0iii <= nlO00i;
                        nl0iiO <= nlO00O;
                        nl0ilO <= nlO0iO;
                        nl0iOl <= nlO0ll;
                        nl0iOO <= nlO0lO;
                        nl0l0i <= nlO0OO;
                        nl0l0O <= nlOi1i;
                        nl0l1O <= nlO0Ol;
                end
        end
        initial
        begin
                nl0iil = 0;
                nl0ili = 0;
                nl0ill = 0;
                nl0iOi = 0;
                nl0l1l = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl0iil <= 1;
                        nl0ili <= 1;
                        nl0ill <= 1;
                        nl0iOi <= 1;
                        nl0l1l <= 1;
                end
                else if  (nli1O1i == 1'b1)
                begin
                        nl0iil <= nlO00l;
                        nl0ili <= nlO0ii;
                        nl0ill <= nlO0il;
                        nl0iOi <= nlO0li;
                        nl0l1l <= nlO0Oi;
                end
        end
        event nl0iil_event;
        event nl0ili_event;
        event nl0ill_event;
        event nl0iOi_event;
        event nl0l1l_event;
        initial
                #1 ->nl0iil_event;
        initial
                #1 ->nl0ili_event;
        initial
                #1 ->nl0ill_event;
        initial
                #1 ->nl0iOi_event;
        initial
                #1 ->nl0l1l_event;
        always @(nl0iil_event)
                nl0iil <= 1;
        always @(nl0ili_event)
                nl0ili <= 1;
        always @(nl0ill_event)
                nl0ill <= 1;
        always @(nl0iOi_event)
                nl0iOi <= 1;
        always @(nl0l1l_event)
                nl0l1l <= 1;
        initial
        begin
                nl0li = 0;
                nl0lO = 0;
        end
        always @ ( negedge reconfig_clk or  negedge wire_nl0ll_PRN)
        begin
                if (wire_nl0ll_PRN == 1'b0)
                begin
                        nl0li <= 1;
                        nl0lO <= 1;
                end
                else
                begin
                        nl0li <= reconfig_togxb[3];
                        nl0lO <= nl0li;
                end
        end
        assign
                wire_nl0ll_PRN = (nlii01O16 ^ nlii01O15);
        initial
        begin
                nl0liO = 0;
                nl0lll = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl0liO <= 0;
                        nl0lll <= 0;
                end
                else if  (nli1lOl == 1'b1)
                begin
                        nl0liO <= nlO01O;
                        nl0lll <= nlO00i;
                end
        end
        initial
        begin
                nl0lii = 0;
                nl0lil = 0;
                nl0lOi = 0;
        end
        always @ (clk or wire_nl0llO_PRN or wire_nl0llO_CLRN)
        begin
                if (wire_nl0llO_PRN == 1'b0)
                begin
                        nl0lii <= 1;
                        nl0lil <= 1;
                        nl0lOi <= 1;
                end
                else if  (wire_nl0llO_CLRN == 1'b0)
                begin
                        nl0lii <= 0;
                        nl0lil <= 0;
                        nl0lOi <= 0;
                end
                else if  (nli1lOl == 1'b1)
                if (clk != nl0llO_clk_prev && clk == 1'b1)
                begin
                        nl0lii <= nlO01i;
                        nl0lil <= nlO01l;
                        nl0lOi <= nlO00l;
                end
                nl0llO_clk_prev <= clk;
        end
        assign
                wire_nl0llO_CLRN = (nli1lOi78 ^ nli1lOi77),
                wire_nl0llO_PRN = ((nli1llO80 ^ nli1llO79) & (~ reset));
        event nl0lii_event;
        event nl0lil_event;
        event nl0lOi_event;
        initial
                #1 ->nl0lii_event;
        initial
                #1 ->nl0lil_event;
        initial
                #1 ->nl0lOi_event;
        always @(nl0lii_event)
                nl0lii <= 1;
        always @(nl0lil_event)
                nl0lil <= 1;
        always @(nl0lOi_event)
                nl0lOi <= 1;
        initial
        begin
                nl111i = 0;
                nl1i0l = 0;
                nl1i0O = 0;
                nl1iii = 0;
                nl1iil = 0;
                nl1iiO = 0;
                nl1ili = 0;
                nl1ill = 0;
                nl1ilO = 0;
                nl1iOi = 0;
                nl1iOl = 0;
                nl1iOO = 0;
                nl1l0l = 0;
                nl1l1i = 0;
                nl1l1l = 0;
                nl1l1O = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge nlili1O)
        begin
                if (nlili1O == 1'b1)
                begin
                        nl111i <= 0;
                        nl1i0l <= 0;
                        nl1i0O <= 0;
                        nl1iii <= 0;
                        nl1iil <= 0;
                        nl1iiO <= 0;
                        nl1ili <= 0;
                        nl1ill <= 0;
                        nl1ilO <= 0;
                        nl1iOi <= 0;
                        nl1iOl <= 0;
                        nl1iOO <= 0;
                        nl1l0l <= 0;
                        nl1l1i <= 0;
                        nl1l1l <= 0;
                        nl1l1O <= 0;
                end
                else if  (nlli1O == 1'b1)
                begin
                        nl111i <= wire_nl1lii_dataout;
                        nl1i0l <= wire_nl1lil_dataout;
                        nl1i0O <= wire_nl1liO_dataout;
                        nl1iii <= wire_nl1lli_dataout;
                        nl1iil <= wire_nl1lll_dataout;
                        nl1iiO <= wire_nl1llO_dataout;
                        nl1ili <= wire_nl1lOi_dataout;
                        nl1ill <= wire_nl1lOl_dataout;
                        nl1ilO <= wire_nl1lOO_dataout;
                        nl1iOi <= wire_nl1O1i_dataout;
                        nl1iOl <= wire_nl1O1l_dataout;
                        nl1iOO <= wire_nl1O1O_dataout;
                        nl1l0l <= wire_nl1Oii_dataout;
                        nl1l1i <= wire_nl1O0i_dataout;
                        nl1l1l <= wire_nl1O0l_dataout;
                        nl1l1O <= wire_nl1O0O_dataout;
                end
        end
        initial
        begin
                nli0O = 0;
        end
        always @ (clk or wire_nli0l_PRN or wire_nli0l_CLRN)
        begin
                if (wire_nli0l_PRN == 1'b0)
                begin
                        nli0O <= 1;
                end
                else if  (wire_nli0l_CLRN == 1'b0)
                begin
                        nli0O <= 0;
                end
                else
                if (clk != nli0l_clk_prev && clk == 1'b1)
                begin
                        nli0O <= nlii0iO;
                end
                nli0l_clk_prev <= clk;
        end
        assign
                wire_nli0l_CLRN = (nlii0il10 ^ nlii0il9),
                wire_nli0l_PRN = ((nlii0ii12 ^ nlii0ii11) & (~ n110l));
        event nli0O_event;
        initial
                #1 ->nli0O_event;
        always @(nli0O_event)
                nli0O <= 1;
        initial
        begin
                nl0lOl = 0;
                nl0O0i = 0;
                nl0O0l = 0;
                nl0O0O = 0;
                nl0O1l = 0;
                nl0O1O = 0;
                nl0Oii = 0;
                nl0Oil = 0;
                nl0OiO = 0;
                nl0Oli = 0;
                nl0Oll = 0;
                nl0OlO = 0;
                nl0OOi = 0;
                nl0OOl = 0;
                nl0OOO = 0;
                nli11l = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nl0lOl <= 0;
                        nl0O0i <= 0;
                        nl0O0l <= 0;
                        nl0O0O <= 0;
                        nl0O1l <= 0;
                        nl0O1O <= 0;
                        nl0Oii <= 0;
                        nl0Oil <= 0;
                        nl0OiO <= 0;
                        nl0Oli <= 0;
                        nl0Oll <= 0;
                        nl0OlO <= 0;
                        nl0OOi <= 0;
                        nl0OOl <= 0;
                        nl0OOO <= 0;
                        nli11l <= 0;
                end
                else if  (nli1O1O == 1'b1)
                begin
                        nl0lOl <= nlO01i;
                        nl0O0i <= nlO00i;
                        nl0O0l <= nlO00l;
                        nl0O0O <= nlO00O;
                        nl0O1l <= nlO01l;
                        nl0O1O <= nlO01O;
                        nl0Oii <= nlO0ii;
                        nl0Oil <= nlO0il;
                        nl0OiO <= nlO0iO;
                        nl0Oli <= nlO0li;
                        nl0Oll <= nlO0ll;
                        nl0OlO <= nlO0lO;
                        nl0OOi <= nlO0Oi;
                        nl0OOl <= nlO0Ol;
                        nl0OOO <= nlO0OO;
                        nli11l <= nlOi1i;
                end
        end
        initial
        begin
                nli00i = 0;
                nli00l = 0;
                nli00O = 0;
                nli01O = 0;
                nli0ii = 0;
                nli0il = 0;
                nli0iO = 0;
                nli0li = 0;
                nli0ll = 0;
                nli0lO = 0;
                nli0Oi = 0;
                nli0Ol = 0;
                nli0OO = 0;
                nli1OO = 0;
                nlii1i = 0;
                nlii1O = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  negedge wire_nlii1l_CLRN)
        begin
                if (wire_nlii1l_CLRN == 1'b0)
                begin
                        nli00i <= 0;
                        nli00l <= 0;
                        nli00O <= 0;
                        nli01O <= 0;
                        nli0ii <= 0;
                        nli0il <= 0;
                        nli0iO <= 0;
                        nli0li <= 0;
                        nli0ll <= 0;
                        nli0lO <= 0;
                        nli0Oi <= 0;
                        nli0Ol <= 0;
                        nli0OO <= 0;
                        nli1OO <= 0;
                        nlii1i <= 0;
                        nlii1O <= 0;
                end
                else if  (nlOlOlO == 1'b1)
                begin
                        nli00i <= nlOO10l;
                        nli00l <= nlOO10O;
                        nli00O <= nlOO1ii;
                        nli01O <= nlOO10i;
                        nli0ii <= nlOO1il;
                        nli0il <= nlOO1iO;
                        nli0iO <= nlOO1li;
                        nli0li <= nlOO1ll;
                        nli0ll <= nlOO1lO;
                        nli0lO <= nlOO1Oi;
                        nli0Oi <= nlOO1Ol;
                        nli0Ol <= nlOO1OO;
                        nli0OO <= nlOO01i;
                        nli1OO <= nlOO11l;
                        nlii1i <= nlOO01l;
                        nlii1O <= nlOO01O;
                end
        end
        assign
                wire_nlii1l_CLRN = ((nli1O0O76 ^ nli1O0O75) & (~ nlili1O));
        initial
        begin
                nliii0O = 0;
                nliiiil = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nli0iil)
        begin
                if (nli0iil == 1'b1)
                begin
                        nliii0O <= 1;
                        nliiiil <= 1;
                end
                else
                begin
                        nliii0O <= nliiiil;
                        nliiiil <= nlii0iO;
                end
        end
        event nliii0O_event;
        event nliiiil_event;
        initial
                #1 ->nliii0O_event;
        initial
                #1 ->nliiiil_event;
        always @(nliii0O_event)
                nliii0O <= 1;
        always @(nliiiil_event)
                nliiiil <= 1;
        initial
        begin
                nliiiiO = 0;
                nliiill = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  posedge nli0i1l)
        begin
                if (nli0i1l == 1'b1)
                begin
                        nliiiiO <= 1;
                        nliiill <= 1;
                end
                else
                begin
                        nliiiiO <= nliiill;
                        nliiill <= nlii0iO;
                end
        end
        event nliiiiO_event;
        event nliiill_event;
        initial
                #1 ->nliiiiO_event;
        initial
                #1 ->nliiill_event;
        always @(nliiiiO_event)
                nliiiiO <= 1;
        always @(nliiill_event)
                nliiill <= 1;
        initial
        begin
                nli0i = 0;
                nlili = 0;
        end
        always @ (clk or wire_nliiO_PRN or wire_nliiO_CLRN)
        begin
                if (wire_nliiO_PRN == 1'b0)
                begin
                        nli0i <= 1;
                        nlili <= 1;
                end
                else if  (wire_nliiO_CLRN == 1'b0)
                begin
                        nli0i <= 0;
                        nlili <= 0;
                end
                else
                if (clk != nliiO_clk_prev && clk == 1'b1)
                begin
                        nli0i <= nlii0iO;
                        nlili <= nli0i;
                end
                nliiO_clk_prev <= clk;
        end
        assign
                wire_nliiO_CLRN = (nlii0Ol6 ^ nlii0Ol5),
                wire_nliiO_PRN = ((nlii0Oi8 ^ nlii0Oi7) & (~ gxb_pwrdn_in));
        event nli0i_event;
        event nlili_event;
        initial
                #1 ->nli0i_event;
        initial
                #1 ->nlili_event;
        always @(nli0i_event)
                nli0i <= 1;
        always @(nlili_event)
                nlili <= 1;
        initial
        begin
                nlii0i = 0;
                nliilO = 0;
                nliiOl = 0;
        end
        always @ ( posedge clk or  posedge reset)
        begin
                if (reset == 1'b1)
                begin
                        nlii0i <= 1;
                        nliilO <= 1;
                        nliiOl <= 1;
                end
                else if  (nli1OiO == 1'b1)
                begin
                        nlii0i <= nlO00O;
                        nliilO <= nlO0il;
                        nliiOl <= nlO0iO;
                end
        end
        event nlii0i_event;
        event nliilO_event;
        event nliiOl_event;
        initial
                #1 ->nlii0i_event;
        initial
                #1 ->nliilO_event;
        initial
                #1 ->nliiOl_event;
        always @(nlii0i_event)
                nlii0i <= 1;
        always @(nliilO_event)
                nliilO <= 1;
        always @(nliiOl_event)
                nliiOl <= 1;
        initial
        begin
                nliill = 0;
                nliiOO = 0;
                nlil1l = 0;
        end
        always @ (clk or wire_nlil1i_PRN or wire_nlil1i_CLRN)
        begin
                if (wire_nlil1i_PRN == 1'b0)
                begin
                        nliill <= 1;
                        nliiOO <= 1;
                        nlil1l <= 1;
                end
                else if  (wire_nlil1i_CLRN == 1'b0)
                begin
                        nliill <= 0;
                        nliiOO <= 0;
                        nlil1l <= 0;
                end
                else if  (nli1OiO == 1'b1)
                if (clk != nlil1i_clk_prev && clk == 1'b1)
                begin
                        nliill <= nlO0ii;
                        nliiOO <= nlO0Oi;
                        nlil1l <= nlO0Ol;
                end
                nlil1i_clk_prev <= clk;
        end
        assign
                wire_nlil1i_CLRN = ((nli1Oil72 ^ nli1Oil71) & (~ reset)),
                wire_nlil1i_PRN = (nli1Oii74 ^ nli1Oii73);
        initial
        begin
                nlili0l = 0;
                nlili1O = 0;
        end
        always @ ( posedge wire_nl0ii_clkout or  posedge nlii0ll)
        begin
                if (nlii0ll == 1'b1)
                begin
                        nlili0l <= 1;
                        nlili1O <= 1;
                end
                else
                begin
                        nlili0l <= nlii0iO;
                        nlili1O <= nlili0l;
                end
        end
        event nlili0l_event;
        event nlili1O_event;
        initial
                #1 ->nlili0l_event;
        initial
                #1 ->nlili1O_event;
        always @(nlili0l_event)
                nlili0l <= 1;
        always @(nlili1O_event)
                nlili1O <= 1;
        initial
        begin
                n010li = 0;
                n010ll = 0;
                n0110i = 0;
                n0110l = 0;
                n0110O = 0;
                n0111i = 0;
                n0111l = 0;
                n0111O = 0;
                n011ii = 0;
                n01i0i = 0;
                n01i0l = 0;
                n01i1i = 0;
                n01i1O = 0;
                n1i01i = 0;
                n1i01l = 0;
                n1i01O = 0;
                n1i0il = 0;
                n1i0li = 0;
                n1OOiO = 0;
                n1OOli = 0;
                n1OOll = 0;
                n1OOlO = 0;
                n1OOOi = 0;
                n1OOOl = 0;
                n1OOOO = 0;
                nili1l = 0;
                nili1O = 0;
                niliil = 0;
                nilill = 0;
                nililO = 0;
                niliOi = 0;
                niliOl = 0;
                niliOO = 0;
                nill0i = 0;
                nill1i = 0;
                nill1l = 0;
                nill1O = 0;
                niO00l = 0;
                niO01i = 0;
                niO01O = 0;
                niO0OO = 0;
                niO1ii = 0;
                niO1il = 0;
                niO1lO = 0;
                niO1Ol = 0;
                niOi0i = 0;
                niOi1l = 0;
                niOi1O = 0;
                niOiiO = 0;
                niOill = 0;
                niOiOi = 0;
                niOiOl = 0;
                niOiOO = 0;
                niOl1i = 0;
                niOl1l = 0;
                nliil1i = 0;
                nliilii = 0;
                nliilil = 0;
                nliiliO = 0;
                nliilli = 0;
                nliilll = 0;
                nliillO = 0;
                nliilOi = 0;
                nliilOl = 0;
                nliilOO = 0;
                nliiOOi = 0;
                nll0iO = 0;
                nll0li = 0;
                nll0ll = 0;
                nll0Oi = 0;
        end
        always @ ( posedge wire_nl00l_clkout or  negedge wire_nll0lO_CLRN)
        begin
                if (wire_nll0lO_CLRN == 1'b0)
                begin
                        n010li <= 0;
                        n010ll <= 0;
                        n0110i <= 0;
                        n0110l <= 0;
                        n0110O <= 0;
                        n0111i <= 0;
                        n0111l <= 0;
                        n0111O <= 0;
                        n011ii <= 0;
                        n01i0i <= 0;
                        n01i0l <= 0;
                        n01i1i <= 0;
                        n01i1O <= 0;
                        n1i01i <= 0;
                        n1i01l <= 0;
                        n1i01O <= 0;
                        n1i0il <= 0;
                        n1i0li <= 0;
                        n1OOiO <= 0;
                        n1OOli <= 0;
                        n1OOll <= 0;
                        n1OOlO <= 0;
                        n1OOOi <= 0;
                        n1OOOl <= 0;
                        n1OOOO <= 0;
                        nili1l <= 0;
                        nili1O <= 0;
                        niliil <= 0;
                        nilill <= 0;
                        nililO <= 0;
                        niliOi <= 0;
                        niliOl <= 0;
                        niliOO <= 0;
                        nill0i <= 0;
                        nill1i <= 0;
                        nill1l <= 0;
                        nill1O <= 0;
                        niO00l <= 0;
                        niO01i <= 0;
                        niO01O <= 0;
                        niO0OO <= 0;
                        niO1ii <= 0;
                        niO1il <= 0;
                        niO1lO <= 0;
                        niO1Ol <= 0;
                        niOi0i <= 0;
                        niOi1l <= 0;
                        niOi1O <= 0;
                        niOiiO <= 0;
                        niOill <= 0;
                        niOiOi <= 0;
                        niOiOl <= 0;
                        niOiOO <= 0;
                        niOl1i <= 0;
                        niOl1l <= 0;
                        nliil1i <= 0;
                        nliilii <= 0;
                        nliilil <= 0;
                        nliiliO <= 0;
                        nliilli <= 0;
                        nliilll <= 0;
                        nliillO <= 0;
                        nliilOi <= 0;
                        nliilOl <= 0;
                        nliilOO <= 0;
                        nliiOOi <= 0;
                        nll0iO <= 0;
                        nll0li <= 0;
                        nll0ll <= 0;
                        nll0Oi <= 0;
                end
                else
                begin
                        n010li <= wire_n01i1l_dataout;
                        n010ll <= n010li;
                        n0110i <= wire_n0100l_dataout;
                        n0110l <= wire_n0100O_dataout;
                        n0110O <= wire_n010ii_dataout;
                        n0111i <= wire_n0101l_dataout;
                        n0111l <= wire_n0101O_dataout;
                        n0111O <= wire_n0100i_dataout;
                        n011ii <= wire_n010il_dataout;
                        n01i0i <= n01i0l;
                        n01i0l <= nlOiilO;
                        n01i1i <= n01i1O;
                        n01i1O <= nlilOl;
                        n1i01i <= wire_n1i1iO_dataout;
                        n1i01l <= wire_n1i0lO_dataout;
                        n1i01O <= wire_n1i0Oi_dataout;
                        n1i0il <= wire_n1ii1O_dataout;
                        n1i0li <= wire_n011iO_dataout;
                        n1OOiO <= wire_n011li_dataout;
                        n1OOli <= wire_n011ll_dataout;
                        n1OOll <= wire_n011lO_dataout;
                        n1OOlO <= wire_n011Oi_dataout;
                        n1OOOi <= wire_n011Ol_dataout;
                        n1OOOl <= wire_n011OO_dataout;
                        n1OOOO <= wire_n0101i_dataout;
                        nili1l <= (~ ((~ (niO01O ^ niO01i)) & (~ (niO00i ^ niO01l))));
                        nili1O <= (~ ((~ (niO1lO ^ niO1il)) & (~ (niO1Oi ^ niO1ll))));
                        niliil <= wire_nill0O_dataout;
                        nilill <= wire_nillii_dataout;
                        nililO <= wire_nillil_dataout;
                        niliOi <= wire_nilliO_dataout;
                        niliOl <= wire_nillli_dataout;
                        niliOO <= wire_nillll_dataout;
                        nill0i <= wire_nillOO_dataout;
                        nill1i <= wire_nilllO_dataout;
                        nill1l <= wire_nillOi_dataout;
                        nill1O <= wire_nillOl_dataout;
                        niO00l <= nl011O;
                        niO01i <= niO01O;
                        niO01O <= niO00l;
                        niO0OO <= niOi1l;
                        niO1ii <= wire_niO1iO_dataout;
                        niO1il <= niO1lO;
                        niO1lO <= niO1Ol;
                        niO1Ol <= nl011O;
                        niOi0i <= n0liOi;
                        niOi1l <= nlilOl;
                        niOi1O <= niOi0i;
                        niOiiO <= wire_niOilO_dataout;
                        niOill <= niOiOi;
                        niOiOi <= nl011l;
                        niOiOl <= niOiOO;
                        niOiOO <= nlilOl;
                        niOl1i <= niOl1l;
                        niOl1l <= nlOl11i;
                        nliil1i <= wire_nliiO1i_dataout;
                        nliilii <= wire_nliiO1l_dataout;
                        nliilil <= wire_nliiO1O_dataout;
                        nliiliO <= wire_nliiO0i_dataout;
                        nliilli <= wire_nliiO0l_dataout;
                        nliilll <= wire_nliiO0O_dataout;
                        nliillO <= wire_nliiOil_dataout;
                        nliilOi <= wire_nliiOiO_dataout;
                        nliilOl <= wire_nliiOli_dataout;
                        nliilOO <= nliiOOi;
                        nliiOOi <= nl011O;
                        nll0iO <= nll0li;
                        nll0li <= nll0ll;
                        nll0ll <= (nlli1l & nll0Oi);
                        nll0Oi <= nlli1l;
                end
        end
        assign
                wire_nll0lO_CLRN = ((nli011l64 ^ nli011l63) & (~ nlii0li));
        initial
        begin
                nll10l = 0;
        end
        always @ (clk or wire_nll10i_PRN or wire_nll10i_CLRN)
        begin
                if (wire_nll10i_PRN == 1'b0)
                begin
                        nll10l <= 1;
                end
                else if  (wire_nll10i_CLRN == 1'b0)
                begin
                        nll10l <= 0;
                end
                else if  (nli1OOO == 1'b1)
                if (clk != nll10i_clk_prev && clk == 1'b1)
                begin
                        nll10l <= nlO0Oi;
                end
                nll10i_clk_prev <= clk;
        end
        assign
                wire_nll10i_CLRN = (nli1OOi68 ^ nli1OOi67),
                wire_nll10i_PRN = ((nli1OlO70 ^ nli1OlO69) & (~ reset));
        event nll10l_event;
        initial
                #1 ->nll10l_event;
        always @(nll10l_event)
                nll10l <= 1;
        initial
        begin
                nliOiO = 0;
                nll11l = 0;
                nll11O = 0;
                nll1ii = 0;
        end
        always @ (clk or wire_nll10O_PRN or reset)
        begin
                if (wire_nll10O_PRN == 1'b0)
                begin
                        nliOiO <= 1;
                        nll11l <= 1;
                        nll11O <= 1;
                        nll1ii <= 1;
                end
                else if  (reset == 1'b1)
                begin
                        nliOiO <= 0;
                        nll11l <= 0;
                        nll11O <= 0;
                        nll1ii <= 0;
                end
                else if  (nli1OOO == 1'b1)
                if (clk != nll10O_clk_prev && clk == 1'b1)
                begin
                        nliOiO <= nlO00O;
                        nll11l <= nlO0ll;
                        nll11O <= nlO0lO;
                        nll1ii <= nlO0OO;
                end
                nll10O_clk_prev <= clk;
        end
        assign
                wire_nll10O_PRN = (nli1OOl66 ^ nli1OOl65);
        initial
        begin
                n0O11l = 0;
                n0Oi0i = 0;
                n1010i = 0;
                n1010l = 0;
                n1010O = 0;
                n1011i = 0;
                n1011l = 0;
                n1011O = 0;
                n101ii = 0;
                n101il = 0;
                n101iO = 0;
                n101li = 0;
                n10l0i = 0;
                n10l0l = 0;
                n10l0O = 0;
                n10lii = 0;
                n10lil = 0;
                n10liO = 0;
                n10lli = 0;
                n10lll = 0;
                n10llO = 0;
                n10lOi = 0;
                n10lOl = 0;
                n10lOO = 0;
                n10OlO = 0;
                n10OOi = 0;
                n11OiO = 0;
                n11Oli = 0;
                n11Oll = 0;
                n11OlO = 0;
                n11OOi = 0;
                n11OOl = 0;
                n11OOO = 0;
                n1i11l = 0;
                nl011i = 0;
                nl1l0O = 0;
                nl1Oil = 0;
                nl1OiO = 0;
                nl1Oli = 0;
                nl1Oll = 0;
                nl1OlO = 0;
                nl1OOi = 0;
                nl1OOl = 0;
                nl1OOO = 0;
                nli1lO = 0;
                nli1Oi = 0;
                nli1Ol = 0;
                nliOlOi = 0;
                nliOO0l = 0;
                nliOOiO = 0;
                nliOOli = 0;
                nliOOll = 0;
                nliOOlO = 0;
                nliOOOi = 0;
                nliOOOl = 0;
                nliOOOO = 0;
                nll001i = 0;
                nll001l = 0;
                nll010l = 0;
                nll010O = 0;
                nll01il = 0;
                nll01lO = 0;
                nll01OO = 0;
                nll0i0l = 0;
                nll0i0O = 0;
                nll0i1l = 0;
                nll0ill = 0;
                nll0ilO = 0;
                nll0iOi = 0;
                nll0iOl = 0;
                nll0iOO = 0;
                nll0l0i = 0;
                nll0l0l = 0;
                nll0l0O = 0;
                nll0l1i = 0;
                nll0l1l = 0;
                nll0l1O = 0;
                nll0lii = 0;
                nll0lil = 0;
                nll0liO = 0;
                nll0lli = 0;
                nll0lll = 0;
                nll110i = 0;
                nll110l = 0;
                nll110O = 0;
                nll111i = 0;
                nll111l = 0;
                nll111O = 0;
                nll11ii = 0;
                nll11il = 0;
                nll11iO = 0;
                nll11li = 0;
                nll11ll = 0;
                nll11lO = 0;
                nll11Oi = 0;
                nll11Ol = 0;
                nll11OO = 0;
                nlli0l = 0;
                nlli1O = 0;
                nlliii = 0;
                nlliil = 0;
                nllil0l = 0;
                nllil0O = 0;
                nllil1i = 0;
                nllili = 0;
                nllilii = 0;
                nllilil = 0;
                nlliliO = 0;
                nllilli = 0;
                nllilll = 0;
                nllillO = 0;
                nllilOi = 0;
                nllilOl = 0;
                nllilOO = 0;
                nlliO0i = 0;
                nlliO0l = 0;
                nlliO0O = 0;
                nlliO1i = 0;
                nlliO1l = 0;
                nlliO1O = 0;
                nlliOii = 0;
                nlliOil = 0;
                nlliOiO = 0;
                nlliOli = 0;
                nllO1lO = 0;
                nllO1Oi = 0;
                nllO1Ol = 0;
                nllOi0i = 0;
                nllOi0l = 0;
                nllOi1l = 0;
                nllOi1O = 0;
                nllOO0i = 0;
                nllOO0l = 0;
                nllOO0O = 0;
                nllOO1i = 0;
                nllOO1l = 0;
                nllOO1O = 0;
                nllOOii = 0;
                nllOOil = 0;
                nllOOiO = 0;
                nllOOli = 0;
                nllOOll = 0;
                nllOOlO = 0;
                nllOOOi = 0;
                nllOOOl = 0;
                nllOOOO = 0;
                nlO101i = 0;
                nlO101l = 0;
                nlO110i = 0;
                nlO110l = 0;
                nlO110O = 0;
                nlO111i = 0;
                nlO111l = 0;
                nlO111O = 0;
                nlO11ii = 0;
                nlO11il = 0;
                nlO11iO = 0;
                nlO11li = 0;
                nlO11ll = 0;
                nlO11lO = 0;
                nlO11Oi = 0;
                nlO11Ol = 0;
                nlO11OO = 0;
                nlOi01i = 0;
                nlOi01O = 0;
                nlOi1ll = 0;
                nlOi1lO = 0;
                nlOi1Oi = 0;
                nlOi1Ol = 0;
                nlOi1OO = 0;
                nlOiilO = 0;
                nlOiiOi = 0;
                nlOil0l = 0;
                nlOil0O = 0;
                nlOilii = 0;
                nlOilil = 0;
                nlOiliO = 0;
                nlOilli = 0;
                nlOilll = 0;
                nlOillO = 0;
                nlOilOi = 0;
                nlOilOl = 0;
                nlOilOO = 0;
                nlOiO0i = 0;
                nlOiO0l = 0;
                nlOiO0O = 0;
                nlOiO1i = 0;
                nlOiO1l = 0;
                nlOiO1O = 0;
                nlOiOii = 0;
                nlOiOil = 0;
                nlOiOiO = 0;
                nlOiOli = 0;
                nlOiOll = 0;
                nlOiOlO = 0;
                nlOiOOi = 0;
                nlOiOOl = 0;
                nlOiOOO = 0;
                nlOl10i = 0;
                nlOl11i = 0;
                nlOl11l = 0;
                nlOl11O = 0;
                nlOlOlO = 0;
                nlOO00i = 0;
                nlOO01i = 0;
                nlOO01l = 0;
                nlOO01O = 0;
                nlOO10i = 0;
                nlOO10l = 0;
                nlOO10O = 0;
                nlOO11l = 0;
                nlOO1ii = 0;
                nlOO1il = 0;
                nlOO1iO = 0;
                nlOO1li = 0;
                nlOO1ll = 0;
                nlOO1lO = 0;
                nlOO1Oi = 0;
                nlOO1Ol = 0;
                nlOO1OO = 0;
                nlOOlOO = 0;
        end
        always @ (wire_nl0ii_clkout or wire_nlliiO_PRN or wire_nlliiO_CLRN)
        begin
                if (wire_nlliiO_PRN == 1'b0)
                begin
                        n0O11l <= 1;
                        n0Oi0i <= 1;
                        n1010i <= 1;
                        n1010l <= 1;
                        n1010O <= 1;
                        n1011i <= 1;
                        n1011l <= 1;
                        n1011O <= 1;
                        n101ii <= 1;
                        n101il <= 1;
                        n101iO <= 1;
                        n101li <= 1;
                        n10l0i <= 1;
                        n10l0l <= 1;
                        n10l0O <= 1;
                        n10lii <= 1;
                        n10lil <= 1;
                        n10liO <= 1;
                        n10lli <= 1;
                        n10lll <= 1;
                        n10llO <= 1;
                        n10lOi <= 1;
                        n10lOl <= 1;
                        n10lOO <= 1;
                        n10OlO <= 1;
                        n10OOi <= 1;
                        n11OiO <= 1;
                        n11Oli <= 1;
                        n11Oll <= 1;
                        n11OlO <= 1;
                        n11OOi <= 1;
                        n11OOl <= 1;
                        n11OOO <= 1;
                        n1i11l <= 1;
                        nl011i <= 1;
                        nl1l0O <= 1;
                        nl1Oil <= 1;
                        nl1OiO <= 1;
                        nl1Oli <= 1;
                        nl1Oll <= 1;
                        nl1OlO <= 1;
                        nl1OOi <= 1;
                        nl1OOl <= 1;
                        nl1OOO <= 1;
                        nli1lO <= 1;
                        nli1Oi <= 1;
                        nli1Ol <= 1;
                        nliOlOi <= 1;
                        nliOO0l <= 1;
                        nliOOiO <= 1;
                        nliOOli <= 1;
                        nliOOll <= 1;
                        nliOOlO <= 1;
                        nliOOOi <= 1;
                        nliOOOl <= 1;
                        nliOOOO <= 1;
                        nll001i <= 1;
                        nll001l <= 1;
                        nll010l <= 1;
                        nll010O <= 1;
                        nll01il <= 1;
                        nll01lO <= 1;
                        nll01OO <= 1;
                        nll0i0l <= 1;
                        nll0i0O <= 1;
                        nll0i1l <= 1;
                        nll0ill <= 1;
                        nll0ilO <= 1;
                        nll0iOi <= 1;
                        nll0iOl <= 1;
                        nll0iOO <= 1;
                        nll0l0i <= 1;
                        nll0l0l <= 1;
                        nll0l0O <= 1;
                        nll0l1i <= 1;
                        nll0l1l <= 1;
                        nll0l1O <= 1;
                        nll0lii <= 1;
                        nll0lil <= 1;
                        nll0liO <= 1;
                        nll0lli <= 1;
                        nll0lll <= 1;
                        nll110i <= 1;
                        nll110l <= 1;
                        nll110O <= 1;
                        nll111i <= 1;
                        nll111l <= 1;
                        nll111O <= 1;
                        nll11ii <= 1;
                        nll11il <= 1;
                        nll11iO <= 1;
                        nll11li <= 1;
                        nll11ll <= 1;
                        nll11lO <= 1;
                        nll11Oi <= 1;
                        nll11Ol <= 1;
                        nll11OO <= 1;
                        nlli0l <= 1;
                        nlli1O <= 1;
                        nlliii <= 1;
                        nlliil <= 1;
                        nllil0l <= 1;
                        nllil0O <= 1;
                        nllil1i <= 1;
                        nllili <= 1;
                        nllilii <= 1;
                        nllilil <= 1;
                        nlliliO <= 1;
                        nllilli <= 1;
                        nllilll <= 1;
                        nllillO <= 1;
                        nllilOi <= 1;
                        nllilOl <= 1;
                        nllilOO <= 1;
                        nlliO0i <= 1;
                        nlliO0l <= 1;
                        nlliO0O <= 1;
                        nlliO1i <= 1;
                        nlliO1l <= 1;
                        nlliO1O <= 1;
                        nlliOii <= 1;
                        nlliOil <= 1;
                        nlliOiO <= 1;
                        nlliOli <= 1;
                        nllO1lO <= 1;
                        nllO1Oi <= 1;
                        nllO1Ol <= 1;
                        nllOi0i <= 1;
                        nllOi0l <= 1;
                        nllOi1l <= 1;
                        nllOi1O <= 1;
                        nllOO0i <= 1;
                        nllOO0l <= 1;
                        nllOO0O <= 1;
                        nllOO1i <= 1;
                        nllOO1l <= 1;
                        nllOO1O <= 1;
                        nllOOii <= 1;
                        nllOOil <= 1;
                        nllOOiO <= 1;
                        nllOOli <= 1;
                        nllOOll <= 1;
                        nllOOlO <= 1;
                        nllOOOi <= 1;
                        nllOOOl <= 1;
                        nllOOOO <= 1;
                        nlO101i <= 1;
                        nlO101l <= 1;
                        nlO110i <= 1;
                        nlO110l <= 1;
                        nlO110O <= 1;
                        nlO111i <= 1;
                        nlO111l <= 1;
                        nlO111O <= 1;
                        nlO11ii <= 1;
                        nlO11il <= 1;
                        nlO11iO <= 1;
                        nlO11li <= 1;
                        nlO11ll <= 1;
                        nlO11lO <= 1;
                        nlO11Oi <= 1;
                        nlO11Ol <= 1;
                        nlO11OO <= 1;
                        nlOi01i <= 1;
                        nlOi01O <= 1;
                        nlOi1ll <= 1;
                        nlOi1lO <= 1;
                        nlOi1Oi <= 1;
                        nlOi1Ol <= 1;
                        nlOi1OO <= 1;
                        nlOiilO <= 1;
                        nlOiiOi <= 1;
                        nlOil0l <= 1;
                        nlOil0O <= 1;
                        nlOilii <= 1;
                        nlOilil <= 1;
                        nlOiliO <= 1;
                        nlOilli <= 1;
                        nlOilll <= 1;
                        nlOillO <= 1;
                        nlOilOi <= 1;
                        nlOilOl <= 1;
                        nlOilOO <= 1;
                        nlOiO0i <= 1;
                        nlOiO0l <= 1;
                        nlOiO0O <= 1;
                        nlOiO1i <= 1;
                        nlOiO1l <= 1;
                        nlOiO1O <= 1;
                        nlOiOii <= 1;
                        nlOiOil <= 1;
                        nlOiOiO <= 1;
                        nlOiOli <= 1;
                        nlOiOll <= 1;
                        nlOiOlO <= 1;
                        nlOiOOi <= 1;
                        nlOiOOl <= 1;
                        nlOiOOO <= 1;
                        nlOl10i <= 1;
                        nlOl11i <= 1;
                        nlOl11l <= 1;
                        nlOl11O <= 1;
                        nlOlOlO <= 1;
                        nlOO00i <= 1;
                        nlOO01i <= 1;
                        nlOO01l <= 1;
                        nlOO01O <= 1;
                        nlOO10i <= 1;
                        nlOO10l <= 1;
                        nlOO10O <= 1;
                        nlOO11l <= 1;
                        nlOO1ii <= 1;
                        nlOO1il <= 1;
                        nlOO1iO <= 1;
                        nlOO1li <= 1;
                        nlOO1ll <= 1;
                        nlOO1lO <= 1;
                        nlOO1Oi <= 1;
                        nlOO1Ol <= 1;
                        nlOO1OO <= 1;
                        nlOOlOO <= 1;
                end
                else if  (wire_nlliiO_CLRN == 1'b0)
                begin
                        n0O11l <= 0;
                        n0Oi0i <= 0;
                        n1010i <= 0;
                        n1010l <= 0;
                        n1010O <= 0;
                        n1011i <= 0;
                        n1011l <= 0;
                        n1011O <= 0;
                        n101ii <= 0;
                        n101il <= 0;
                        n101iO <= 0;
                        n101li <= 0;
                        n10l0i <= 0;
                        n10l0l <= 0;
                        n10l0O <= 0;
                        n10lii <= 0;
                        n10lil <= 0;
                        n10liO <= 0;
                        n10lli <= 0;
                        n10lll <= 0;
                        n10llO <= 0;
                        n10lOi <= 0;
                        n10lOl <= 0;
                        n10lOO <= 0;
                        n10OlO <= 0;
                        n10OOi <= 0;
                        n11OiO <= 0;
                        n11Oli <= 0;
                        n11Oll <= 0;
                        n11OlO <= 0;
                        n11OOi <= 0;
                        n11OOl <= 0;
                        n11OOO <= 0;
                        n1i11l <= 0;
                        nl011i <= 0;
                        nl1l0O <= 0;
                        nl1Oil <= 0;
                        nl1OiO <= 0;
                        nl1Oli <= 0;
                        nl1Oll <= 0;
                        nl1OlO <= 0;
                        nl1OOi <= 0;
                        nl1OOl <= 0;
                        nl1OOO <= 0;
                        nli1lO <= 0;
                        nli1Oi <= 0;
                        nli1Ol <= 0;
                        nliOlOi <= 0;
                        nliOO0l <= 0;
                        nliOOiO <= 0;
                        nliOOli <= 0;
                        nliOOll <= 0;
                        nliOOlO <= 0;
                        nliOOOi <= 0;
                        nliOOOl <= 0;
                        nliOOOO <= 0;
                        nll001i <= 0;
                        nll001l <= 0;
                        nll010l <= 0;
                        nll010O <= 0;
                        nll01il <= 0;
                        nll01lO <= 0;
                        nll01OO <= 0;
                        nll0i0l <= 0;
                        nll0i0O <= 0;
                        nll0i1l <= 0;
                        nll0ill <= 0;
                        nll0ilO <= 0;
                        nll0iOi <= 0;
                        nll0iOl <= 0;
                        nll0iOO <= 0;
                        nll0l0i <= 0;
                        nll0l0l <= 0;
                        nll0l0O <= 0;
                        nll0l1i <= 0;
                        nll0l1l <= 0;
                        nll0l1O <= 0;
                        nll0lii <= 0;
                        nll0lil <= 0;
                        nll0liO <= 0;
                        nll0lli <= 0;
                        nll0lll <= 0;
                        nll110i <= 0;
                        nll110l <= 0;
                        nll110O <= 0;
                        nll111i <= 0;
                        nll111l <= 0;
                        nll111O <= 0;
                        nll11ii <= 0;
                        nll11il <= 0;
                        nll11iO <= 0;
                        nll11li <= 0;
                        nll11ll <= 0;
                        nll11lO <= 0;
                        nll11Oi <= 0;
                        nll11Ol <= 0;
                        nll11OO <= 0;
                        nlli0l <= 0;
                        nlli1O <= 0;
                        nlliii <= 0;
                        nlliil <= 0;
                        nllil0l <= 0;
                        nllil0O <= 0;
                        nllil1i <= 0;
                        nllili <= 0;
                        nllilii <= 0;
                        nllilil <= 0;
                        nlliliO <= 0;
                        nllilli <= 0;
                        nllilll <= 0;
                        nllillO <= 0;
                        nllilOi <= 0;
                        nllilOl <= 0;
                        nllilOO <= 0;
                        nlliO0i <= 0;
                        nlliO0l <= 0;
                        nlliO0O <= 0;
                        nlliO1i <= 0;
                        nlliO1l <= 0;
                        nlliO1O <= 0;
                        nlliOii <= 0;
                        nlliOil <= 0;
                        nlliOiO <= 0;
                        nlliOli <= 0;
                        nllO1lO <= 0;
                        nllO1Oi <= 0;
                        nllO1Ol <= 0;
                        nllOi0i <= 0;
                        nllOi0l <= 0;
                        nllOi1l <= 0;
                        nllOi1O <= 0;
                        nllOO0i <= 0;
                        nllOO0l <= 0;
                        nllOO0O <= 0;
                        nllOO1i <= 0;
                        nllOO1l <= 0;
                        nllOO1O <= 0;
                        nllOOii <= 0;
                        nllOOil <= 0;
                        nllOOiO <= 0;
                        nllOOli <= 0;
                        nllOOll <= 0;
                        nllOOlO <= 0;
                        nllOOOi <= 0;
                        nllOOOl <= 0;
                        nllOOOO <= 0;
                        nlO101i <= 0;
                        nlO101l <= 0;
                        nlO110i <= 0;
                        nlO110l <= 0;
                        nlO110O <= 0;
                        nlO111i <= 0;
                        nlO111l <= 0;
                        nlO111O <= 0;
                        nlO11ii <= 0;
                        nlO11il <= 0;
                        nlO11iO <= 0;
                        nlO11li <= 0;
                        nlO11ll <= 0;
                        nlO11lO <= 0;
                        nlO11Oi <= 0;
                        nlO11Ol <= 0;
                        nlO11OO <= 0;
                        nlOi01i <= 0;
                        nlOi01O <= 0;
                        nlOi1ll <= 0;
                        nlOi1lO <= 0;
                        nlOi1Oi <= 0;
                        nlOi1Ol <= 0;
                        nlOi1OO <= 0;
                        nlOiilO <= 0;
                        nlOiiOi <= 0;
                        nlOil0l <= 0;
                        nlOil0O <= 0;
                        nlOilii <= 0;
                        nlOilil <= 0;
                        nlOiliO <= 0;
                        nlOilli <= 0;
                        nlOilll <= 0;
                        nlOillO <= 0;
                        nlOilOi <= 0;
                        nlOilOl <= 0;
                        nlOilOO <= 0;
                        nlOiO0i <= 0;
                        nlOiO0l <= 0;
                        nlOiO0O <= 0;
                        nlOiO1i <= 0;
                        nlOiO1l <= 0;
                        nlOiO1O <= 0;
                        nlOiOii <= 0;
                        nlOiOil <= 0;
                        nlOiOiO <= 0;
                        nlOiOli <= 0;
                        nlOiOll <= 0;
                        nlOiOlO <= 0;
                        nlOiOOi <= 0;
                        nlOiOOl <= 0;
                        nlOiOOO <= 0;
                        nlOl10i <= 0;
                        nlOl11i <= 0;
                        nlOl11l <= 0;
                        nlOl11O <= 0;
                        nlOlOlO <= 0;
                        nlOO00i <= 0;
                        nlOO01i <= 0;
                        nlOO01l <= 0;
                        nlOO01O <= 0;
                        nlOO10i <= 0;
                        nlOO10l <= 0;
                        nlOO10O <= 0;
                        nlOO11l <= 0;
                        nlOO1ii <= 0;
                        nlOO1il <= 0;
                        nlOO1iO <= 0;
                        nlOO1li <= 0;
                        nlOO1ll <= 0;
                        nlOO1lO <= 0;
                        nlOO1Oi <= 0;
                        nlOO1Ol <= 0;
                        nlOO1OO <= 0;
                        nlOOlOO <= 0;
                end
                else
                if (wire_nl0ii_clkout != nlliiO_clk_prev && wire_nl0ii_clkout == 1'b1)
                begin
                        n0O11l <= (~ ((~ (n0Oi0i ^ wire_n01ilO_dout[0])) & (~ (n0Oiil ^ wire_n01ilO_dout[1]))));
                        n0Oi0i <= wire_n01ilO_dout[0];
                        n1010i <= wire_n100il_dataout;
                        n1010l <= wire_n100iO_dataout;
                        n1010O <= wire_n100li_dataout;
                        n1011i <= wire_n1000l_dataout;
                        n1011l <= wire_n1000O_dataout;
                        n1011O <= wire_n100ii_dataout;
                        n101ii <= wire_n100ll_dataout;
                        n101il <= wire_n100lO_dataout;
                        n101iO <= wire_n100Oi_dataout;
                        n101li <= wire_n100Ol_dataout;
                        n10l0i <= wire_n10O1i_dataout;
                        n10l0l <= wire_n10O1l_dataout;
                        n10l0O <= wire_n10O1O_dataout;
                        n10lii <= wire_n10O0i_dataout;
                        n10lil <= wire_n10O0l_dataout;
                        n10liO <= wire_n10O0O_dataout;
                        n10lli <= wire_n10Oii_dataout;
                        n10lll <= wire_n10Oil_dataout;
                        n10llO <= wire_n10OiO_dataout;
                        n10lOi <= wire_n10Oli_dataout;
                        n10lOl <= wire_n10Oll_dataout;
                        n10lOO <= niO1i;
                        n10OlO <= wire_n10OOl_dataout;
                        n10OOi <= n1i11l;
                        n11OiO <= wire_n101Oi_dataout;
                        n11Oli <= wire_n101Ol_dataout;
                        n11Oll <= wire_n101OO_dataout;
                        n11OlO <= wire_n1001i_dataout;
                        n11OOi <= wire_n1001l_dataout;
                        n11OOl <= wire_n1001O_dataout;
                        n11OOO <= wire_n1000i_dataout;
                        n1i11l <= nlilOl;
                        nl011i <= nlO1Ol;
                        nl1l0O <= nl1OlO;
                        nl1Oil <= nl1OOi;
                        nl1OiO <= nl1OOl;
                        nl1Oli <= nl1OOO;
                        nl1Oll <= nl011i;
                        nl1OlO <= nlO1li;
                        nl1OOi <= nlO1ll;
                        nl1OOl <= nlO1lO;
                        nl1OOO <= nlO1Oi;
                        nli1lO <= nli1Oi;
                        nli1Oi <= nli10O;
                        nli1Ol <= wire_nli01i_dataout;
                        nliOlOi <= wire_nliOO0O_dataout;
                        nliOO0l <= wire_nll101i_dataout;
                        nliOOiO <= wire_nll01ii_dataout;
                        nliOOli <= wire_nll101l_dataout;
                        nliOOll <= wire_nll101O_dataout;
                        nliOOlO <= wire_nll100i_dataout;
                        nliOOOi <= wire_nll100l_dataout;
                        nliOOOl <= wire_nll100O_dataout;
                        nliOOOO <= wire_nll10ii_dataout;
                        nll001i <= wire_nll000l_dataout;
                        nll001l <= wire_nll0i1O_dataout;
                        nll010l <= wire_nliOlOl_dataout;
                        nll010O <= wire_nll01iO_dataout;
                        nll01il <= wire_nll01Oi_dataout;
                        nll01lO <= wire_nll001O_dataout;
                        nll01OO <= wire_nll000i_dataout;
                        nll0i0l <= wire_nll0iil_dataout;
                        nll0i0O <= wire_nll0llO_dataout;
                        nll0i1l <= wire_nll0iii_dataout;
                        nll0ill <= wire_nll0lOi_dataout;
                        nll0ilO <= wire_nll0lOl_dataout;
                        nll0iOi <= wire_nll0lOO_dataout;
                        nll0iOl <= wire_nll0O1i_dataout;
                        nll0iOO <= wire_nll0O1l_dataout;
                        nll0l0i <= wire_nll0O0O_dataout;
                        nll0l0l <= wire_nll0Oii_dataout;
                        nll0l0O <= wire_nll0Oil_dataout;
                        nll0l1i <= wire_nll0O1O_dataout;
                        nll0l1l <= wire_nll0O0i_dataout;
                        nll0l1O <= wire_nll0O0l_dataout;
                        nll0lii <= wire_nll0OiO_dataout;
                        nll0lil <= wire_nll0Oli_dataout;
                        nll0liO <= wire_nll0Oll_dataout;
                        nll0lli <= wire_nll0OlO_dataout;
                        nll0lll <= wire_nllil1l_dataout;
                        nll110i <= wire_nll10ll_dataout;
                        nll110l <= wire_nll10lO_dataout;
                        nll110O <= wire_nll10Oi_dataout;
                        nll111i <= wire_nll10il_dataout;
                        nll111l <= wire_nll10iO_dataout;
                        nll111O <= wire_nll10li_dataout;
                        nll11ii <= wire_nll10Ol_dataout;
                        nll11il <= wire_nll10OO_dataout;
                        nll11iO <= wire_nll1i1i_dataout;
                        nll11li <= wire_nll1i1l_dataout;
                        nll11ll <= wire_nll1i1O_dataout;
                        nll11lO <= wire_nll1i0i_dataout;
                        nll11Oi <= wire_nll1i0l_dataout;
                        nll11Ol <= wire_nll1i0O_dataout;
                        nll11OO <= wire_nliOO0i_dataout;
                        nlli0l <= nlliii;
                        nlli1O <= (nlliil & (~ nlliii));
                        nlliii <= nlliil;
                        nlliil <= (nlliOl & nllili);
                        nllil0l <= wire_nlliOlO_dataout;
                        nllil0O <= wire_nlliOOi_dataout;
                        nllil1i <= wire_nlliOll_dataout;
                        nllili <= nlliOl;
                        nllilii <= wire_nlliOOl_dataout;
                        nllilil <= wire_nlliOOO_dataout;
                        nlliliO <= wire_nlll11i_dataout;
                        nllilli <= wire_nlll11l_dataout;
                        nllilll <= wire_nlll11O_dataout;
                        nllillO <= wire_nlll10i_dataout;
                        nllilOi <= wire_nlll10l_dataout;
                        nllilOl <= wire_nlll10O_dataout;
                        nllilOO <= wire_nlll1ii_dataout;
                        nlliO0i <= wire_nlll1ll_dataout;
                        nlliO0l <= wire_nlll1lO_dataout;
                        nlliO0O <= wire_nlll1Oi_dataout;
                        nlliO1i <= wire_nlll1il_dataout;
                        nlliO1l <= wire_nlll1iO_dataout;
                        nlliO1O <= wire_nlll1li_dataout;
                        nlliOii <= wire_nlll1Ol_dataout;
                        nlliOil <= wire_nlll1OO_dataout;
                        nlliOiO <= wire_nlll01i_dataout;
                        nlliOli <= wire_nllO1OO_dataout;
                        nllO1lO <= wire_nllO01i_dataout;
                        nllO1Oi <= wire_nllO01l_dataout;
                        nllO1Ol <= wire_nllOi0O_dataout;
                        nllOi0i <= wire_nllOiiO_dataout;
                        nllOi0l <= wire_nlO101O_dataout;
                        nllOi1l <= wire_nllOiii_dataout;
                        nllOi1O <= wire_nllOiil_dataout;
                        nllOO0i <= wire_nlO10ii_dataout;
                        nllOO0l <= wire_nlO10il_dataout;
                        nllOO0O <= wire_nlO10iO_dataout;
                        nllOO1i <= wire_nlO100i_dataout;
                        nllOO1l <= wire_nlO100l_dataout;
                        nllOO1O <= wire_nlO100O_dataout;
                        nllOOii <= wire_nlO10li_dataout;
                        nllOOil <= wire_nlO10ll_dataout;
                        nllOOiO <= wire_nlO10lO_dataout;
                        nllOOli <= wire_nlO10Oi_dataout;
                        nllOOll <= wire_nlO10Ol_dataout;
                        nllOOlO <= wire_nlO10OO_dataout;
                        nllOOOi <= wire_nlO1i1i_dataout;
                        nllOOOl <= wire_nlO1i1l_dataout;
                        nllOOOO <= wire_nlO1i1O_dataout;
                        nlO101i <= wire_nlO1l0i_dataout;
                        nlO101l <= wire_nlOi00i_dataout;
                        nlO110i <= wire_nlO1iii_dataout;
                        nlO110l <= wire_nlO1iil_dataout;
                        nlO110O <= wire_nlO1iiO_dataout;
                        nlO111i <= wire_nlO1i0i_dataout;
                        nlO111l <= wire_nlO1i0l_dataout;
                        nlO111O <= wire_nlO1i0O_dataout;
                        nlO11ii <= wire_nlO1ili_dataout;
                        nlO11il <= wire_nlO1ill_dataout;
                        nlO11iO <= wire_nlO1ilO_dataout;
                        nlO11li <= wire_nlO1iOi_dataout;
                        nlO11ll <= wire_nlO1iOl_dataout;
                        nlO11lO <= wire_nlO1iOO_dataout;
                        nlO11Oi <= wire_nlO1l1i_dataout;
                        nlO11Ol <= wire_nlO1l1l_dataout;
                        nlO11OO <= wire_nlO1l1O_dataout;
                        nlOi01i <= wire_nlOi0li_dataout;
                        nlOi01O <= wire_nlili0O_dout;
                        nlOi1ll <= wire_nlOi00l_dataout;
                        nlOi1lO <= wire_nlOi00O_dataout;
                        nlOi1Oi <= wire_nlOi0ii_dataout;
                        nlOi1Ol <= wire_nlOi0il_dataout;
                        nlOi1OO <= wire_nlOi0iO_dataout;
                        nlOiilO <= wire_nlOiiOl_dataout;
                        nlOiiOi <= wire_nlOl10l_dataout;
                        nlOil0l <= wire_nlOl10O_dataout;
                        nlOil0O <= wire_nlOl1ii_dataout;
                        nlOilii <= wire_nlOl1il_dataout;
                        nlOilil <= wire_nlOl1iO_dataout;
                        nlOiliO <= wire_nlOl1li_dataout;
                        nlOilli <= wire_nlOl1ll_dataout;
                        nlOilll <= wire_nlOl1lO_dataout;
                        nlOillO <= wire_nlOl1Oi_dataout;
                        nlOilOi <= wire_nlOl1Ol_dataout;
                        nlOilOl <= wire_nlOl1OO_dataout;
                        nlOilOO <= wire_nlOl01i_dataout;
                        nlOiO0i <= wire_nlOl00l_dataout;
                        nlOiO0l <= wire_nlOl00O_dataout;
                        nlOiO0O <= wire_nlOl0ii_dataout;
                        nlOiO1i <= wire_nlOl01l_dataout;
                        nlOiO1l <= wire_nlOl01O_dataout;
                        nlOiO1O <= wire_nlOl00i_dataout;
                        nlOiOii <= wire_nlOl0il_dataout;
                        nlOiOil <= wire_nlOl0iO_dataout;
                        nlOiOiO <= wire_nlOl0li_dataout;
                        nlOiOli <= wire_nlOl0ll_dataout;
                        nlOiOll <= wire_nlOl0lO_dataout;
                        nlOiOlO <= wire_nlOl0Oi_dataout;
                        nlOiOOi <= wire_nlOl0Ol_dataout;
                        nlOiOOl <= wire_nlOl0OO_dataout;
                        nlOiOOO <= wire_nlOli1i_dataout;
                        nlOl10i <= wire_nlOlOOi_dataout;
                        nlOl11i <= wire_nlOli1l_dataout;
                        nlOl11l <= wire_nlOli1O_dataout;
                        nlOl11O <= wire_nlOli0i_dataout;
                        nlOlOlO <= wire_nlOO11O_dataout;
                        nlOO00i <= wire_nlOOO1i_dataout;
                        nlOO01i <= wire_nlOOi1O_dataout;
                        nlOO01l <= wire_nlOOi0i_dataout;
                        nlOO01O <= wire_nlOOi0l_dataout;
                        nlOO10i <= wire_nlOO00O_dataout;
                        nlOO10l <= wire_nlOO0ii_dataout;
                        nlOO10O <= wire_nlOO0il_dataout;
                        nlOO11l <= wire_nlOO00l_dataout;
                        nlOO1ii <= wire_nlOO0iO_dataout;
                        nlOO1il <= wire_nlOO0li_dataout;
                        nlOO1iO <= wire_nlOO0ll_dataout;
                        nlOO1li <= wire_nlOO0lO_dataout;
                        nlOO1ll <= wire_nlOO0Oi_dataout;
                        nlOO1lO <= wire_nlOO0Ol_dataout;
                        nlOO1Oi <= wire_nlOO0OO_dataout;
                        nlOO1Ol <= wire_nlOOi1i_dataout;
                        nlOO1OO <= wire_nlOOi1l_dataout;
                        nlOOlOO <= wire_n101lO_dataout;
                end
                nlliiO_clk_prev <= wire_nl0ii_clkout;
        end
        assign
                wire_nlliiO_CLRN = ((nli010i60 ^ nli010i59) & (~ nlili1O)),
                wire_nlliiO_PRN = (nli011O62 ^ nli011O61);
        initial
        begin
                niOO0i = 0;
                niOO0l = 0;
                niOO0O = 0;
                niOO1i = 0;
                niOO1l = 0;
                niOO1O = 0;
                niOOii = 0;
                niOOil = 0;
                niOOiO = 0;
                niOOli = 0;
                niOOll = 0;
                niOOlO = 0;
                niOOOi = 0;
                niOOOl = 0;
                niOOOO = 0;
                nl010l = 0;
                nl011l = 0;
                nl011O = 0;
                nl1i0i = 0;
                nli10l = 0;
                nli10O = 0;
                nli11O = 0;
                nli1ll = 0;
                nlil0i = 0;
                nlil0O = 0;
                nlil1O = 0;
                nlilii = 0;
                nlilOl = 0;
                nliO0l = 0;
                nliO0O = 0;
                nliOii = 0;
                nliOil = 0;
                nll00i = 0;
                nll00l = 0;
                nll01i = 0;
                nll01l = 0;
                nll01O = 0;
                nll0Ol = 0;
                nll11i = 0;
                nll1il = 0;
                nll1iO = 0;
                nll1OO = 0;
                nlli1i = 0;
                nlli1l = 0;
                nllill = 0;
                nlliOi = 0;
                nlliOl = 0;
                nlliOO = 0;
                nlll0i = 0;
                nlll0l = 0;
                nlll0O = 0;
                nlllii = 0;
                nlllil = 0;
                nllliO = 0;
                nlllli = 0;
                nlllll = 0;
                nllOil = 0;
                nllOiO = 0;
                nllOli = 0;
                nllOll = 0;
                nllOlO = 0;
                nllOOi = 0;
                nllOOl = 0;
                nllOOO = 0;
                nlO00i = 0;
                nlO00l = 0;
                nlO00O = 0;
                nlO01i = 0;
                nlO01l = 0;
                nlO01O = 0;
                nlO0ii = 0;
                nlO0il = 0;
                nlO0iO = 0;
                nlO0li = 0;
                nlO0ll = 0;
                nlO0lO = 0;
                nlO0Oi = 0;
                nlO0Ol = 0;
                nlO0OO = 0;
                nlO10i = 0;
                nlO10l = 0;
                nlO10O = 0;
                nlO11i = 0;
                nlO11l = 0;
                nlO11O = 0;
                nlO1ii = 0;
                nlO1il = 0;
                nlO1iO = 0;
                nlO1li = 0;
                nlO1ll = 0;
                nlO1lO = 0;
                nlO1Oi = 0;
                nlO1Ol = 0;
                nlO1OO = 0;
                nlOi1i = 0;
                nlOi1l = 0;
                nlOOii = 0;
                nlOOil = 0;
                nlOOiO = 0;
                nlOOli = 0;
                nlOOOi = 0;
        end
        always @ ( posedge clk or  negedge wire_nlOOlO_CLRN)
        begin
                if (wire_nlOOlO_CLRN == 1'b0)
                begin
                        niOO0i <= 0;
                        niOO0l <= 0;
                        niOO0O <= 0;
                        niOO1i <= 0;
                        niOO1l <= 0;
                        niOO1O <= 0;
                        niOOii <= 0;
                        niOOil <= 0;
                        niOOiO <= 0;
                        niOOli <= 0;
                        niOOll <= 0;
                        niOOlO <= 0;
                        niOOOi <= 0;
                        niOOOl <= 0;
                        niOOOO <= 0;
                        nl010l <= 0;
                        nl011l <= 0;
                        nl011O <= 0;
                        nl1i0i <= 0;
                        nli10l <= 0;
                        nli10O <= 0;
                        nli11O <= 0;
                        nli1ll <= 0;
                        nlil0i <= 0;
                        nlil0O <= 0;
                        nlil1O <= 0;
                        nlilii <= 0;
                        nlilOl <= 0;
                        nliO0l <= 0;
                        nliO0O <= 0;
                        nliOii <= 0;
                        nliOil <= 0;
                        nll00i <= 0;
                        nll00l <= 0;
                        nll01i <= 0;
                        nll01l <= 0;
                        nll01O <= 0;
                        nll0Ol <= 0;
                        nll11i <= 0;
                        nll1il <= 0;
                        nll1iO <= 0;
                        nll1OO <= 0;
                        nlli1i <= 0;
                        nlli1l <= 0;
                        nllill <= 0;
                        nlliOi <= 0;
                        nlliOl <= 0;
                        nlliOO <= 0;
                        nlll0i <= 0;
                        nlll0l <= 0;
                        nlll0O <= 0;
                        nlllii <= 0;
                        nlllil <= 0;
                        nllliO <= 0;
                        nlllli <= 0;
                        nlllll <= 0;
                        nllOil <= 0;
                        nllOiO <= 0;
                        nllOli <= 0;
                        nllOll <= 0;
                        nllOlO <= 0;
                        nllOOi <= 0;
                        nllOOl <= 0;
                        nllOOO <= 0;
                        nlO00i <= 0;
                        nlO00l <= 0;
                        nlO00O <= 0;
                        nlO01i <= 0;
                        nlO01l <= 0;
                        nlO01O <= 0;
                        nlO0ii <= 0;
                        nlO0il <= 0;
                        nlO0iO <= 0;
                        nlO0li <= 0;
                        nlO0ll <= 0;
                        nlO0lO <= 0;
                        nlO0Oi <= 0;
                        nlO0Ol <= 0;
                        nlO0OO <= 0;
                        nlO10i <= 0;
                        nlO10l <= 0;
                        nlO10O <= 0;
                        nlO11i <= 0;
                        nlO11l <= 0;
                        nlO11O <= 0;
                        nlO1ii <= 0;
                        nlO1il <= 0;
                        nlO1iO <= 0;
                        nlO1li <= 0;
                        nlO1ll <= 0;
                        nlO1lO <= 0;
                        nlO1Oi <= 0;
                        nlO1Ol <= 0;
                        nlO1OO <= 0;
                        nlOi1i <= 0;
                        nlOi1l <= 0;
                        nlOOii <= 0;
                        nlOOil <= 0;
                        nlOOiO <= 0;
                        nlOOli <= 0;
                        nlOOOi <= 0;
                end
                else
                begin
                        niOO0i <= wire_nl110O_dataout;
                        niOO0l <= wire_nl11ii_dataout;
                        niOO0O <= wire_nl11il_dataout;
                        niOO1i <= wire_nl111O_dataout;
                        niOO1l <= wire_nl110i_dataout;
                        niOO1O <= wire_nl110l_dataout;
                        niOOii <= wire_nl11iO_dataout;
                        niOOil <= wire_nl11li_dataout;
                        niOOiO <= wire_nl11ll_dataout;
                        niOOli <= wire_nl11lO_dataout;
                        niOOll <= wire_nl11Oi_dataout;
                        niOOlO <= wire_nl11Ol_dataout;
                        niOOOi <= wire_nl11OO_dataout;
                        niOOOl <= wire_nl101i_dataout;
                        niOOOO <= wire_nl101l_dataout;
                        nl010l <= wire_nl00il_dataout;
                        nl011l <= wire_nl010O_dataout;
                        nl011O <= wire_nl01ii_dataout;
                        nl1i0i <= wire_nl111l_dataout;
                        nli10l <= wire_nli1ii_dataout;
                        nli10O <= nli1ll;
                        nli11O <= nli10O;
                        nli1ll <= nli1Ol;
                        nlil0i <= wire_nlilli_dataout;
                        nlil0O <= ((~ nll1il) & (nll00i & nll10l));
                        nlil1O <= nll01l;
                        nlilii <= wire_nlilOO_dataout;
                        nlilOl <= (nll1il | nll11l);
                        nliO0l <= nll10l;
                        nliO0O <= nll11O;
                        nliOii <= nll11i;
                        nliOil <= wire_nliOll_dataout;
                        nll00i <= nll00l;
                        nll00l <= nliOOiO;
                        nll01i <= niO1i;
                        nll01l <= nll01O;
                        nll01O <= nll010O;
                        nll0Ol <= nll0iO;
                        nll11i <= wire_nll1li_dataout;
                        nll1il <= wire_nll1lO_dataout;
                        nll1iO <= nlO1iO;
                        nll1OO <= nll01i;
                        nlli1i <= wire_nlli0i_dataout;
                        nlli1l <= wire_nlOi0i_o;
                        nllill <= nlli0l;
                        nlliOi <= wire_nlll1i_dataout;
                        nlliOl <= wire_nlOi0O_o;
                        nlliOO <= nli010l;
                        nlll0i <= wire_nlllOi_dataout;
                        nlll0l <= wire_nlllOl_dataout;
                        nlll0O <= wire_nlllOO_dataout;
                        nlllii <= wire_nllO1i_dataout;
                        nlllil <= wire_nllO1l_dataout;
                        nllliO <= wire_nllO1O_dataout;
                        nlllli <= wire_nllO0i_dataout;
                        nlllll <= wire_nllO0l_dataout;
                        nllOil <= nl1i0i;
                        nllOiO <= niOO1i;
                        nllOli <= niOO1l;
                        nllOll <= niOO1O;
                        nllOlO <= niOO0i;
                        nllOOi <= niOO0l;
                        nllOOl <= niOO0O;
                        nllOOO <= niOOii;
                        nlO00i <= writedata[3];
                        nlO00l <= writedata[4];
                        nlO00O <= writedata[5];
                        nlO01i <= writedata[0];
                        nlO01l <= writedata[1];
                        nlO01O <= writedata[2];
                        nlO0ii <= writedata[6];
                        nlO0il <= writedata[7];
                        nlO0iO <= writedata[8];
                        nlO0li <= writedata[9];
                        nlO0ll <= writedata[10];
                        nlO0lO <= writedata[11];
                        nlO0Oi <= writedata[12];
                        nlO0Ol <= writedata[13];
                        nlO0OO <= writedata[14];
                        nlO10i <= niOOll;
                        nlO10l <= niOOlO;
                        nlO10O <= niOOOi;
                        nlO11i <= niOOil;
                        nlO11l <= niOOiO;
                        nlO11O <= niOOli;
                        nlO1ii <= niOOOl;
                        nlO1il <= niOOOO;
                        nlO1iO <= wire_nlOiil_o;
                        nlO1li <= address[0];
                        nlO1ll <= address[1];
                        nlO1lO <= address[2];
                        nlO1Oi <= address[3];
                        nlO1Ol <= address[4];
                        nlO1OO <= wire_nlOi1O_dataout;
                        nlOi1i <= writedata[15];
                        nlOi1l <= wire_nlOi0i_o;
                        nlOOii <= wire_nlOi0O_o;
                        nlOOil <= nlOOli;
                        nlOOiO <= wire_nlOiil_o;
                        nlOOli <= wire_nlOili_o;
                        nlOOOi <= wire_nlOOOl_dataout;
                end
        end
        assign
                wire_nlOOlO_CLRN = ((nli001O58 ^ nli001O57) & (~ reset));
        and(wire_n0000i_dataout, wire_n000ll_dataout, nli100l);
        and(wire_n0000l_dataout, wire_n000lO_dataout, nli100l);
        and(wire_n0000O_dataout, wire_n000Oi_dataout, nli100l);
        assign          wire_n0001i_dataout = (nli100i === 1'b1) ? wire_n00iiO_dataout : wire_n000il_dataout;
        assign          wire_n0001l_dataout = (nli100i === 1'b1) ? wire_n00ili_dataout : wire_n000iO_dataout;
        and(wire_n0001O_dataout, wire_n000li_dataout, nli100l);
        assign          wire_n000i_dataout = (n01OO === 1'b1) ? wire_n00ii_o[1] : n00iO;
        and(wire_n000ii_dataout, wire_n000Ol_dataout, nli100l);
        and(wire_n000il_dataout, wire_n000OO_dataout, nli100l);
        and(wire_n000iO_dataout, wire_n00i1i_dataout, nli100l);
        assign          wire_n000l_dataout = (n01OO === 1'b1) ? wire_n00ii_o[2] : n01Ol;
        and(wire_n000li_dataout, wire_n00i1l_o[0], ~(wire_n00i1O_o));
        and(wire_n000ll_dataout, wire_n00i1l_o[1], ~(wire_n00i1O_o));
        and(wire_n000lO_dataout, wire_n00i1l_o[2], ~(wire_n00i1O_o));
        and(wire_n000O_dataout, wire_n00ii_o[3], n01OO);
        and(wire_n000Oi_dataout, wire_n00i1l_o[3], ~(wire_n00i1O_o));
        and(wire_n000Ol_dataout, wire_n00i1l_o[4], ~(wire_n00i1O_o));
        and(wire_n000OO_dataout, wire_n00i1l_o[5], ~(wire_n00i1O_o));
        assign          wire_n0011l_dataout = (nli100i === 1'b1) ? nli101l : wire_n0011O_dataout;
        and(wire_n0011O_dataout, nli101O, nli100l);
        and(wire_n001i_dataout, wire_n000i_dataout, ~(nli0i1i));
        or(wire_n001l_dataout, wire_n000l_dataout, nli0i1i);
        assign          wire_n001ll_dataout = (nli100i === 1'b1) ? wire_n00i0i_dataout : wire_n0001O_dataout;
        assign          wire_n001lO_dataout = (nli100i === 1'b1) ? wire_n00i0l_dataout : wire_n0000i_dataout;
        or(wire_n001O_dataout, wire_n000O_dataout, nli0i1i);
        assign          wire_n001Oi_dataout = (nli100i === 1'b1) ? wire_n00i0O_dataout : wire_n0000l_dataout;
        assign          wire_n001Ol_dataout = (nli100i === 1'b1) ? wire_n00iii_dataout : wire_n0000O_dataout;
        assign          wire_n001OO_dataout = (nli100i === 1'b1) ? wire_n00iil_dataout : wire_n000ii_dataout;
        and(wire_n00i0i_dataout, wire_n00i1l_o[0], ~(nli100O));
        and(wire_n00i0l_dataout, wire_n00i1l_o[1], ~(nli100O));
        and(wire_n00i0O_dataout, wire_n00i1l_o[2], ~(nli100O));
        and(wire_n00i1i_dataout, wire_n00i1l_o[6], ~(wire_n00i1O_o));
        and(wire_n00iii_dataout, wire_n00i1l_o[3], ~(nli100O));
        and(wire_n00iil_dataout, wire_n00i1l_o[4], ~(nli100O));
        and(wire_n00iiO_dataout, wire_n00i1l_o[5], ~(nli100O));
        and(wire_n00ili_dataout, wire_n00i1l_o[6], ~(nli100O));
        and(wire_n00l0i_dataout, (~ n01OiO), ~(nli10ii));
        and(wire_n00l1O_dataout, n01OiO, ~(nli10ii));
        and(wire_n00lii_dataout, wire_n00lli_dataout, ~((~ nli10lO)));
        and(wire_n00lil_dataout, nli10li, ~((~ nli10lO)));
        or(wire_n00liO_dataout, wire_n00lll_dataout, (~ nli10lO));
        and(wire_n00lli_dataout, nli10iO, ~(nli10li));
        and(wire_n00lll_dataout, (~ nli10iO), ~(nli10li));
        or(wire_n00O1l_dataout, wire_n00O0i_o[0], nli10lO);
        and(wire_n00O1O_dataout, wire_n00O0i_o[1], ~(nli10lO));
        and(wire_n0100i_dataout, wire_n1OiiO_o, ~(wire_n1i10O_dout));
        and(wire_n0100l_dataout, n0110l, ~(wire_n1i10O_dout));
        and(wire_n0100O_dataout, wire_n1Oili_dataout, ~(wire_n1i10O_dout));
        and(wire_n0101i_dataout, wire_n1Oi0O_o, ~(wire_n1i10O_dout));
        and(wire_n0101l_dataout, wire_n1Oiil_dataout, ~(wire_n1i10O_dout));
        and(wire_n0101O_dataout, n0111O, ~(wire_n1i10O_dout));
        and(wire_n010i_dataout, wire_n01ii_dataout, ~(nli00OO));
        and(wire_n010ii_dataout, wire_n1Oill_o, ~(wire_n1i10O_dout));
        and(wire_n010il_dataout, wire_n1OiOl_o, ~(wire_n1i10O_dout));
        or(wire_n010iO_dataout, wire_n1Ol1i_o, wire_n1i10O_dout);
        or(wire_n010l_dataout, wire_n01il_dataout, nli00OO);
        assign          wire_n010lO_dataout = (wire_n010Oi_o[1] === 1'b1) ? (~ ((~ n1i01i) & (~ n01i0i))) : (n1i01i | n01i0i);
        or(wire_n010O_dataout, wire_n01iO_dataout, nli00OO);
        and(wire_n011iO_dataout, n1OOiO, ~(wire_n1i10O_dout));
        and(wire_n011li_dataout, n1OOli, ~(wire_n1i10O_dout));
        and(wire_n011ll_dataout, n1OOll, ~(wire_n1i10O_dout));
        and(wire_n011lO_dataout, wire_n1Oi0l_dataout, ~(wire_n1i10O_dout));
        and(wire_n011Oi_dataout, n1OOOi, ~(wire_n1i10O_dout));
        and(wire_n011Ol_dataout, n1OOOl, ~(wire_n1i10O_dout));
        and(wire_n011OO_dataout, n1OOOO, ~(wire_n1i10O_dout));
        and(wire_n01i1l_dataout, wire_n010lO_dataout, ~(n01i1i));
        assign          wire_n01ii_dataout = (n011O === 1'b1) ? wire_n01li_o[1] : n01ll;
        assign          wire_n01il_dataout = (n011O === 1'b1) ? wire_n01li_o[2] : n011l;
        and(wire_n01iO_dataout, wire_n01li_o[3], n011O);
        assign          wire_n01lii_dataout = (n00O0l === 1'b1) ? wire_n01lll_dataout : wire_n01liO_dataout;
        assign          wire_n01lil_dataout = (n00O0l === 1'b1) ? wire_n01llO_dataout : wire_n01liO_dataout;
        and(wire_n01liO_dataout, nli11Ol, n00O1i);
        or(wire_n01lll_dataout, n01OOO, nli11Ol);
        or(wire_n01llO_dataout, n01l0l, nli11Ol);
        or(wire_n01Oli_dataout, (n00O1i & (~ nli11OO)), (n00O0O & (~ nli11OO)));
        and(wire_n0i00i_dataout, wire_n0i0ii_o[1], wire_n0i0il_o);
        and(wire_n0i00l_dataout, wire_n0i0ii_o[2], wire_n0i0il_o);
        and(wire_n0i00O_dataout, wire_n0i0ii_o[3], wire_n0i0il_o);
        and(wire_n0i01O_dataout, wire_n0i0ii_o[0], wire_n0i0il_o);
        and(wire_n0iilO_dataout, wire_n0il1i_o[0], wire_n0il1l_o);
        and(wire_n0iiOi_dataout, wire_n0il1i_o[1], wire_n0il1l_o);
        and(wire_n0iiOl_dataout, wire_n0il1i_o[2], wire_n0il1l_o);
        and(wire_n0iiOO_dataout, wire_n0il1i_o[3], wire_n0il1l_o);
        and(wire_n0il0i_dataout, wire_n00OOO_q_b[1], n0iOii);
        and(wire_n0il0l_dataout, wire_n00OOO_q_b[2], n0iOii);
        and(wire_n0il0O_dataout, wire_n00OOO_q_b[3], n0iOii);
        and(wire_n0il1O_dataout, wire_n00OOO_q_b[0], n0iOii);
        and(wire_n0ilii_dataout, wire_n00OOO_q_b[4], n0iOii);
        and(wire_n0ilil_dataout, wire_n00OOO_q_b[5], n0iOii);
        and(wire_n0iliO_dataout, wire_n00OOO_q_b[6], n0iOii);
        and(wire_n0illi_dataout, wire_n00OOO_q_b[7], n0iOii);
        and(wire_n0illl_dataout, wire_n00OOO_q_b[8], n0iOii);
        and(wire_n0illO_dataout, wire_n00OOO_q_b[9], n0iOii);
        assign          wire_n0l0lO_dataout = (((n0lili & nli10Ol) & (~ ((~ wire_n0illl_dataout) & (n0iO0i & (~ n0l0ll))))) === 1'b1) ? n0Oi1i : wire_n0l0Oi_dataout;
        and(wire_n0l0Oi_dataout, n0Oi1i, ((n0lili & (~ nli10Ol)) & (~ (n0iO0i & (~ wire_n0illl_dataout)))));
        or(wire_n0lill_dataout, (~ n0iO0i), wire_n0lilO_o[1]);
        and(wire_n0ll0i_dataout, n0ll1O, n0lO1i);
        and(wire_n0ll0l_dataout, n0llll, n0lO1i);
        and(wire_n0ll0O_dataout, n0lllO, n0lO1i);
        and(wire_n0llii_dataout, n0llOi, n0lO1i);
        and(wire_n0llil_dataout, n0llOl, n0lO1i);
        and(wire_n0lliO_dataout, n0llOO, n0lO1i);
        assign          wire_n0lO0i_dataout = (n0Oi1i === 1'b1) ? wire_n0iliO_dataout : wire_n0il0l_dataout;
        assign          wire_n0lO0l_dataout = (n0Oi1i === 1'b1) ? wire_n0illi_dataout : wire_n0il0O_dataout;
        assign          wire_n0lO1l_dataout = (n0Oi1i === 1'b1) ? wire_n0ilii_dataout : wire_n0il1O_dataout;
        assign          wire_n0lO1O_dataout = (n0Oi1i === 1'b1) ? wire_n0ilil_dataout : wire_n0il0i_dataout;
        and(wire_n0O00i_dataout, wire_n0ilil_dataout, nli10OO);
        and(wire_n0O00l_dataout, wire_n0iliO_dataout, nli10OO);
        and(wire_n0O00O_dataout, wire_n0illi_dataout, nli10OO);
        and(wire_n0O01i_dataout, wire_n0il0l_dataout, nli10OO);
        and(wire_n0O01l_dataout, wire_n0il0O_dataout, nli10OO);
        and(wire_n0O01O_dataout, wire_n0ilii_dataout, nli10OO);
        and(wire_n0O0ii_dataout, wire_n0illl_dataout, nli10OO);
        and(wire_n0O0il_dataout, wire_n0illO_dataout, nli10OO);
        and(wire_n0O1Ol_dataout, wire_n0il1O_dataout, nli10OO);
        and(wire_n0O1OO_dataout, wire_n0il0i_dataout, nli10OO);
        assign          wire_n0Oi0l_dataout = (nlil1il === 1'b1) ? wire_n0Oi0O_dataout : n0Oi1i;
        or(wire_n0Oi0O_dataout, (~ n0Oi1i), nli10OO);
        assign          wire_n0OOll_dataout = (nli1i1i === 1'b1) ? ni1i1O : wire_ni110i_dataout;
        assign          wire_n0OOlO_dataout = (nli1i1i === 1'b1) ? ni1i0i : wire_ni110l_dataout;
        assign          wire_n0OOOi_dataout = (nli1i1i === 1'b1) ? ni1i0l : wire_ni110O_dataout;
        assign          wire_n0OOOl_dataout = (nli1i1i === 1'b1) ? ni1i0O : wire_ni11ii_dataout;
        assign          wire_n0OOOO_dataout = (nli1i1i === 1'b1) ? ni1iii : wire_ni11il_dataout;
        and(wire_n1000i_dataout, wire_n10iii_dataout, ~(n10OOi));
        and(wire_n1000l_dataout, wire_n10iil_dataout, ~(n10OOi));
        and(wire_n1000O_dataout, wire_n10iiO_dataout, ~(n10OOi));
        and(wire_n1001i_dataout, wire_n10i0l_dataout, ~(n10OOi));
        and(wire_n1001l_dataout, (~ niO1i), ~(n10OOi));
        and(wire_n1001O_dataout, wire_n10i0O_dataout, ~(n10OOi));
        assign          wire_n100i_dataout = (n11OO === 1'b1) ? wire_n100O_o[1] : n10ii;
        and(wire_n100ii_dataout, wire_n10ili_dataout, ~(n10OOi));
        and(wire_n100il_dataout, wire_n10ill_dataout, ~(n10OOi));
        and(wire_n100iO_dataout, wire_n10ilO_dataout, ~(n10OOi));
        and(wire_n100l_dataout, wire_n100O_o[2], n11OO);
        and(wire_n100li_dataout, wire_n10iOi_dataout, ~(n10OOi));
        and(wire_n100ll_dataout, wire_n10iOl_dataout, ~(n10OOi));
        and(wire_n100lO_dataout, wire_n10iOO_dataout, ~(n10OOi));
        and(wire_n100Oi_dataout, wire_n10l1i_dataout, ~(n10OOi));
        and(wire_n100Ol_dataout, wire_n10l1l_dataout, ~(n10OOi));
        or(wire_n100OO_dataout, wire_n10l1O_dataout, n10OOi);
        or(wire_n101l_dataout, wire_n100i_dataout, nli000O);
        and(wire_n101lO_dataout, wire_n10i1i_dataout, ~(n10OOi));
        or(wire_n101O_dataout, wire_n100l_dataout, nli000O);
        and(wire_n101Oi_dataout, wire_n10i1l_dataout, ~(n10OOi));
        and(wire_n101Ol_dataout, wire_n10i1O_dataout, ~(n10OOi));
        and(wire_n101OO_dataout, wire_n10i0i_dataout, ~(n10OOi));
        and(wire_n10i0i_dataout, wire_nlOOOil_o, ~((~ niO1i)));
        and(wire_n10i0l_dataout, wire_nlOOOli_o, ~((~ niO1i)));
        and(wire_n10i0O_dataout, wire_nlOOOlO_o, ~((~ niO1i)));
        and(wire_n10i1i_dataout, wire_nlOOO0i_o, ~((~ niO1i)));
        and(wire_n10i1l_dataout, wire_nlOOO0O_dataout, ~((~ niO1i)));
        and(wire_n10i1O_dataout, wire_nlOOOii_dataout, ~((~ niO1i)));
        and(wire_n10iii_dataout, wire_nlOOOOl_dataout, ~((~ niO1i)));
        and(wire_n10iil_dataout, wire_nlOOOOO_o, ~((~ niO1i)));
        and(wire_n10iiO_dataout, wire_n1111i_o, ~((~ niO1i)));
        and(wire_n10ili_dataout, wire_n1111O_dataout, ~((~ niO1i)));
        and(wire_n10ill_dataout, wire_n1110i_o, ~((~ niO1i)));
        and(wire_n10ilO_dataout, wire_n1110O_dataout, ~((~ niO1i)));
        and(wire_n10iOi_dataout, wire_n111ii_dataout, ~((~ niO1i)));
        and(wire_n10iOl_dataout, wire_n111il_o, ~((~ niO1i)));
        and(wire_n10iOO_dataout, wire_n111li_o, ~((~ niO1i)));
        and(wire_n10l1i_dataout, wire_n111lO_o, ~((~ niO1i)));
        and(wire_n10l1l_dataout, wire_n111Ol_o, ~((~ niO1i)));
        and(wire_n10l1O_dataout, wire_n1101i_o, ~((~ niO1i)));
        and(wire_n10O0i_dataout, niOll, ~(n10OOi));
        and(wire_n10O0l_dataout, niOlO, ~(n10OOi));
        and(wire_n10O0O_dataout, niOOi, ~(n10OOi));
        and(wire_n10O1i_dataout, n0O1i, ~(n10OOi));
        and(wire_n10O1l_dataout, niO0O, ~(n10OOi));
        and(wire_n10O1O_dataout, niOli, ~(n10OOi));
        and(wire_n10Oii_dataout, niOOl, ~(n10OOi));
        and(wire_n10Oil_dataout, niOOO, ~(n10OOi));
        and(wire_n10OiO_dataout, nl11i, ~(n10OOi));
        and(wire_n10Oli_dataout, nl11l, ~(n10OOi));
        and(wire_n10Oll_dataout, niOii, ~(n10OOi));
        and(wire_n10OOl_dataout, wire_n10OOO_dataout, niO1i);
        or(wire_n10OOO_dataout, (~ n10OlO), ((~ n10lOO) & niO1i));
        and(wire_n1100i_dataout, wire_n110ii_dataout, ~(nl0OO1l));
        and(wire_n1100l_dataout, nl0OOli, ~(nl0OO1l));
        and(wire_n1100O_dataout, nl0OliO, ~(nl0OOli));
        and(wire_n1101O_dataout, wire_n1100O_dataout, ~(nl0OO1l));
        and(wire_n110ii_dataout, (~ nl0OliO), ~(nl0OOli));
        and(wire_n110iO_dataout, nl0OliO, ~(nl0OO0l));
        and(wire_n110li_dataout, (~ nl0OliO), ~(nl0OO0l));
        and(wire_n110ll_dataout, wire_n110OO_dataout, ~(nl0OlOl));
        and(wire_n110lO_dataout, nl0OllO, ~(nl0OlOl));
        and(wire_n110Oi_dataout, wire_n11i1i_dataout, ~(nl0OlOl));
        and(wire_n110Ol_dataout, wire_n11i1l_dataout, ~(nl0OlOl));
        and(wire_n110OO_dataout, wire_n11i1O_dataout, ~(nl0OllO));
        and(wire_n1110O_dataout, nl0OliO, n1010O);
        and(wire_n1111O_dataout, wire_n110Oi_dataout, n101ii);
        and(wire_n111ii_dataout, nl0OlOl, n101ii);
        and(wire_n11i0i_dataout, (~ nl0OliO), ~(nl0Olll));
        and(wire_n11i1i_dataout, nl0Olll, ~(nl0OllO));
        and(wire_n11i1l_dataout, wire_n11i0i_dataout, ~(nl0OllO));
        and(wire_n11i1O_dataout, nl0OliO, ~(nl0Olll));
        and(wire_n11ill_dataout, (~ nl0OO1i), ~(nl0OO1l));
        and(wire_n11ilO_dataout, nl0OO1i, ~(nl0OO1l));
        or(wire_n11iOl_dataout, (~ nl0OO1l), n10l0l);
        and(wire_n11iOO_dataout, nl0OO1l, ~(n10l0l));
        and(wire_n11l0i_dataout, wire_n11lii_dataout, ~(nl0OOiO));
        and(wire_n11l0l_dataout, wire_n11lil_dataout, ~(nl0OOii));
        or(wire_n11l0O_dataout, nl0OO0O, nl0OOii);
        and(wire_n11l1l_dataout, wire_n11l0l_dataout, ~(nl0OOiO));
        and(wire_n11l1O_dataout, wire_n11l0O_dataout, ~(nl0OOiO));
        and(wire_n11lii_dataout, wire_n11liO_dataout, ~(nl0OOii));
        and(wire_n11lil_dataout, nl0OO0i, ~(nl0OO0O));
        and(wire_n11liO_dataout, (~ nl0OO0i), ~(nl0OO0O));
        and(wire_n11O0i_dataout, nl0OOlO, ~(nl0OOOi));
        and(wire_n11O0l_dataout, (~ nl0OOlO), ~(nl0OOOi));
        or(wire_n1i0ll_dataout, wire_n1ii0l_dataout, wire_n1i10O_dout);
        and(wire_n1i0lO_dataout, wire_n1ii0O_dataout, ~(wire_n1i10O_dout));
        and(wire_n1i0Oi_dataout, wire_n1iiii_dataout, ~(wire_n1i10O_dout));
        or(wire_n1i0Ol_dataout, wire_n1iiil_dataout, wire_n1i10O_dout);
        or(wire_n1i0OO_dataout, wire_n1iiiO_dataout, wire_n1i10O_dout);
        and(wire_n1i1iO_dataout, wire_n1i1li_dataout, ~(wire_n1i10O_dout));
        or(wire_n1i1li_dataout, wire_n1i1ll_dataout, wire_n1OiOl_o);
        and(wire_n1i1ll_dataout, n1i01i, ~(wire_n1Oili_dataout));
        or(wire_n1i1Oi_dataout, wire_n1i1Ol_dataout, wire_n1i10O_dout);
        or(wire_n1i1Ol_dataout, wire_n1i1OO_dataout, wire_n1Oi0O_o);
        or(wire_n1i1OO_dataout, (~ n1i1il), nli111l);
        or(wire_n1ii0i_dataout, wire_n1iiOi_dataout, wire_n1i10O_dout);
        or(wire_n1ii0l_dataout, wire_n1iiOl_dataout, wire_n1OiOl_o);
        or(wire_n1ii0O_dataout, wire_n1iiOO_dataout, wire_n1OiOl_o);
        or(wire_n1ii1i_dataout, wire_n1iili_dataout, wire_n1i10O_dout);
        or(wire_n1ii1l_dataout, wire_n1iill_dataout, wire_n1i10O_dout);
        and(wire_n1ii1O_dataout, wire_n1iilO_dataout, ~(wire_n1i10O_dout));
        or(wire_n1iiii_dataout, wire_n1il1i_dataout, wire_n1OiOl_o);
        and(wire_n1iiil_dataout, wire_n1il1l_dataout, ~(wire_n1OiOl_o));
        or(wire_n1iiiO_dataout, wire_n1il1O_dataout, wire_n1OiOl_o);
        or(wire_n1iili_dataout, wire_n1il0i_dataout, wire_n1OiOl_o);
        or(wire_n1iill_dataout, wire_n1il0l_dataout, wire_n1OiOl_o);
        or(wire_n1iilO_dataout, wire_n1il0O_dataout, wire_n1OiOl_o);
        or(wire_n1iiOi_dataout, wire_n1ilii_dataout, wire_n1OiOl_o);
        or(wire_n1iiOl_dataout, wire_n1ilil_dataout, wire_n1Oili_dataout);
        or(wire_n1iiOO_dataout, wire_n1iliO_dataout, wire_n1Oili_dataout);
        or(wire_n1il0i_dataout, wire_n1ilOi_dataout, wire_n1Oili_dataout);
        or(wire_n1il0l_dataout, wire_n1ilOl_dataout, wire_n1Oili_dataout);
        or(wire_n1il0O_dataout, wire_n1ilOO_dataout, wire_n1Oili_dataout);
        and(wire_n1il1i_dataout, wire_n1illi_dataout, ~(wire_n1Oili_dataout));
        or(wire_n1il1l_dataout, wire_n1illl_dataout, wire_n1Oili_dataout);
        or(wire_n1il1O_dataout, wire_n1illO_dataout, wire_n1Oili_dataout);
        or(wire_n1ilii_dataout, wire_n1iO1i_dataout, wire_n1Oili_dataout);
        or(wire_n1ilil_dataout, wire_n1iO1l_dataout, n0110l);
        or(wire_n1iliO_dataout, wire_n1iO1O_dataout, n0110l);
        or(wire_n1illi_dataout, wire_n1iO0i_dataout, n0110l);
        or(wire_n1illl_dataout, wire_n1iO0l_dataout, n0110l);
        and(wire_n1illO_dataout, wire_n1iO0O_dataout, ~(n0110l));
        or(wire_n1ilOi_dataout, wire_n1iOii_dataout, n0110l);
        or(wire_n1ilOl_dataout, wire_n1iOil_dataout, n0110l);
        or(wire_n1ilOO_dataout, wire_n1iOiO_dataout, n0110l);
        or(wire_n1iO0i_dataout, wire_n1iOOi_dataout, wire_n1Oiil_dataout);
        or(wire_n1iO0l_dataout, wire_n1iOOl_dataout, wire_n1Oiil_dataout);
        and(wire_n1iO0O_dataout, wire_n1iOOO_dataout, ~(wire_n1Oiil_dataout));
        or(wire_n1iO1i_dataout, wire_n1iOli_dataout, n0110l);
        or(wire_n1iO1l_dataout, wire_n1iOll_dataout, wire_n1Oiil_dataout);
        or(wire_n1iO1O_dataout, wire_n1iOlO_dataout, wire_n1Oiil_dataout);
        or(wire_n1iOii_dataout, wire_n1l11i_dataout, wire_n1Oiil_dataout);
        or(wire_n1iOil_dataout, wire_n1l11l_dataout, wire_n1Oiil_dataout);
        or(wire_n1iOiO_dataout, wire_n1l11O_dataout, wire_n1Oiil_dataout);
        or(wire_n1iOli_dataout, wire_n1l10i_dataout, wire_n1Oiil_dataout);
        or(wire_n1iOll_dataout, wire_n1l10l_dataout, wire_n1OiiO_o);
        or(wire_n1iOlO_dataout, wire_n1l10O_dataout, wire_n1OiiO_o);
        or(wire_n1iOOi_dataout, wire_n1l1ii_dataout, wire_n1OiiO_o);
        or(wire_n1iOOl_dataout, wire_n1l1il_dataout, wire_n1OiiO_o);
        and(wire_n1iOOO_dataout, wire_n1l1iO_dataout, ~(wire_n1OiiO_o));
        or(wire_n1l00i_dataout, wire_n1l0Oi_dataout, nli111O);
        or(wire_n1l00l_dataout, wire_n1l0Ol_dataout, nli111O);
        or(wire_n1l00O_dataout, wire_n1l0OO_dataout, nli111O);
        or(wire_n1l01i_dataout, wire_n1l0li_dataout, nli111O);
        or(wire_n1l01l_dataout, wire_n1l0ll_dataout, nli111O);
        or(wire_n1l01O_dataout, wire_n1l0lO_dataout, nli111O);
        or(wire_n1l0ii_dataout, wire_n1li1i_dataout, nli111O);
        and(wire_n1l0il_dataout, wire_n1li1l_dataout, ~(wire_n1Oill_o));
        assign          wire_n1l0iO_dataout = (wire_n1Oill_o === 1'b1) ? nii00O : wire_n1li1O_dataout;
        assign          wire_n1l0li_dataout = (wire_n1Oill_o === 1'b1) ? nii0ii : wire_n1li0i_dataout;
        assign          wire_n1l0ll_dataout = (wire_n1Oill_o === 1'b1) ? nii0il : wire_n1li0l_dataout;
        assign          wire_n1l0lO_dataout = (wire_n1Oill_o === 1'b1) ? nii0iO : wire_n1li0O_dataout;
        assign          wire_n1l0Oi_dataout = (wire_n1Oill_o === 1'b1) ? nii0li : wire_n1liii_dataout;
        assign          wire_n1l0Ol_dataout = (wire_n1Oill_o === 1'b1) ? nii0ll : wire_n1liil_dataout;
        assign          wire_n1l0OO_dataout = (wire_n1Oill_o === 1'b1) ? nii0lO : wire_n1liiO_dataout;
        or(wire_n1l10i_dataout, wire_n1l1Oi_dataout, wire_n1OiiO_o);
        or(wire_n1l10l_dataout, wire_n1l1Ol_dataout, n0111O);
        and(wire_n1l10O_dataout, wire_n1l1OO_dataout, ~(n0111O));
        or(wire_n1l11i_dataout, wire_n1l1li_dataout, wire_n1OiiO_o);
        or(wire_n1l11l_dataout, wire_n1l1ll_dataout, wire_n1OiiO_o);
        or(wire_n1l11O_dataout, wire_n1l1lO_dataout, wire_n1OiiO_o);
        or(wire_n1l1ii_dataout, wire_n1l01i_dataout, n0111O);
        or(wire_n1l1il_dataout, wire_n1l01l_dataout, n0111O);
        or(wire_n1l1iO_dataout, wire_n1l01O_dataout, n0111O);
        or(wire_n1l1l_dataout, wire_n1l0i_o[1], (~ nli00iO));
        or(wire_n1l1li_dataout, wire_n1l00i_dataout, n0111O);
        or(wire_n1l1ll_dataout, wire_n1l00l_dataout, n0111O);
        or(wire_n1l1lO_dataout, wire_n1l00O_dataout, n0111O);
        or(wire_n1l1O_dataout, wire_n1l0i_o[2], (~ nli00iO));
        or(wire_n1l1Oi_dataout, wire_n1l0ii_dataout, n0111O);
        or(wire_n1l1Ol_dataout, wire_n1l0il_dataout, nli111O);
        and(wire_n1l1OO_dataout, wire_n1l0iO_dataout, ~(nli111O));
        and(wire_n1li0i_dataout, wire_n1liOi_dataout, ~(wire_n1Oi0O_o));
        or(wire_n1li0l_dataout, wire_n1liOl_dataout, wire_n1Oi0O_o);
        or(wire_n1li0O_dataout, wire_n1liOO_dataout, wire_n1Oi0O_o);
        assign          wire_n1li1i_dataout = (wire_n1Oill_o === 1'b1) ? nii0Oi : wire_n1lili_dataout;
        or(wire_n1li1l_dataout, wire_n1lill_dataout, wire_n1Oi0O_o);
        and(wire_n1li1O_dataout, wire_n1lilO_dataout, ~(wire_n1Oi0O_o));
        or(wire_n1liii_dataout, wire_n1ll1i_dataout, wire_n1Oi0O_o);
        or(wire_n1liil_dataout, wire_n1ll1l_dataout, wire_n1Oi0O_o);
        and(wire_n1liiO_dataout, wire_n1ll1O_dataout, ~(wire_n1Oi0O_o));
        or(wire_n1lili_dataout, wire_n1ll0i_dataout, wire_n1Oi0O_o);
        and(wire_n1lill_dataout, wire_n1ll0l_dataout, ~(n1OOOO));
        or(wire_n1lilO_dataout, wire_n1ll0O_dataout, n1OOOO);
        and(wire_n1liOi_dataout, wire_n1llii_dataout, ~(n1OOOO));
        or(wire_n1liOl_dataout, wire_n1llil_dataout, n1OOOO);
        and(wire_n1liOO_dataout, wire_n1lliO_dataout, ~(n1OOOO));
        or(wire_n1ll0i_dataout, wire_n1llOi_dataout, n1OOOO);
        and(wire_n1ll0l_dataout, wire_n1llOl_dataout, ~(n1OOOl));
        assign          wire_n1ll0O_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[0] : wire_n1llOO_dataout;
        or(wire_n1ll1i_dataout, wire_n1llli_dataout, n1OOOO);
        or(wire_n1ll1l_dataout, wire_n1llll_dataout, n1OOOO);
        and(wire_n1ll1O_dataout, wire_n1lllO_dataout, ~(n1OOOO));
        assign          wire_n1llii_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[1] : wire_n1lO1i_dataout;
        assign          wire_n1llil_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[2] : wire_n1lO1l_dataout;
        assign          wire_n1lliO_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[3] : wire_n1lO1O_dataout;
        assign          wire_n1llli_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[4] : wire_n1lO0i_dataout;
        assign          wire_n1llll_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[5] : wire_n1lO0l_dataout;
        assign          wire_n1lllO_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[6] : wire_n1lO0O_dataout;
        assign          wire_n1llOi_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[7] : wire_n1lOii_dataout;
        and(wire_n1llOl_dataout, wire_n1lOil_dataout, ~(n1OOOi));
        assign          wire_n1llOO_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[8] : wire_n1lOiO_dataout;
        assign          wire_n1lO0i_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[12] : wire_n1lOOi_dataout;
        assign          wire_n1lO0l_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[13] : wire_n1lOOl_dataout;
        assign          wire_n1lO0O_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[14] : wire_n1lOOO_dataout;
        assign          wire_n1lO1i_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[9] : wire_n1lOli_dataout;
        assign          wire_n1lO1l_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[10] : wire_n1lOll_dataout;
        assign          wire_n1lO1O_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[11] : wire_n1lOlO_dataout;
        assign          wire_n1lOii_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[15] : wire_n1O11i_dataout;
        or(wire_n1lOil_dataout, wire_n1O11l_dataout, wire_n1Oi0l_dataout);
        and(wire_n1lOiO_dataout, wire_n1O11O_dataout, ~(wire_n1Oi0l_dataout));
        and(wire_n1lOli_dataout, wire_n1O10i_dataout, ~(wire_n1Oi0l_dataout));
        or(wire_n1lOll_dataout, wire_n1O10l_dataout, wire_n1Oi0l_dataout);
        or(wire_n1lOlO_dataout, wire_n1O10O_dataout, wire_n1Oi0l_dataout);
        or(wire_n1lOOi_dataout, wire_n1O1ii_dataout, wire_n1Oi0l_dataout);
        or(wire_n1lOOl_dataout, wire_n1O1il_dataout, wire_n1Oi0l_dataout);
        and(wire_n1lOOO_dataout, wire_n1O1iO_dataout, ~(wire_n1Oi0l_dataout));
        assign          wire_n1O00i_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[7] : wire_n1O0Oi_dataout;
        and(wire_n1O00l_dataout, wire_n1O0Ol_dataout, ~(n1OOiO));
        and(wire_n1O00O_dataout, wire_n1i10l_dout[8], n1OOiO);
        assign          wire_n1O01i_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[4] : wire_n1O0li_dataout;
        assign          wire_n1O01l_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[5] : wire_n1O0ll_dataout;
        assign          wire_n1O01O_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[6] : wire_n1O0lO_dataout;
        and(wire_n1O0ii_dataout, wire_n1i10l_dout[9], n1OOiO);
        assign          wire_n1O0il_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[10] : wire_n1Oi1i_dataout;
        assign          wire_n1O0iO_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[11] : wire_n1O0Ol_dataout;
        or(wire_n1O0l_dataout, wire_n1OiO_o[1], (~ nli00lO));
        or(wire_n1O0li_dataout, wire_n1i10l_dout[12], ~(n1OOiO));
        assign          wire_n1O0ll_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[13] : wire_n1O0Ol_dataout;
        assign          wire_n1O0lO_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[14] : wire_n1O0OO_dataout;
        or(wire_n1O0O_dataout, wire_n1OiO_o[2], (~ nli00lO));
        assign          wire_n1O0Oi_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[15] : wire_n1Oi1i_dataout;
        or(wire_n1O0Ol_dataout, (~ nli111i), nli111l);
        and(wire_n1O0OO_dataout, nli111i, ~(nli111l));
        or(wire_n1O10i_dataout, wire_n1O1Oi_dataout, n1OOll);
        and(wire_n1O10l_dataout, wire_n1O1Ol_dataout, ~(n1OOll));
        and(wire_n1O10O_dataout, wire_n1O1OO_dataout, ~(n1OOll));
        or(wire_n1O11i_dataout, wire_n1O1li_dataout, wire_n1Oi0l_dataout);
        and(wire_n1O11l_dataout, wire_n1O1ll_dataout, ~(n1OOll));
        and(wire_n1O11O_dataout, wire_n1O1lO_dataout, ~(n1OOll));
        and(wire_n1O1ii_dataout, wire_n1O01i_dataout, ~(n1OOll));
        and(wire_n1O1il_dataout, wire_n1O01l_dataout, ~(n1OOll));
        or(wire_n1O1iO_dataout, wire_n1O01O_dataout, n1OOll);
        and(wire_n1O1li_dataout, wire_n1O00i_dataout, ~(n1OOll));
        and(wire_n1O1ll_dataout, wire_n1O00l_dataout, ~(n1OOli));
        assign          wire_n1O1lO_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[0] : wire_n1O00O_dataout;
        assign          wire_n1O1Oi_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[1] : wire_n1O0ii_dataout;
        assign          wire_n1O1Ol_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[2] : wire_n1O0il_dataout;
        assign          wire_n1O1OO_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[3] : wire_n1O0iO_dataout;
        and(wire_n1Oi0l_dataout, nli11iO, n1OOlO);
        or(wire_n1Oi1i_dataout, (~ nli111i), nli111l);
        or(wire_n1Oii_dataout, wire_n1OiO_o[3], (~ nli00lO));
        and(wire_n1Oiil_dataout, n1i1il, n0110i);
        or(wire_n1Oil_dataout, wire_n1OiO_o[4], (~ nli00lO));
        and(wire_n1Oili_dataout, nli11li, n0110O);
        and(wire_n1Ol0i_dataout, nli11lO, ~(nli11iO));
        and(wire_n1Ol0l_dataout, wire_n1Olii_dataout, ~(nli11iO));
        and(wire_n1Ol0O_dataout, nli11il, ~(nli11lO));
        and(wire_n1Ol1O_dataout, wire_n1Ol0O_dataout, ~(nli11iO));
        and(wire_n1Olii_dataout, (~ nli11il), ~(nli11lO));
        and(wire_n1Olll_dataout, wire_n1OlOl_dataout, ~(nli11Oi));
        and(wire_n1OllO_dataout, nli11lO, ~(nli11Oi));
        and(wire_n1OlOi_dataout, wire_n1OlOO_dataout, ~(nli11Oi));
        and(wire_n1OlOl_dataout, nli11ll, ~(nli11lO));
        and(wire_n1OlOO_dataout, (~ nli11ll), ~(nli11lO));
        and(wire_ni01il_dataout, wire_ni01lO_o[0], wire_ni01Oi_o);
        and(wire_ni01iO_dataout, wire_ni01lO_o[1], wire_ni01Oi_o);
        and(wire_ni01li_dataout, wire_ni01lO_o[2], wire_ni01Oi_o);
        and(wire_ni01ll_dataout, wire_ni01lO_o[3], wire_ni01Oi_o);
        and(wire_ni0i0i_dataout, wire_ni0i0l_o[3], wire_ni0i0O_o);
        and(wire_ni0i1i_dataout, wire_ni0i0l_o[0], wire_ni0i0O_o);
        and(wire_ni0i1l_dataout, wire_ni0i0l_o[1], wire_ni0i0O_o);
        and(wire_ni0i1O_dataout, wire_ni0i0l_o[2], wire_ni0i0O_o);
        and(wire_ni0iii_dataout, wire_ni1O0i_q_b[0], ni0lli);
        and(wire_ni0iil_dataout, wire_ni1O0i_q_b[1], ni0lli);
        and(wire_ni0iiO_dataout, wire_ni1O0i_q_b[2], ni0lli);
        and(wire_ni0ili_dataout, wire_ni1O0i_q_b[3], ni0lli);
        and(wire_ni0ill_dataout, wire_ni1O0i_q_b[4], ni0lli);
        and(wire_ni0ilO_dataout, wire_ni1O0i_q_b[5], ni0lli);
        and(wire_ni0iOi_dataout, wire_ni1O0i_q_b[6], ni0lli);
        and(wire_ni0iOl_dataout, wire_ni1O0i_q_b[7], ni0lli);
        and(wire_ni0iOO_dataout, wire_ni1O0i_q_b[8], ni0lli);
        and(wire_ni0l1i_dataout, wire_ni1O0i_q_b[9], ni0lli);
        and(wire_ni10il_dataout, nli1i0l, ~(nli1i0O));
        and(wire_ni10iO_dataout, (~ nli1i0l), ~(nli1i0O));
        and(wire_ni110i_dataout, ni1l0i, ni10Ol);
        and(wire_ni110l_dataout, ni1l0l, ni10Ol);
        and(wire_ni110O_dataout, ni1l0O, ni10Ol);
        assign          wire_ni111i_dataout = (nli1i1i === 1'b1) ? ni1iil : wire_ni11iO_dataout;
        assign          wire_ni111l_dataout = (nli1i1i === 1'b1) ? ni1iiO : wire_ni11li_dataout;
        assign          wire_ni111O_dataout = (nli1i1i === 1'b1) ? ni1ili : wire_ni11ll_dataout;
        and(wire_ni11ii_dataout, ni1lii, ni10Ol);
        and(wire_ni11il_dataout, ni1lil, ni10Ol);
        and(wire_ni11iO_dataout, ni1liO, ni10Ol);
        and(wire_ni11li_dataout, ni1lli, ni10Ol);
        and(wire_ni11ll_dataout, ni1lll, ni10Ol);
        and(wire_niii0i_dataout, nli1iiO, nli1ill);
        or(wire_niii1i_dataout, niiilO, nil1OO);
        assign          wire_niii1O_dataout = (nli1ili === 1'b1) ? nli1iil : wire_niii0i_dataout;
        assign          wire_niiiOi_dataout = (nli1ili === 1'b1) ? wire_niiO0O_dataout : wire_niil0l_dataout;
        assign          wire_niiiOl_dataout = (nli1ili === 1'b1) ? wire_niiOii_dataout : wire_niil0O_dataout;
        assign          wire_niiiOO_dataout = (nli1ili === 1'b1) ? wire_niiOil_dataout : wire_niilii_dataout;
        assign          wire_niil0i_dataout = (nli1ili === 1'b1) ? wire_niiOlO_dataout : wire_niilll_dataout;
        and(wire_niil0l_dataout, wire_niillO_dataout, nli1ill);
        and(wire_niil0O_dataout, wire_niilOi_dataout, nli1ill);
        assign          wire_niil1i_dataout = (nli1ili === 1'b1) ? wire_niiOiO_dataout : wire_niilil_dataout;
        assign          wire_niil1l_dataout = (nli1ili === 1'b1) ? wire_niiOli_dataout : wire_niiliO_dataout;
        assign          wire_niil1O_dataout = (nli1ili === 1'b1) ? wire_niiOll_dataout : wire_niilli_dataout;
        and(wire_niilii_dataout, wire_niilOl_dataout, nli1ill);
        and(wire_niilil_dataout, wire_niilOO_dataout, nli1ill);
        and(wire_niiliO_dataout, wire_niiO1i_dataout, nli1ill);
        and(wire_niilli_dataout, wire_niiO1l_dataout, nli1ill);
        and(wire_niilll_dataout, wire_niiO1O_dataout, nli1ill);
        and(wire_niillO_dataout, wire_niiO0i_o[0], ~(wire_niiO0l_o));
        and(wire_niilOi_dataout, wire_niiO0i_o[1], ~(wire_niiO0l_o));
        and(wire_niilOl_dataout, wire_niiO0i_o[2], ~(wire_niiO0l_o));
        and(wire_niilOO_dataout, wire_niiO0i_o[3], ~(wire_niiO0l_o));
        and(wire_niiO0O_dataout, wire_niiO0i_o[0], ~(nli1ilO));
        and(wire_niiO1i_dataout, wire_niiO0i_o[4], ~(wire_niiO0l_o));
        and(wire_niiO1l_dataout, wire_niiO0i_o[5], ~(wire_niiO0l_o));
        and(wire_niiO1O_dataout, wire_niiO0i_o[6], ~(wire_niiO0l_o));
        and(wire_niiOii_dataout, wire_niiO0i_o[1], ~(nli1ilO));
        and(wire_niiOil_dataout, wire_niiO0i_o[2], ~(nli1ilO));
        and(wire_niiOiO_dataout, wire_niiO0i_o[3], ~(nli1ilO));
        and(wire_niiOli_dataout, wire_niiO0i_o[4], ~(nli1ilO));
        and(wire_niiOll_dataout, wire_niiO0i_o[5], ~(nli1ilO));
        and(wire_niiOlO_dataout, wire_niiO0i_o[6], ~(nli1ilO));
        and(wire_nil10l_dataout, nii0OO, ~(nli1iOi));
        and(wire_nil10O_dataout, (~ nii0OO), ~(nli1iOi));
        and(wire_nil1iO_dataout, nli1iOO, ~(nli1l1i));
        and(wire_nil1li_dataout, (~ nli1iOO), ~(nli1l1i));
        assign          wire_nill0O_dataout = (nliil0l === 1'b1) ? wire_nilO1i_dataout : niliil;
        assign          wire_nillii_dataout = (nliil0l === 1'b1) ? wire_nilO1l_dataout : nilill;
        assign          wire_nillil_dataout = (nliil0l === 1'b1) ? wire_nilO1O_dataout : nililO;
        assign          wire_nilliO_dataout = (nliil0l === 1'b1) ? wire_nilO0i_dataout : niliOi;
        assign          wire_nillli_dataout = (nliil0l === 1'b1) ? wire_nilO0l_dataout : niliOl;
        assign          wire_nillll_dataout = (nliil0l === 1'b1) ? wire_nilO0O_dataout : niliOO;
        assign          wire_nilllO_dataout = (nliil0l === 1'b1) ? wire_nilOii_dataout : nill1i;
        assign          wire_nillOi_dataout = (nliil0l === 1'b1) ? wire_nilOil_dataout : nill1l;
        assign          wire_nillOl_dataout = (nliil0l === 1'b1) ? wire_nilOiO_dataout : nill1O;
        assign          wire_nillOO_dataout = (nliil0l === 1'b1) ? wire_nilOli_dataout : nill0i;
        assign          wire_nilO0i_dataout = (nli1l0i === 1'b1) ? nilOOO : n0Olii;
        assign          wire_nilO0l_dataout = (nli1l0i === 1'b1) ? niO11i : n0Olil;
        assign          wire_nilO0O_dataout = (nli1l0i === 1'b1) ? niO11l : n0OliO;
        assign          wire_nilO1i_dataout = (nli1l0i === 1'b1) ? nill0l : n0Ol0i;
        assign          wire_nilO1l_dataout = (nli1l0i === 1'b1) ? nilOOi : n0Ol0l;
        assign          wire_nilO1O_dataout = (nli1l0i === 1'b1) ? nilOOl : n0Ol0O;
        assign          wire_nilOii_dataout = (nli1l0i === 1'b1) ? niO11O : n0Olli;
        assign          wire_nilOil_dataout = (nli1l0i === 1'b1) ? niO10i : n0Olll;
        assign          wire_nilOiO_dataout = (nli1l0i === 1'b1) ? niO10l : n0Ol1O;
        assign          wire_nilOli_dataout = (nli1l0i === 1'b1) ? niO10O : n0OO1l;
        assign          wire_niO0ll_dataout = (wire_niO0lO_o[1] === 1'b1) ? (~ ((~ mii_tx_en) & (~ niOi1O))) : (mii_tx_en | niOi1O);
        assign          wire_niO1iO_dataout = (nliil0l === 1'b1) ? wire_niO1li_dataout : niO1ii;
        and(wire_niO1l_dataout, wire_niO1O_dataout, ~(((~ n0O1i) | (~ wire_nl0ii_syncstatus[0]))));
        or(wire_niO1li_dataout, (~ niO1ii), nli1l0i);
        or(wire_niO1O_dataout, n0lil, ((wire_nl0ii_syncstatus[0] & wire_nl0ii_rlv) & (nlii1Ol22 ^ nlii1Ol21)));
        assign          wire_niOi0l_dataout = (wire_niOi0O_o[1] === 1'b1) ? (~ ((~ nii00l) | (~ niOl1i))) : (niOill & (nii00l & niOl1i));
        and(wire_niOi1i_dataout, wire_niO0ll_dataout, ~(niO0OO));
        and(wire_niOilO_dataout, wire_niOi0l_dataout, ~(niOiOl));
        and(wire_nl000i_dataout, nl0i1i, ~((nl00OO & (~ nl00Ol))));
        or(wire_nl00il_dataout, wire_nl00iO_dataout, nlliOO);
        and(wire_nl00iO_dataout, nl010l, ~((nli1liO & nlO1iO)));
        and(wire_nl010O_dataout, wire_nl01iO_dataout, ~((~ nl00ll)));
        and(wire_nl01ii_dataout, wire_nl01li_dataout, ~((~ nl00ll)));
        or(wire_nl01il_dataout, wire_nl01ll_dataout, (~ nl00ll));
        assign          wire_nl01iO_dataout = (nli1lii === 1'b1) ? wire_nl000i_dataout : wire_nl01lO_dataout;
        assign          wire_nl01li_dataout = (nli1lii === 1'b1) ? nl00Ol : wire_nl01Oi_dataout;
        assign          wire_nl01ll_dataout = (nli1lii === 1'b1) ? nl00OO : wire_nl01Ol_dataout;
        assign          wire_nl01lO_dataout = (nli1l0O === 1'b1) ? wire_nl01OO_dataout : nl011l;
        assign          wire_nl01Oi_dataout = (nli1l0O === 1'b1) ? nli0lO : nl011O;
        assign          wire_nl01Ol_dataout = (nli1l0O === 1'b1) ? nli0Oi : nl010i;
        and(wire_nl01OO_dataout, (~ nli0Ol), ~((nli0Oi & (~ nli0lO))));
        and(wire_nl101i_dataout, wire_nl1i1l_o, nlO1iO);
        and(wire_nl101l_dataout, wire_nl1i1O_o, nlO1iO);
        and(wire_nl110i_dataout, wire_nl100l_o, nlO1iO);
        and(wire_nl110l_dataout, wire_nl100O_o, nlO1iO);
        and(wire_nl110O_dataout, wire_nl10ii_o, nlO1iO);
        and(wire_nl111l_dataout, wire_nl101O_o, nlO1iO);
        and(wire_nl111O_dataout, wire_nl100i_o, nlO1iO);
        and(wire_nl11ii_dataout, wire_nl10il_o, nlO1iO);
        and(wire_nl11il_dataout, wire_nl10iO_o, nlO1iO);
        and(wire_nl11iO_dataout, wire_nl10li_o, nlO1iO);
        and(wire_nl11li_dataout, wire_nl10ll_o, nlO1iO);
        and(wire_nl11ll_dataout, wire_nl10lO_o, nlO1iO);
        and(wire_nl11lO_dataout, wire_nl10Oi_o, nlO1iO);
        and(wire_nl11Oi_dataout, wire_nl10Ol_o, nlO1iO);
        and(wire_nl11Ol_dataout, wire_nl10OO_o, nlO1iO);
        and(wire_nl11OO_dataout, wire_nl1i1i_o, nlO1iO);
        and(wire_nl1lii_dataout, nli1OO, nli1l0l);
        and(wire_nl1lil_dataout, nli01O, nli1l0l);
        and(wire_nl1liO_dataout, nli00i, nli1l0l);
        and(wire_nl1lli_dataout, nli00l, nli1l0l);
        and(wire_nl1lll_dataout, nli00O, nli1l0l);
        and(wire_nl1llO_dataout, nli0ii, nli1l0l);
        and(wire_nl1lOi_dataout, nli0il, nli1l0l);
        and(wire_nl1lOl_dataout, nli0iO, nli1l0l);
        and(wire_nl1lOO_dataout, nli0li, nli1l0l);
        and(wire_nl1O0i_dataout, nli0Ol, nli1l0l);
        and(wire_nl1O0l_dataout, nli0OO, nli1l0l);
        and(wire_nl1O0O_dataout, nlii1i, nli1l0l);
        and(wire_nl1O1i_dataout, nli0ll, nli1l0l);
        and(wire_nl1O1l_dataout, nli0lO, nli1l0l);
        and(wire_nl1O1O_dataout, nli0Oi, nli1l0l);
        and(wire_nl1Oii_dataout, nlii1O, nli1l0l);
        or(wire_nli01i_dataout, wire_nli01l_dataout, nll010l);
        and(wire_nli01l_dataout, nli1Ol, ~(nli1lO));
        or(wire_nli1ii_dataout, wire_nli1il_dataout, nli10O);
        and(wire_nli1il_dataout, nli10l, ~((nll1iO & (nli1O0l & (~ nlO1iO)))));
        and(wire_nli1l_dataout, wire_nl01O_locked, ~(reset));
        and(wire_nlii0l_dataout, nlii0i, ~(nl00ll));
        and(wire_nlii0O_dataout, nliill, ~(nl00ll));
        and(wire_nliiii_dataout, nliilO, ~(nl00ll));
        and(wire_nliiil_dataout, nliiOl, ~(nl00ll));
        and(wire_nliiiO_dataout, nliiOO, ~(nl00ll));
        or(wire_nliil1l_dataout, wire_nliil1O_dataout, nliiOlO);
        or(wire_nliil1O_dataout, (((~ nliiOlO) & (~ nliilOO)) & nl0O11O), (((~ nliiOlO) & nliilOO) & nl0O10i));
        and(wire_nliili_dataout, nlil1l, ~(nl00ll));
        and(wire_nliiO0i_dataout, wire_nliiOii_o[3], ~(nl0O11O));
        and(wire_nliiO0l_dataout, wire_nliiOii_o[4], ~(nl0O11O));
        and(wire_nliiO0O_dataout, wire_nliiOii_o[5], ~(nl0O11O));
        and(wire_nliiO1i_dataout, wire_nliiOii_o[0], ~(nl0O11O));
        and(wire_nliiO1l_dataout, wire_nliiOii_o[1], ~(nl0O11O));
        and(wire_nliiO1O_dataout, wire_nliiOii_o[2], ~(nl0O11O));
        and(wire_nliiOil_dataout, wire_nliiOll_o[0], ~(nl0O10i));
        and(wire_nliiOiO_dataout, wire_nliiOll_o[1], ~(nl0O10i));
        and(wire_nliiOli_dataout, wire_nliiOll_o[2], ~(nl0O10i));
        and(wire_nlil00i_dataout, wire_nlil0li_o[0], ~(nl0O10l));
        and(wire_nlil00l_dataout, wire_nlil0li_o[1], ~(nl0O10l));
        and(wire_nlil00O_dataout, wire_nlil0li_o[2], ~(nl0O10l));
        and(wire_nlil0ii_dataout, wire_nlil0li_o[3], ~(nl0O10l));
        and(wire_nlil0il_dataout, wire_nlil0li_o[4], ~(nl0O10l));
        and(wire_nlil0iO_dataout, wire_nlil0li_o[5], ~(nl0O10l));
        and(wire_nlil0ll_dataout, wire_nlil0Ol_o[0], ~(nl0O10O));
        and(wire_nlil0lO_dataout, wire_nlil0Ol_o[1], ~(nl0O10O));
        and(wire_nlil0Oi_dataout, wire_nlil0Ol_o[2], ~(nl0O10O));
        or(wire_nlil10l_dataout, wire_nlil10O_dataout, nlil0OO);
        or(wire_nlil10O_dataout, (((~ nlil0OO) & (~ nlil01O)) & nl0O10l), (((~ nlil0OO) & nlil01O) & nl0O10O));
        or(wire_nlilli_dataout, wire_nlilll_dataout, (nll1OO & (~ nlilii)));
        and(wire_nlilll_dataout, nlil0i, ~(((~ nll1OO) & nlil0i)));
        and(wire_nlilOO_dataout, wire_nliO1i_dataout, ~((nll1iO & (nli1Oll & (~ nlO1iO)))));
        or(wire_nliO1i_dataout, nlilii, (nll1OO & nlil0i));
        assign          wire_nliOll_dataout = (nl00ll === 1'b1) ? wire_nliOlO_dataout : wire_nliOOO_dataout;
        and(wire_nliOlO_dataout, nliOiO, ((~ nll10l) & ((~ nl0i1i) & (~ nl00Oi))));
        and(wire_nliOlOl_dataout, wire_nliOlOO_dataout, ~(wire_nliliil_dout));
        or(wire_nliOlOO_dataout, wire_nliOO1i_dataout, wire_nlO0O1i_o);
        and(wire_nliOO0i_dataout, wire_nliliii_dout, ~(wire_nliliil_dout));
        and(wire_nliOO0O_dataout, wire_nliOOii_dataout, ~(wire_nliliil_dout));
        and(wire_nliOO1i_dataout, nll010l, ~((wire_nlO0Oii_o | (wire_nlO0OiO_o | wire_nlO0O0l_o))));
        or(wire_nliOOii_dataout, wire_nliOOil_dataout, niO1i);
        and(wire_nliOOil_dataout, nliOlOi, ~(nl0O1ii));
        and(wire_nliOOO_dataout, nliOiO, ~(nll10l));
        and(wire_nll000i_dataout, wire_nll00ii_dataout, ~(wire_nliliil_dout));
        and(wire_nll000l_dataout, wire_nll00il_dataout, ~(wire_nliliil_dout));
        assign          wire_nll000O_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[0] : wire_nll00iO_dataout;
        and(wire_nll001O_dataout, wire_nll000O_dataout, ~(wire_nliliil_dout));
        assign          wire_nll00ii_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[1] : wire_nll00li_dataout;
        assign          wire_nll00il_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[2] : wire_nll00ll_dataout;
        and(wire_nll00iO_dataout, wire_nll00lO_dataout, ~((~ nlOl10i)));
        and(wire_nll00li_dataout, wire_nll00Oi_dataout, ~((~ nlOl10i)));
        and(wire_nll00ll_dataout, wire_nll00Ol_dataout, ~((~ nlOl10i)));
        and(wire_nll00lO_dataout, nll01lO, ~(nlOlOlO));
        and(wire_nll00Oi_dataout, nll01OO, ~(nlOlOlO));
        and(wire_nll00Ol_dataout, nll001i, ~(nlOlOlO));
        assign          wire_nll011i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[18] : nll11lO;
        assign          wire_nll011l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[19] : nll11Oi;
        assign          wire_nll011O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[20] : nll11Ol;
        and(wire_nll01ii_dataout, wire_nlO0llO_o, ~(wire_nliliil_dout));
        and(wire_nll01iO_dataout, wire_nll01li_dataout, ~(wire_nliliil_dout));
        or(wire_nll01li_dataout, wire_nll01ll_dataout, wire_nlO0O1O_o);
        and(wire_nll01ll_dataout, nll010O, ~(wire_nlO0Oii_o));
        and(wire_nll01Oi_dataout, ((~ nl0O1OO) & nl0O1iO), ~(wire_nliliil_dout));
        and(wire_nll0i1O_dataout, (nll0i0l | wire_nliliiO_dout), ~(wire_nliliil_dout));
        and(wire_nll0iii_dataout, (nlOi1lO | nlOi1ll), ~(wire_nliliil_dout));
        and(wire_nll0iil_dataout, (nlOi1ll | nlO101l), ~(wire_nliliil_dout));
        and(wire_nll0llO_dataout, wire_nll0OOi_dataout, ~(wire_nliliil_dout));
        and(wire_nll0lOi_dataout, wire_nll0OOl_dataout, ~(wire_nliliil_dout));
        and(wire_nll0lOl_dataout, wire_nll0OOO_dataout, ~(wire_nliliil_dout));
        and(wire_nll0lOO_dataout, wire_nlli11i_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O0i_dataout, wire_nlli10l_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O0l_dataout, wire_nlli10O_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O0O_dataout, wire_nlli1ii_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O1i_dataout, wire_nlli11l_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O1l_dataout, wire_nlli11O_dataout, ~(wire_nliliil_dout));
        and(wire_nll0O1O_dataout, wire_nlli10i_dataout, ~(wire_nliliil_dout));
        and(wire_nll0Oii_dataout, wire_nlli1il_dataout, ~(wire_nliliil_dout));
        and(wire_nll0Oil_dataout, wire_nlli1iO_dataout, ~(wire_nliliil_dout));
        and(wire_nll0OiO_dataout, wire_nlli1li_dataout, ~(wire_nliliil_dout));
        and(wire_nll0Oli_dataout, wire_nlli1ll_dataout, ~(wire_nliliil_dout));
        and(wire_nll0Oll_dataout, wire_nlli1lO_dataout, ~(wire_nliliil_dout));
        and(wire_nll0OlO_dataout, wire_nlli1Oi_dataout, ~(wire_nliliil_dout));
        and(wire_nll0OOi_dataout, wire_nlli1Ol_dataout, ~(nlOi01l));
        and(wire_nll0OOl_dataout, wire_nlli1OO_dataout, ~(nlOi01l));
        and(wire_nll0OOO_dataout, wire_nlli01i_dataout, ~(nlOi01l));
        and(wire_nll100i_dataout, wire_nll1ili_dataout, ~(wire_nliliil_dout));
        and(wire_nll100l_dataout, wire_nll1ill_dataout, ~(wire_nliliil_dout));
        and(wire_nll100O_dataout, wire_nll1ilO_dataout, ~(wire_nliliil_dout));
        and(wire_nll101i_dataout, wire_nll1iii_dataout, ~(wire_nliliil_dout));
        and(wire_nll101l_dataout, wire_nll1iil_dataout, ~(wire_nliliil_dout));
        and(wire_nll101O_dataout, wire_nll1iiO_dataout, ~(wire_nliliil_dout));
        and(wire_nll10ii_dataout, wire_nll1iOi_dataout, ~(wire_nliliil_dout));
        and(wire_nll10il_dataout, wire_nll1iOl_dataout, ~(wire_nliliil_dout));
        and(wire_nll10iO_dataout, wire_nll1iOO_dataout, ~(wire_nliliil_dout));
        and(wire_nll10li_dataout, wire_nll1l1i_dataout, ~(wire_nliliil_dout));
        and(wire_nll10ll_dataout, wire_nll1l1l_dataout, ~(wire_nliliil_dout));
        and(wire_nll10lO_dataout, wire_nll1l1O_dataout, ~(wire_nliliil_dout));
        and(wire_nll10Oi_dataout, wire_nll1l0i_dataout, ~(wire_nliliil_dout));
        and(wire_nll10Ol_dataout, wire_nll1l0l_dataout, ~(wire_nliliil_dout));
        and(wire_nll10OO_dataout, wire_nll1l0O_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i0i_dataout, wire_nll1lli_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i0l_dataout, wire_nll1lll_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i0O_dataout, wire_nll1llO_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i1i_dataout, wire_nll1lii_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i1l_dataout, wire_nll1lil_dataout, ~(wire_nliliil_dout));
        and(wire_nll1i1O_dataout, wire_nll1liO_dataout, ~(wire_nliliil_dout));
        and(wire_nll1iii_dataout, wire_nll1lOi_dataout, ~(niO1i));
        and(wire_nll1iil_dataout, wire_nll1lOl_dataout, ~(niO1i));
        and(wire_nll1iiO_dataout, wire_nll1lOO_dataout, ~(niO1i));
        and(wire_nll1ili_dataout, wire_nll1O1i_dataout, ~(niO1i));
        and(wire_nll1ill_dataout, wire_nll1O1l_dataout, ~(niO1i));
        and(wire_nll1ilO_dataout, wire_nll1O1O_dataout, ~(niO1i));
        and(wire_nll1iOi_dataout, wire_nll1O0i_dataout, ~(niO1i));
        and(wire_nll1iOl_dataout, wire_nll1O0l_dataout, ~(niO1i));
        and(wire_nll1iOO_dataout, wire_nll1O0O_dataout, ~(niO1i));
        and(wire_nll1l0i_dataout, wire_nll1Oli_dataout, ~(niO1i));
        and(wire_nll1l0l_dataout, wire_nll1Oll_dataout, ~(niO1i));
        and(wire_nll1l0O_dataout, wire_nll1OlO_dataout, ~(niO1i));
        and(wire_nll1l1i_dataout, wire_nll1Oii_dataout, ~(niO1i));
        and(wire_nll1l1l_dataout, wire_nll1Oil_dataout, ~(niO1i));
        and(wire_nll1l1O_dataout, wire_nll1OiO_dataout, ~(niO1i));
        and(wire_nll1li_dataout, wire_nll1ll_dataout, ~(nll11OO));
        and(wire_nll1lii_dataout, wire_nll1OOi_dataout, ~(niO1i));
        and(wire_nll1lil_dataout, wire_nll1OOl_dataout, ~(niO1i));
        and(wire_nll1liO_dataout, wire_nll1OOO_dataout, ~(niO1i));
        assign          wire_nll1ll_dataout = (nli1OOO === 1'b1) ? nlO0li : nll11i;
        and(wire_nll1lli_dataout, wire_nll011i_dataout, ~(niO1i));
        and(wire_nll1lll_dataout, wire_nll011l_dataout, ~(niO1i));
        and(wire_nll1llO_dataout, wire_nll011O_dataout, ~(niO1i));
        and(wire_nll1lO_dataout, wire_nll1Oi_dataout, ~(nll1il));
        assign          wire_nll1lOi_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[0] : nliOO0l;
        assign          wire_nll1lOl_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[1] : nliOOli;
        assign          wire_nll1lOO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[2] : nliOOll;
        assign          wire_nll1O0i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[6] : nliOOOO;
        assign          wire_nll1O0l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[7] : nll111i;
        assign          wire_nll1O0O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[8] : nll111l;
        assign          wire_nll1O1i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[3] : nliOOlO;
        assign          wire_nll1O1l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[4] : nliOOOi;
        assign          wire_nll1O1O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[5] : nliOOOl;
        assign          wire_nll1Oi_dataout = (nli1OOO === 1'b1) ? nlOi1i : nll1il;
        assign          wire_nll1Oii_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[9] : nll111O;
        assign          wire_nll1Oil_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[10] : nll110i;
        assign          wire_nll1OiO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[11] : nll110l;
        assign          wire_nll1Oli_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[12] : nll110O;
        assign          wire_nll1Oll_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[13] : nll11ii;
        assign          wire_nll1OlO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[14] : nll11il;
        assign          wire_nll1OOi_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[15] : nll11iO;
        assign          wire_nll1OOl_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[16] : nll11li;
        assign          wire_nll1OOO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[17] : nll11ll;
        assign          wire_nlli00i_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nlii0l_dataout : wire_nllii0l_dataout;
        assign          wire_nlli00l_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nlii0O_dataout : wire_nllii0O_dataout;
        assign          wire_nlli00O_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiii_dataout : wire_nlliiii_dataout;
        and(wire_nlli01i_dataout, wire_nllii1l_dataout, ~(wire_nlO0O0l_o));
        and(wire_nlli01l_dataout, wire_nllii1O_dataout, ~(wire_nlO0O0l_o));
        and(wire_nlli01O_dataout, wire_nllii0i_dataout, ~(wire_nlO0O0l_o));
        or(wire_nlli0i_dataout, nll0Ol, nli010O);
        assign          wire_nlli0ii_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiil_dataout : wire_nlliiil_dataout;
        and(wire_nlli0il_dataout, wire_nlliiiO_dataout, ~(wire_nlO0O0l_o));
        and(wire_nlli0iO_dataout, wire_nlliili_dataout, ~(wire_nlO0O0l_o));
        and(wire_nlli0li_dataout, wire_nlliill_dataout, ~(wire_nlO0O0l_o));
        assign          wire_nlli0ll_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiiO_dataout : wire_nlliilO_dataout;
        assign          wire_nlli0lO_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliili_dataout : wire_nlliiOi_dataout;
        and(wire_nlli0Oi_dataout, wire_nlliiOl_dataout, ~(wire_nlO0O0l_o));
        and(wire_nlli0Ol_dataout, wire_nlliiOO_dataout, ~(wire_nlO0O0l_o));
        assign          wire_nlli0OO_dataout = (wire_nlO0O1O_o === 1'b1) ? nl00ll : nll0i0O;
        and(wire_nlli10i_dataout, wire_nlli00l_dataout, ~(nlOi01l));
        and(wire_nlli10l_dataout, wire_nlli00O_dataout, ~(nlOi01l));
        and(wire_nlli10O_dataout, wire_nlli0ii_dataout, ~(nlOi01l));
        and(wire_nlli11i_dataout, wire_nlli01l_dataout, ~(nlOi01l));
        and(wire_nlli11l_dataout, wire_nlli01O_dataout, ~(nlOi01l));
        and(wire_nlli11O_dataout, wire_nlli00i_dataout, ~(nlOi01l));
        and(wire_nlli1ii_dataout, wire_nlli0il_dataout, ~(nlOi01l));
        and(wire_nlli1il_dataout, wire_nlli0iO_dataout, ~(nlOi01l));
        and(wire_nlli1iO_dataout, wire_nlli0li_dataout, ~(nlOi01l));
        and(wire_nlli1li_dataout, wire_nlli0ll_dataout, ~(nlOi01l));
        and(wire_nlli1ll_dataout, wire_nlli0lO_dataout, ~(nlOi01l));
        and(wire_nlli1lO_dataout, wire_nlli0Oi_dataout, ~(nlOi01l));
        and(wire_nlli1Oi_dataout, wire_nlli0Ol_dataout, ~(nlOi01l));
        assign          wire_nlli1Ol_dataout = (wire_nlO0O0l_o === 1'b1) ? nl00ll : wire_nlli0OO_dataout;
        and(wire_nlli1OO_dataout, wire_nllii1i_dataout, ~(wire_nlO0O0l_o));
        and(wire_nllii0i_dataout, nll0iOl, ~(wire_nlO0O1O_o));
        assign          wire_nllii0l_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nlii0l_dataout : nll0iOO;
        assign          wire_nllii0O_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nlii0O_dataout : nll0l1i;
        and(wire_nllii1i_dataout, nll0ill, ~(wire_nlO0O1O_o));
        and(wire_nllii1l_dataout, nll0ilO, ~(wire_nlO0O1O_o));
        and(wire_nllii1O_dataout, nll0iOi, ~(wire_nlO0O1O_o));
        assign          wire_nlliiii_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiii_dataout : nll0l1l;
        assign          wire_nlliiil_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiil_dataout : nll0l1O;
        and(wire_nlliiiO_dataout, nll0l0i, ~(wire_nlO0O1O_o));
        and(wire_nlliili_dataout, nll0l0l, ~(wire_nlO0O1O_o));
        and(wire_nlliill_dataout, nll0l0O, ~(wire_nlO0O1O_o));
        assign          wire_nlliilO_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiiO_dataout : nll0lii;
        assign          wire_nlliiOi_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliili_dataout : nll0lil;
        or(wire_nlliiOl_dataout, nll0liO, wire_nlO0O1O_o);
        and(wire_nlliiOO_dataout, nll0lli, ~(wire_nlO0O1O_o));
        and(wire_nllil1l_dataout, wire_nllil1O_dataout, ~(wire_nliliil_dout));
        and(wire_nllil1O_dataout, nl0O1li, ~((nlOi01l | nl0O1Oi)));
        and(wire_nlliOll_dataout, wire_nlll01l_dataout, ~(wire_nliliil_dout));
        and(wire_nlliOlO_dataout, wire_nlll01O_dataout, ~(wire_nliliil_dout));
        and(wire_nlliOOi_dataout, wire_nlll00i_dataout, ~(wire_nliliil_dout));
        and(wire_nlliOOl_dataout, wire_nlll00l_dataout, ~(wire_nliliil_dout));
        and(wire_nlliOOO_dataout, wire_nlll00O_dataout, ~(wire_nliliil_dout));
        and(wire_nlll00i_dataout, wire_nlllili_dataout, ~(nl0O1lO));
        and(wire_nlll00l_dataout, wire_nlllill_dataout, ~(nl0O1lO));
        and(wire_nlll00O_dataout, wire_nlllilO_dataout, ~(nl0O1lO));
        and(wire_nlll01i_dataout, wire_nllliii_dataout, ~(wire_nliliil_dout));
        and(wire_nlll01l_dataout, wire_nllliil_dataout, ~(nl0O1lO));
        and(wire_nlll01O_dataout, wire_nllliiO_dataout, ~(nl0O1lO));
        and(wire_nlll0ii_dataout, wire_nllliOi_dataout, ~(nl0O1lO));
        and(wire_nlll0il_dataout, wire_nllliOl_dataout, ~(nl0O1lO));
        and(wire_nlll0iO_dataout, wire_nllliOO_dataout, ~(nl0O1lO));
        and(wire_nlll0li_dataout, wire_nllll1i_dataout, ~(nl0O1lO));
        and(wire_nlll0ll_dataout, wire_nllll1l_dataout, ~(nl0O1lO));
        and(wire_nlll0lO_dataout, wire_nllll1O_dataout, ~(nl0O1lO));
        and(wire_nlll0Oi_dataout, wire_nllll0i_dataout, ~(nl0O1lO));
        and(wire_nlll0Ol_dataout, wire_nllll0l_dataout, ~(nl0O1lO));
        and(wire_nlll0OO_dataout, wire_nllll0O_dataout, ~(nl0O1lO));
        and(wire_nlll10i_dataout, wire_nlll0li_dataout, ~(wire_nliliil_dout));
        and(wire_nlll10l_dataout, wire_nlll0ll_dataout, ~(wire_nliliil_dout));
        and(wire_nlll10O_dataout, wire_nlll0lO_dataout, ~(wire_nliliil_dout));
        and(wire_nlll11i_dataout, wire_nlll0ii_dataout, ~(wire_nliliil_dout));
        and(wire_nlll11l_dataout, wire_nlll0il_dataout, ~(wire_nliliil_dout));
        and(wire_nlll11O_dataout, wire_nlll0iO_dataout, ~(wire_nliliil_dout));
        or(wire_nlll1i_dataout, nllill, nli010O);
        and(wire_nlll1ii_dataout, wire_nlll0Oi_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1il_dataout, wire_nlll0Ol_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1iO_dataout, wire_nlll0OO_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1li_dataout, wire_nllli1i_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1ll_dataout, wire_nllli1l_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1lO_dataout, wire_nllli1O_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1Oi_dataout, wire_nllli0i_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1Ol_dataout, wire_nllli0l_dataout, ~(wire_nliliil_dout));
        and(wire_nlll1OO_dataout, wire_nllli0O_dataout, ~(wire_nliliil_dout));
        and(wire_nllli0i_dataout, wire_nllllli_dataout, ~(nl0O1lO));
        and(wire_nllli0l_dataout, wire_nllllll_dataout, ~(nl0O1lO));
        and(wire_nllli0O_dataout, wire_nlllllO_dataout, ~(nl0O1lO));
        and(wire_nllli1i_dataout, wire_nllllii_dataout, ~(nl0O1lO));
        and(wire_nllli1l_dataout, wire_nllllil_dataout, ~(nl0O1lO));
        and(wire_nllli1O_dataout, wire_nlllliO_dataout, ~(nl0O1lO));
        and(wire_nllliii_dataout, wire_nllllOi_dataout, ~(nl0O1lO));
        assign          wire_nllliil_dataout = (nl0O1ll === 1'b1) ? wire_nllllOl_dataout : nllil1i;
        assign          wire_nllliiO_dataout = (nl0O1ll === 1'b1) ? wire_nllllOO_dataout : nllil0l;
        assign          wire_nlllili_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1i_dataout : nllil0O;
        assign          wire_nlllill_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1l_dataout : nllilii;
        assign          wire_nlllilO_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1O_dataout : nllilil;
        assign          wire_nllliOi_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0i_dataout : nlliliO;
        assign          wire_nllliOl_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0l_dataout : nllilli;
        assign          wire_nllliOO_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0O_dataout : nllilll;
        assign          wire_nllll0i_dataout = (nl0O1ll === 1'b1) ? wire_nlllOli_dataout : nllilOO;
        assign          wire_nllll0l_dataout = (nl0O1ll === 1'b1) ? wire_nlllOll_dataout : nlliO1i;
        assign          wire_nllll0O_dataout = (nl0O1ll === 1'b1) ? wire_nlllOlO_dataout : nlliO1l;
        assign          wire_nllll1i_dataout = (nl0O1ll === 1'b1) ? wire_nlllOii_dataout : nllillO;
        assign          wire_nllll1l_dataout = (nl0O1ll === 1'b1) ? wire_nlllOil_dataout : nllilOi;
        assign          wire_nllll1O_dataout = (nl0O1ll === 1'b1) ? wire_nlllOiO_dataout : nllilOl;
        assign          wire_nllllii_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOi_dataout : nlliO1O;
        assign          wire_nllllil_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOl_dataout : nlliO0i;
        assign          wire_nlllliO_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOO_dataout : nlliO0l;
        assign          wire_nllllli_dataout = (nl0O1ll === 1'b1) ? wire_nllO11i_dataout : nlliO0O;
        assign          wire_nllllll_dataout = (nl0O1ll === 1'b1) ? wire_nllO11l_dataout : nlliOii;
        assign          wire_nlllllO_dataout = (nl0O1ll === 1'b1) ? wire_nllO11O_dataout : nlliOil;
        assign          wire_nllllOi_dataout = (nl0O1ll === 1'b1) ? wire_nllO10i_dataout : nlliOiO;
        assign          wire_nllllOl_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[0] : nllil1i;
        assign          wire_nllllOO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[1] : nllil0l;
        assign          wire_nlllO0i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[5] : nlliliO;
        assign          wire_nlllO0l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[6] : nllilli;
        assign          wire_nlllO0O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[7] : nllilll;
        assign          wire_nlllO1i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[2] : nllil0O;
        assign          wire_nlllO1l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[3] : nllilii;
        assign          wire_nlllO1O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[4] : nllilil;
        and(wire_nlllOi_dataout, wire_nllO0O_o[0], nli01ii);
        assign          wire_nlllOii_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[8] : nllillO;
        assign          wire_nlllOil_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[9] : nllilOi;
        assign          wire_nlllOiO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[10] : nllilOl;
        and(wire_nlllOl_dataout, wire_nllO0O_o[1], nli01ii);
        assign          wire_nlllOli_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[11] : nllilOO;
        assign          wire_nlllOll_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[12] : nlliO1i;
        assign          wire_nlllOlO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[13] : nlliO1l;
        and(wire_nlllOO_dataout, wire_nllO0O_o[2], nli01ii);
        assign          wire_nlllOOi_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[14] : nlliO1O;
        assign          wire_nlllOOl_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[15] : nlliO0i;
        assign          wire_nlllOOO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[16] : nlliO0l;
        and(wire_nllO01i_dataout, ((~ nl0O1OO) & (nl0O00i & nl0O01i)), ~(wire_nliliil_dout));
        and(wire_nllO01l_dataout, ((~ nl0O1OO) & nl0O00i), ~(wire_nliliil_dout));
        and(wire_nllO0i_dataout, wire_nllO0O_o[6], nli01ii);
        and(wire_nllO0l_dataout, wire_nllO0O_o[7], nli01ii);
        assign          wire_nllO10i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[20] : nlliOiO;
        assign          wire_nllO11i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[17] : nlliO0O;
        assign          wire_nllO11l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[18] : nlliOii;
        assign          wire_nllO11O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[19] : nlliOil;
        and(wire_nllO1i_dataout, wire_nllO0O_o[3], nli01ii);
        and(wire_nllO1l_dataout, wire_nllO0O_o[4], nli01ii);
        and(wire_nllO1O_dataout, wire_nllO0O_o[5], nli01ii);
        and(wire_nllO1OO_dataout, ((~ (nlO101i ^ nllOOOl)) & nl0O1Ol), ~(wire_nliliil_dout));
        and(wire_nllOi0O_dataout, wire_nllOili_dataout, ~(wire_nliliil_dout));
        and(wire_nllOiii_dataout, wire_nllOill_dataout, ~(wire_nliliil_dout));
        and(wire_nllOiil_dataout, wire_nllOl0l_dataout, ~(wire_nliliil_dout));
        and(wire_nllOiiO_dataout, wire_nllOl0O_dataout, ~(wire_nliliil_dout));
        assign          wire_nllOili_dataout = (nlOlOlO === 1'b1) ? wire_nllOiOl_dataout : wire_nllOilO_dataout;
        assign          wire_nllOill_dataout = (nlOlOlO === 1'b1) ? wire_nllOiOO_dataout : wire_nllOiOi_dataout;
        and(wire_nllOilO_dataout, nllO1Ol, ~(nlOl10i));
        and(wire_nllOiOi_dataout, nllOi1l, ~(nlOl10i));
        and(wire_nllOiOl_dataout, wire_nllOl1i_dataout, nl0O01l);
        and(wire_nllOiOO_dataout, wire_nllOl1l_dataout, nl0O01l);
        assign          wire_nllOl0l_dataout = (nlOlOlO === 1'b1) ? wire_nllOliO_dataout : wire_nllOlii_dataout;
        assign          wire_nllOl0O_dataout = (nlOlOlO === 1'b1) ? wire_nllOlli_dataout : wire_nllOlil_dataout;
        assign          wire_nllOl1i_dataout = ((~ nl0O01i) === 1'b1) ? wire_nllOl1O_o[0] : nllO1Ol;
        assign          wire_nllOl1l_dataout = ((~ nl0O01i) === 1'b1) ? wire_nllOl1O_o[1] : nllOi1l;
        and(wire_nllOlii_dataout, nllOi1O, ~(nlOl10i));
        and(wire_nllOlil_dataout, nllOi0i, ~(nlOl10i));
        and(wire_nllOliO_dataout, wire_nllOlll_dataout, nl0O00l);
        and(wire_nllOlli_dataout, wire_nllOllO_dataout, nl0O00l);
        assign          wire_nllOlll_dataout = ((~ nl0O00i) === 1'b1) ? wire_nllOlOi_o[0] : nllOi1O;
        assign          wire_nllOllO_dataout = ((~ nl0O00i) === 1'b1) ? wire_nllOlOi_o[1] : nllOi0i;
        assign          wire_nlO000i_dataout = (nl0O0il === 1'b1) ? nlO11Oi : nllOOlO;
        assign          wire_nlO000l_dataout = (nl0O0il === 1'b1) ? nlO11Ol : nllOOOi;
        assign          wire_nlO000O_dataout = (nl0O0il === 1'b1) ? nlO101i : nllOOOl;
        assign          wire_nlO001i_dataout = (nl0O0il === 1'b1) ? nlO11li : nllOOiO;
        assign          wire_nlO001l_dataout = (nl0O0il === 1'b1) ? nlO11ll : nllOOli;
        assign          wire_nlO001O_dataout = (nl0O0il === 1'b1) ? nlO11lO : nllOOll;
        and(wire_nlO00il_dataout, wire_nlO0iiO_dataout, ~(nlOl10i));
        and(wire_nlO00iO_dataout, wire_nlO0ili_dataout, ~(nlOl10i));
        and(wire_nlO00li_dataout, wire_nlO0ill_dataout, ~(nlOl10i));
        and(wire_nlO00ll_dataout, wire_nlO0ilO_dataout, ~(nlOl10i));
        and(wire_nlO00lO_dataout, wire_nlO0iOi_dataout, ~(nlOl10i));
        and(wire_nlO00Oi_dataout, wire_nlO0iOl_dataout, ~(nlOl10i));
        and(wire_nlO00Ol_dataout, wire_nlO0iOO_dataout, ~(nlOl10i));
        and(wire_nlO00OO_dataout, wire_nlO0l1i_dataout, ~(nlOl10i));
        and(wire_nlO010i_dataout, wire_nlO0i0O_dataout, ~(nlOi01l));
        and(wire_nlO010l_dataout, wire_nlO0iii_dataout, ~(nlOi01l));
        and(wire_nlO010O_dataout, wire_nlO0iil_dataout, ~(nlOi01l));
        and(wire_nlO011i_dataout, wire_nlO0i1O_dataout, ~(nlOi01l));
        and(wire_nlO011l_dataout, wire_nlO0i0i_dataout, ~(nlOi01l));
        and(wire_nlO011O_dataout, wire_nlO0i0l_dataout, ~(nlOi01l));
        assign          wire_nlO01ii_dataout = (nl0O0il === 1'b1) ? nlO111i : nllOi0l;
        assign          wire_nlO01il_dataout = (nl0O0il === 1'b1) ? nlO111l : nllOO1i;
        assign          wire_nlO01iO_dataout = (nl0O0il === 1'b1) ? nlO111O : nllOO1l;
        assign          wire_nlO01li_dataout = (nl0O0il === 1'b1) ? nlO110i : nllOO1O;
        assign          wire_nlO01ll_dataout = (nl0O0il === 1'b1) ? nlO110l : nllOO0i;
        assign          wire_nlO01lO_dataout = (nl0O0il === 1'b1) ? nlO110O : nllOO0l;
        assign          wire_nlO01Oi_dataout = (nl0O0il === 1'b1) ? nlO11ii : nllOO0O;
        assign          wire_nlO01Ol_dataout = (nl0O0il === 1'b1) ? nlO11il : nllOOii;
        assign          wire_nlO01OO_dataout = (nl0O0il === 1'b1) ? nlO11iO : nllOOil;
        and(wire_nlO0i0i_dataout, wire_nlO0l0l_dataout, ~(nlOl10i));
        and(wire_nlO0i0l_dataout, wire_nlO0l0O_dataout, ~(nlOl10i));
        and(wire_nlO0i0O_dataout, wire_nlO0lii_dataout, ~(nlOl10i));
        and(wire_nlO0i1i_dataout, wire_nlO0l1l_dataout, ~(nlOl10i));
        and(wire_nlO0i1l_dataout, wire_nlO0l1O_dataout, ~(nlOl10i));
        and(wire_nlO0i1O_dataout, wire_nlO0l0i_dataout, ~(nlOl10i));
        and(wire_nlO0iii_dataout, wire_nlO0lil_dataout, ~(nlOl10i));
        and(wire_nlO0iil_dataout, wire_nlO0liO_dataout, ~(nlOl10i));
        assign          wire_nlO0iiO_dataout = (nlOlOlO === 1'b1) ? nlOO11l : nlO111i;
        assign          wire_nlO0ili_dataout = (nlOlOlO === 1'b1) ? nlOO10i : nlO111l;
        assign          wire_nlO0ill_dataout = (nlOlOlO === 1'b1) ? nlOO10l : nlO111O;
        assign          wire_nlO0ilO_dataout = (nlOlOlO === 1'b1) ? nlOO10O : nlO110i;
        assign          wire_nlO0iOi_dataout = (nlOlOlO === 1'b1) ? nlOO1ii : nlO110l;
        assign          wire_nlO0iOl_dataout = (nlOlOlO === 1'b1) ? nlOO1il : nlO110O;
        assign          wire_nlO0iOO_dataout = (nlOlOlO === 1'b1) ? nlOO1iO : nlO11ii;
        assign          wire_nlO0l0i_dataout = (nlOlOlO === 1'b1) ? nlOO1Oi : nlO11ll;
        assign          wire_nlO0l0l_dataout = (nlOlOlO === 1'b1) ? nlOO1Ol : nlO11lO;
        assign          wire_nlO0l0O_dataout = (nlOlOlO === 1'b1) ? nlOO1OO : nlO11Oi;
        assign          wire_nlO0l1i_dataout = (nlOlOlO === 1'b1) ? nlOO1li : nlO11il;
        assign          wire_nlO0l1l_dataout = (nlOlOlO === 1'b1) ? nlOO1ll : nlO11iO;
        assign          wire_nlO0l1O_dataout = (nlOlOlO === 1'b1) ? nlOO1lO : nlO11li;
        assign          wire_nlO0lii_dataout = (nlOlOlO === 1'b1) ? nlOO01i : nlO11Ol;
        assign          wire_nlO0lil_dataout = (nlOlOlO === 1'b1) ? nlOO01l : nlO11OO;
        assign          wire_nlO0liO_dataout = (nlOlOlO === 1'b1) ? nlOO01O : nlO101i;
        and(wire_nlO0Oll_dataout, (~ nl0Oi0i), ~(nl0Oi1i));
        and(wire_nlO0OlO_dataout, nl0Oi0i, ~(nl0Oi1i));
        and(wire_nlO0OOl_dataout, (~ nl0Oi0i), ~(nl0Oi1l));
        and(wire_nlO0OOO_dataout, nl0Oi0i, ~(nl0Oi1l));
        and(wire_nlO100i_dataout, wire_nlO1l0O_dataout, ~(wire_nliliil_dout));
        and(wire_nlO100l_dataout, wire_nlO1lii_dataout, ~(wire_nliliil_dout));
        and(wire_nlO100O_dataout, wire_nlO1lil_dataout, ~(wire_nliliil_dout));
        and(wire_nlO101O_dataout, wire_nlO1l0l_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10ii_dataout, wire_nlO1liO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10il_dataout, wire_nlO1lli_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10iO_dataout, wire_nlO1lll_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10li_dataout, wire_nlO1llO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10ll_dataout, wire_nlO1lOi_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10lO_dataout, wire_nlO1lOl_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10Oi_dataout, wire_nlO1lOO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10Ol_dataout, wire_nlO1O1i_dataout, ~(wire_nliliil_dout));
        and(wire_nlO10OO_dataout, wire_nlO1O1l_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i0i_dataout, wire_nlO1O0O_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i0l_dataout, wire_nlO1Oii_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i0O_dataout, wire_nlO1Oil_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i1i_dataout, wire_nlO1O1O_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i1l_dataout, wire_nlO1O0i_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1i1O_dataout, wire_nlO1O0l_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iii_dataout, wire_nlO1OiO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iil_dataout, wire_nlO1Oli_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iiO_dataout, wire_nlO1Oll_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1ili_dataout, wire_nlO1OlO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1ill_dataout, wire_nlO1OOi_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1ilO_dataout, wire_nlO1OOl_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iOi_dataout, wire_nlO1OOO_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iOl_dataout, wire_nlO011i_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1iOO_dataout, wire_nlO011l_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1l0i_dataout, wire_nlO010O_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1l0l_dataout, wire_nlO01ii_dataout, ~(nlOi01l));
        and(wire_nlO1l0O_dataout, wire_nlO01il_dataout, ~(nlOi01l));
        and(wire_nlO1l1i_dataout, wire_nlO011O_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1l1l_dataout, wire_nlO010i_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1l1O_dataout, wire_nlO010l_dataout, ~(wire_nliliil_dout));
        and(wire_nlO1lii_dataout, wire_nlO01iO_dataout, ~(nlOi01l));
        and(wire_nlO1lil_dataout, wire_nlO01li_dataout, ~(nlOi01l));
        and(wire_nlO1liO_dataout, wire_nlO01ll_dataout, ~(nlOi01l));
        and(wire_nlO1lli_dataout, wire_nlO01lO_dataout, ~(nlOi01l));
        and(wire_nlO1lll_dataout, wire_nlO01Oi_dataout, ~(nlOi01l));
        and(wire_nlO1llO_dataout, wire_nlO01Ol_dataout, ~(nlOi01l));
        and(wire_nlO1lOi_dataout, wire_nlO01OO_dataout, ~(nlOi01l));
        and(wire_nlO1lOl_dataout, wire_nlO001i_dataout, ~(nlOi01l));
        and(wire_nlO1lOO_dataout, wire_nlO001l_dataout, ~(nlOi01l));
        and(wire_nlO1O0i_dataout, wire_nlO000O_dataout, ~(nlOi01l));
        and(wire_nlO1O0l_dataout, nl0O0ii, ~(nlOi01l));
        and(wire_nlO1O0O_dataout, wire_nlO00il_dataout, ~(nlOi01l));
        and(wire_nlO1O1i_dataout, wire_nlO001O_dataout, ~(nlOi01l));
        and(wire_nlO1O1l_dataout, wire_nlO000i_dataout, ~(nlOi01l));
        and(wire_nlO1O1O_dataout, wire_nlO000l_dataout, ~(nlOi01l));
        and(wire_nlO1Oii_dataout, wire_nlO00iO_dataout, ~(nlOi01l));
        and(wire_nlO1Oil_dataout, wire_nlO00li_dataout, ~(nlOi01l));
        and(wire_nlO1OiO_dataout, wire_nlO00ll_dataout, ~(nlOi01l));
        and(wire_nlO1Oli_dataout, wire_nlO00lO_dataout, ~(nlOi01l));
        and(wire_nlO1Oll_dataout, wire_nlO00Oi_dataout, ~(nlOi01l));
        and(wire_nlO1OlO_dataout, wire_nlO00Ol_dataout, ~(nlOi01l));
        and(wire_nlO1OOi_dataout, wire_nlO00OO_dataout, ~(nlOi01l));
        and(wire_nlO1OOl_dataout, wire_nlO0i1i_dataout, ~(nlOi01l));
        and(wire_nlO1OOO_dataout, wire_nlO0i1l_dataout, ~(nlOi01l));
        and(wire_nlOi00i_dataout, wire_nlO0lli_o, ~(nl0Oiii));
        and(wire_nlOi00l_dataout, wire_nlO0llO_o, ~(nl0Oiii));
        and(wire_nlOi00O_dataout, wire_nlO0lOl_o, ~(nl0Oiii));
        and(wire_nlOi0ii_dataout, wire_nlO0O1i_o, ~(nl0Oiii));
        and(wire_nlOi0il_dataout, wire_nlO0O1O_o, ~(nl0Oiii));
        and(wire_nlOi0iO_dataout, wire_nlO0O0l_o, ~(nl0Oiii));
        and(wire_nlOi0li_dataout, wire_nlO0Oii_o, ~(nl0Oiii));
        or(wire_nlOi0ll_dataout, wire_nlO0OiO_o, nl0Oiii);
        and(wire_nlOi10i_dataout, wire_nlOi10O_dataout, ~(nl0Oi0l));
        and(wire_nlOi10l_dataout, (~ nl0Oi1O), ~(nl0Oi0i));
        or(wire_nlOi10O_dataout, nl0Oi1O, nl0Oi0i);
        and(wire_nlOi11O_dataout, wire_nlOi10l_dataout, ~(nl0Oi0l));
        and(wire_nlOi1O_dataout, write, wire_nlOili_o);
        and(wire_nlOiiOl_dataout, wire_nlOiiOO_dataout, ~(n10OOi));
        or(wire_nlOiiOO_dataout, wire_nlOil1i_dataout, wire_n111li_o);
        and(wire_nlOil1i_dataout, nlOiilO, ~((wire_nlOOOii_dataout | (wire_n1111O_dataout | (wire_n111ii_dataout | wire_nlOOOli_o)))));
        and(wire_nlOl00i_dataout, nlOiOll, ~(n10OOi));
        and(wire_nlOl00l_dataout, nlOiOlO, ~(n10OOi));
        and(wire_nlOl00O_dataout, wire_nlOlliO_dataout, ~(n10OOi));
        and(wire_nlOl01i_dataout, nlOiOil, ~(n10OOi));
        and(wire_nlOl01l_dataout, nlOiOiO, ~(n10OOi));
        and(wire_nlOl01O_dataout, nlOiOli, ~(n10OOi));
        and(wire_nlOl0i_dataout, wire_nlOlil_dataout, ~((~ nlOOOi)));
        and(wire_nlOl0ii_dataout, wire_nlOllli_dataout, ~(n10OOi));
        and(wire_nlOl0il_dataout, wire_nlOllll_dataout, ~(n10OOi));
        and(wire_nlOl0iO_dataout, wire_nlOlllO_dataout, ~(n10OOi));
        or(wire_nlOl0l_dataout, wire_nlOliO_dataout, (~ nlOOOi));
        and(wire_nlOl0li_dataout, wire_nlOllOi_dataout, ~(n10OOi));
        and(wire_nlOl0ll_dataout, wire_nlOllOl_dataout, ~(n10OOi));
        and(wire_nlOl0lO_dataout, wire_nlOllOO_dataout, ~(n10OOi));
        and(wire_nlOl0O_dataout, nli01lO, ~(nli01OO));
        and(wire_nlOl0Oi_dataout, wire_nlOlO1i_dataout, ~(n10OOi));
        and(wire_nlOl0Ol_dataout, wire_nlOli0l_dataout, ~(n10OOi));
        and(wire_nlOl0OO_dataout, wire_nlOliii_dataout, ~(n10OOi));
        and(wire_nlOl10l_dataout, nlOillO, ~(n10OOi));
        and(wire_nlOl10O_dataout, nlOilOi, ~(n10OOi));
        and(wire_nlOl1i_dataout, nli01OO, ~((~ nlOOOi)));
        and(wire_nlOl1ii_dataout, nlOilOl, ~(n10OOi));
        and(wire_nlOl1il_dataout, nlOilOO, ~(n10OOi));
        and(wire_nlOl1iO_dataout, nlOiO1i, ~(n10OOi));
        and(wire_nlOl1l_dataout, wire_nlOl0O_dataout, ~((~ nlOOOi)));
        and(wire_nlOl1li_dataout, nlOiO1l, ~(n10OOi));
        and(wire_nlOl1ll_dataout, nlOiO1O, ~(n10OOi));
        and(wire_nlOl1lO_dataout, nlOiO0i, ~(n10OOi));
        and(wire_nlOl1O_dataout, wire_nlOlii_dataout, ~((~ nlOOOi)));
        and(wire_nlOl1Oi_dataout, nlOiO0l, ~(n10OOi));
        and(wire_nlOl1Ol_dataout, nlOiO0O, ~(n10OOi));
        and(wire_nlOl1OO_dataout, nlOiOii, ~(n10OOi));
        and(wire_nlOli0i_dataout, wire_nlOlO1l_dataout, ~(n10OOi));
        or(wire_nlOli0l_dataout, wire_nlOli0O_dataout, wire_nlOOOii_dataout);
        or(wire_nlOli0O_dataout, nlOiOOl, nl0Oili);
        and(wire_nlOli1i_dataout, wire_nlOliil_dataout, ~(n10OOi));
        and(wire_nlOli1l_dataout, wire_nlOlilO_dataout, ~(n10OOi));
        and(wire_nlOli1O_dataout, wire_nlOllii_dataout, ~(n10OOi));
        and(wire_nlOlii_dataout, wire_nlOlli_dataout, ~(nli01OO));
        or(wire_nlOliii_dataout, nlOiOOO, nl0Oili);
        or(wire_nlOliil_dataout, (wire_n1110i_o | wire_n1111O_dataout), ((n10lOl & wire_n111il_o) & nl0Oiil));
        and(wire_nlOlil_dataout, wire_nlOlll_dataout, ~(nli01OO));
        or(wire_nlOlilO_dataout, wire_nlOliOi_dataout, nl0Oili);
        and(wire_nlOliO_dataout, wire_nlOllO_dataout, ~(nli01OO));
        or(wire_nlOliOi_dataout, nlOl11l, nl0Oill);
        and(wire_nlOlli_dataout, wire_nlOlOi_dataout, ~(nli01lO));
        or(wire_nlOllii_dataout, wire_nlOllil_dataout, nl0Oili);
        assign          wire_nlOllil_dataout = (nl0Oill === 1'b1) ? nlOl11l : nlOl11O;
        or(wire_nlOlliO_dataout, wire_nlOlO1O_dataout, wire_n111li_o);
        and(wire_nlOlll_dataout, nli01ll, ~(nli01lO));
        and(wire_nlOllli_dataout, wire_nlOlO0i_dataout, ~(wire_n111li_o));
        or(wire_nlOllll_dataout, wire_nlOlO0l_dataout, wire_n111li_o);
        and(wire_nlOlllO_dataout, wire_nlOlO0O_dataout, ~(wire_n111li_o));
        and(wire_nlOllO_dataout, wire_nlOlOl_dataout, ~(nli01lO));
        or(wire_nlOllOi_dataout, wire_nlOlOii_dataout, wire_n111li_o);
        and(wire_nlOllOl_dataout, wire_nlOlOil_dataout, ~(wire_n111li_o));
        or(wire_nlOllOO_dataout, wire_nlOlOiO_dataout, wire_n111li_o);
        assign          wire_nlOlO0i_dataout = (nl0OilO === 1'b1) ? n10lii : wire_n1110i_o;
        assign          wire_nlOlO0l_dataout = (nl0OilO === 1'b1) ? n10lil : wire_n1110i_o;
        assign          wire_nlOlO0O_dataout = (nl0OilO === 1'b1) ? n10liO : wire_n1110i_o;
        and(wire_nlOlO1i_dataout, wire_nlOlOli_dataout, ~(wire_n111li_o));
        or(wire_nlOlO1l_dataout, nl0OilO, wire_n111li_o);
        and(wire_nlOlO1O_dataout, n10l0O, nl0OilO);
        and(wire_nlOlOi_dataout, nli01li, ~(nli01ll));
        and(wire_nlOlOii_dataout, n10lli, nl0OilO);
        and(wire_nlOlOil_dataout, n10lll, nl0OilO);
        and(wire_nlOlOiO_dataout, n10llO, nl0OilO);
        and(wire_nlOlOl_dataout, (~ nli01li), ~(nli01ll));
        and(wire_nlOlOli_dataout, n10lOi, nl0OilO);
        and(wire_nlOlOOi_dataout, ((n101li & wire_n111lO_o) | (n101iO & wire_n111Ol_o)), ~(n10OOi));
        and(wire_nlOO00l_dataout, wire_nlOOi0O_dataout, ~(n10OOi));
        and(wire_nlOO00O_dataout, wire_nlOOiii_dataout, ~(n10OOi));
        and(wire_nlOO0ii_dataout, wire_nlOOiil_dataout, ~(n10OOi));
        and(wire_nlOO0il_dataout, wire_nlOOiiO_dataout, ~(n10OOi));
        and(wire_nlOO0iO_dataout, wire_nlOOili_dataout, ~(n10OOi));
        and(wire_nlOO0li_dataout, wire_nlOOill_dataout, ~(n10OOi));
        and(wire_nlOO0ll_dataout, wire_nlOOilO_dataout, ~(n10OOi));
        and(wire_nlOO0lO_dataout, wire_nlOOiOi_dataout, ~(n10OOi));
        and(wire_nlOO0Oi_dataout, wire_nlOOiOl_dataout, ~(n10OOi));
        and(wire_nlOO0Ol_dataout, wire_nlOOiOO_dataout, ~(n10OOi));
        and(wire_nlOO0OO_dataout, wire_nlOOl1i_dataout, ~(n10OOi));
        and(wire_nlOO11O_dataout, wire_nlOOOOl_dataout, ~(n10OOi));
        and(wire_nlOOi0i_dataout, wire_nlOOl0l_dataout, ~(n10OOi));
        and(wire_nlOOi0l_dataout, wire_nlOOl0O_dataout, ~(n10OOi));
        assign          wire_nlOOi0O_dataout = (wire_nlOOOOO_o === 1'b1) ? n10l0O : nlOO11l;
        and(wire_nlOOi1i_dataout, wire_nlOOl1l_dataout, ~(n10OOi));
        and(wire_nlOOi1l_dataout, wire_nlOOl1O_dataout, ~(n10OOi));
        and(wire_nlOOi1O_dataout, wire_nlOOl0i_dataout, ~(n10OOi));
        assign          wire_nlOOiii_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lii : nlOO10i;
        assign          wire_nlOOiil_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lil : nlOO10l;
        assign          wire_nlOOiiO_dataout = (wire_nlOOOOO_o === 1'b1) ? n10liO : nlOO10O;
        assign          wire_nlOOili_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lli : nlOO1ii;
        assign          wire_nlOOill_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lll : nlOO1il;
        assign          wire_nlOOilO_dataout = (wire_nlOOOOO_o === 1'b1) ? n10llO : nlOO1iO;
        assign          wire_nlOOiOi_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lOi : nlOO1li;
        assign          wire_nlOOiOl_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1ll : wire_nlOOlii_dataout;
        assign          wire_nlOOiOO_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1lO : wire_nlOOlil_dataout;
        assign          wire_nlOOl0i_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01i : wire_nlOOllO_dataout;
        assign          wire_nlOOl0l_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01l : wire_nlOOlOi_dataout;
        assign          wire_nlOOl0O_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01O : wire_nlOOlOl_dataout;
        assign          wire_nlOOl1i_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1Oi : wire_nlOOliO_dataout;
        assign          wire_nlOOl1l_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1Ol : wire_nlOOlli_dataout;
        assign          wire_nlOOl1O_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1OO : wire_nlOOlll_dataout;
        assign          wire_nlOOlii_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10l0O : nlOO1ll;
        assign          wire_nlOOlil_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lii : nlOO1lO;
        assign          wire_nlOOliO_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lil : nlOO1Oi;
        assign          wire_nlOOlli_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10liO : nlOO1Ol;
        assign          wire_nlOOlll_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lli : nlOO1OO;
        assign          wire_nlOOllO_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lll : nlOO01i;
        assign          wire_nlOOlOi_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10llO : nlOO01l;
        assign          wire_nlOOlOl_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lOi : nlOO01O;
        and(wire_nlOOO0O_dataout, nl0OliO, n11Oli);
        or(wire_nlOOO1i_dataout, wire_nlOOO1l_dataout, n11OOl);
        and(wire_nlOOO1l_dataout, nlOO00i, ~((wire_n111lO_o | wire_nlOOOOl_dataout)));
        and(wire_nlOOOii_dataout, wire_n110ll_dataout, n101ii);
        and(wire_nlOOOl_dataout, wire_nlOOOO_dataout, nlOOll);
        or(wire_nlOOOO_dataout, wire_n111i_o[0], nlOOOi);
        and(wire_nlOOOOl_dataout, (~ nl0OO1O), n1011i);
        oper_add   n00i1l
        (
        .a({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n0011i}),
        .b({{6{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n00i1l_o));
        defparam
                n00i1l.sgate_representation = 0,
                n00i1l.width_a = 7,
                n00i1l.width_b = 7,
                n00i1l.width_o = 7;
        oper_add   n00ii
        (
        .a({n01OO, n01Ol, n00iO, 1'b1}),
        .b({{2{1'b1}}, 1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n00ii_o));
        defparam
                n00ii.sgate_representation = 0,
                n00ii.width_a = 4,
                n00ii.width_b = 4,
                n00ii.width_o = 4;
        oper_add   n00O0i
        (
        .a({n00lOO, n001li}),
        .b({1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n00O0i_o));
        defparam
                n00O0i.sgate_representation = 0,
                n00O0i.width_a = 2,
                n00O0i.width_b = 2,
                n00O0i.width_o = 2;
        oper_add   n01li
        (
        .a({n011O, n011l, n01ll, 1'b1}),
        .b({{2{1'b1}}, 1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n01li_o));
        defparam
                n01li.sgate_representation = 0,
                n01li.width_a = 4,
                n01li.width_b = 4,
                n01li.width_o = 4;
        oper_add   n0i0ii
        (
        .a({n0i01l, n0i1OO, n0i1Ol, n0i1Oi}),
        .b({{3{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n0i0ii_o));
        defparam
                n0i0ii.sgate_representation = 0,
                n0i0ii.width_a = 4,
                n0i0ii.width_b = 4,
                n0i0ii.width_o = 4;
        oper_add   n0il1i
        (
        .a({n0iill, n0iiiO, n0iiil, n0ii0O}),
        .b({{3{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n0il1i_o));
        defparam
                n0il1i.sgate_representation = 0,
                n0il1i.width_a = 4,
                n0il1i.width_b = 4,
                n0il1i.width_o = 4;
        oper_add   n0ilOl
        (
        .a({n0iOlO, n0iOll, n0iOli, n0iOil, 1'b1}),
        .b({(~ n0ii0i), (~ n0ii1O), (~ n0ii1l), (~ n0i0lO), 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n0ilOl_o));
        defparam
                n0ilOl.sgate_representation = 0,
                n0ilOl.width_a = 5,
                n0ilOl.width_b = 5,
                n0ilOl.width_o = 5;
        oper_add   n0iO0l
        (
        .a({n0i1ll, n0i1li, n0i1iO, n0i10i, 1'b1}),
        .b({(~ n0l1Oi), (~ n0l1lO), (~ n0l1ll), (~ n0l1iO), 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n0iO0l_o));
        defparam
                n0iO0l.sgate_representation = 0,
                n0iO0l.width_a = 5,
                n0iO0l.width_b = 5,
                n0iO0l.width_o = 5;
        oper_add   n100O
        (
        .a({n11OO, n10ii, 1'b1}),
        .b({1'b1, 1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n100O_o));
        defparam
                n100O.sgate_representation = 0,
                n100O.width_a = 3,
                n100O.width_b = 3,
                n100O.width_o = 3;
        oper_add   n111i
        (
        .a({nlOOOi}),
        .b({1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n111i_o));
        defparam
                n111i.sgate_representation = 0,
                n111i.width_a = 1,
                n111i.width_b = 1,
                n111i.width_o = 1;
        oper_add   n1l0i
        (
        .a({n1iOO, n1ill, 1'b1}),
        .b({1'b1, 1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n1l0i_o));
        defparam
                n1l0i.sgate_representation = 0,
                n1l0i.width_a = 3,
                n1l0i.width_b = 3,
                n1l0i.width_o = 3;
        oper_add   n1OiO
        (
        .a({n1O1O, n1O1l, n1O1i, n1llO, 1'b1}),
        .b({{3{1'b1}}, 1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_n1OiO_o));
        defparam
                n1OiO.sgate_representation = 0,
                n1OiO.width_a = 5,
                n1OiO.width_b = 5,
                n1OiO.width_o = 5;
        oper_add   ni01lO
        (
        .a({ni01ii, ni010l, ni010i, ni011l}),
        .b({{3{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_ni01lO_o));
        defparam
                ni01lO.sgate_representation = 0,
                ni01lO.width_a = 4,
                ni01lO.width_b = 4,
                ni01lO.width_o = 4;
        oper_add   ni0i0l
        (
        .a({ni00OO, ni00Oi, ni00lO, ni00ll}),
        .b({{3{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_ni0i0l_o));
        defparam
                ni0i0l.sgate_representation = 0,
                ni0i0l.width_a = 4,
                ni0i0l.width_b = 4,
                ni0i0l.width_o = 4;
        oper_add   ni0l1O
        (
        .a({ni0lOO, ni0lOl, ni0lOi, ni0lll, 1'b1}),
        .b({(~ ni00iO), (~ ni00il), (~ ni00ii), (~ ni001l), 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_ni0l1O_o));
        defparam
                ni0l1O.sgate_representation = 0,
                ni0l1O.width_a = 5,
                ni0l1O.width_b = 5,
                ni0l1O.width_o = 5;
        oper_add   ni0lil
        (
        .a({ni1OOO, ni1OOl, ni1OOi, ni1Oil, 1'b1}),
        .b({(~ nii11l), (~ nii11i), (~ ni0OOO), (~ ni0OOi), 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_ni0lil_o));
        defparam
                ni0lil.sgate_representation = 0,
                ni0lil.width_a = 5,
                ni0lil.width_b = 5,
                ni0lil.width_o = 5;
        oper_add   niiO0i
        (
        .a({niiill, niiili, niiiiO, niiiil, niiiii, niii0O, niii1l}),
        .b({{6{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_niiO0i_o));
        defparam
                niiO0i.sgate_representation = 0,
                niiO0i.width_a = 7,
                niiO0i.width_b = 7,
                niiO0i.width_o = 7;
        oper_add   nliiOii
        (
        .a({nliilll, nliilli, nliiliO, nliilil, nliilii, nliil1i}),
        .b({{5{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nliiOii_o));
        defparam
                nliiOii.sgate_representation = 0,
                nliiOii.width_a = 6,
                nliiOii.width_b = 6,
                nliiOii.width_o = 6;
        oper_add   nliiOll
        (
        .a({nliilOl, nliilOi, nliillO}),
        .b({{2{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nliiOll_o));
        defparam
                nliiOll.sgate_representation = 0,
                nliiOll.width_a = 3,
                nliiOll.width_b = 3,
                nliiOll.width_o = 3;
        oper_add   nlil0li
        (
        .a({nlil1Ol, nlil1Oi, nlil1lO, nlil1ll, nlil1li, nlil10i}),
        .b({{5{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nlil0li_o));
        defparam
                nlil0li.sgate_representation = 0,
                nlil0li.width_a = 6,
                nlil0li.width_b = 6,
                nlil0li.width_o = 6;
        oper_add   nlil0Ol
        (
        .a({nlil01l, nlil01i, nlil1OO}),
        .b({{2{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nlil0Ol_o));
        defparam
                nlil0Ol.sgate_representation = 0,
                nlil0Ol.width_a = 3,
                nlil0Ol.width_b = 3,
                nlil0Ol.width_o = 3;
        oper_add   nll00OO
        (
        .a({nll001i, nll01OO, nll01lO}),
        .b({{2{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nll00OO_o));
        defparam
                nll00OO.sgate_representation = 0,
                nll00OO.width_a = 3,
                nll00OO.width_b = 3,
                nll00OO.width_o = 3;
        oper_add   nll010i
        (
        .a({nll11Ol, nll11Oi, nll11lO, nll11ll, nll11li, nll11iO, nll11il, nll11ii, nll110O, nll110l, nll110i, nll111O, nll111l, nll111i, nliOOOO, nliOOOl, nliOOOi, nliOOlO, nliOOll, nliOOli, nliOO0l}),
        .b({{20{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nll010i_o));
        defparam
                nll010i.sgate_representation = 0,
                nll010i.width_a = 21,
                nll010i.width_b = 21,
                nll010i.width_o = 21;
        oper_add   nllO0O
        (
        .a({nlllll, nlllli, nllliO, nlllil, nlllii, nlll0O, nlll0l, nlll0i}),
        .b({{7{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nllO0O_o));
        defparam
                nllO0O.sgate_representation = 0,
                nllO0O.width_a = 8,
                nllO0O.width_b = 8,
                nllO0O.width_o = 8;
        oper_add   nllO10l
        (
        .a({nlliOiO, nlliOil, nlliOii, nlliO0O, nlliO0l, nlliO0i, nlliO1O, nlliO1l, nlliO1i, nllilOO, nllilOl, nllilOi, nllillO, nllilll, nllilli, nlliliO, nllilil, nllilii, nllil0O, nllil0l, nllil1i}),
        .b({{20{1'b0}}, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nllO10l_o));
        defparam
                nllO10l.sgate_representation = 0,
                nllO10l.width_a = 21,
                nllO10l.width_b = 21,
                nllO10l.width_o = 21;
        oper_add   nllOl1O
        (
        .a({nllOi1l, nllO1Ol}),
        .b({1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nllOl1O_o));
        defparam
                nllOl1O.sgate_representation = 0,
                nllOl1O.width_a = 2,
                nllOl1O.width_b = 2,
                nllOl1O.width_o = 2;
        oper_add   nllOlOi
        (
        .a({nllOi0i, nllOi1O}),
        .b({1'b0, 1'b1}),
        .cin(1'b0),
        .cout(),
        .o(wire_nllOlOi_o));
        defparam
                nllOlOi.sgate_representation = 0,
                nllOlOi.width_a = 2,
                nllOlOi.width_b = 2,
                nllOlOi.width_o = 2;
        oper_decoder   n010Oi
        (
        .i({n010li}),
        .o(wire_n010Oi_o));
        defparam
                n010Oi.width_i = 1,
                n010Oi.width_o = 2;
        oper_decoder   n0lilO
        (
        .i({n0lili}),
        .o(wire_n0lilO_o));
        defparam
                n0lilO.width_i = 1,
                n0lilO.width_o = 2;
        oper_decoder   niO0lO
        (
        .i({niO0il}),
        .o(wire_niO0lO_o));
        defparam
                niO0lO.width_i = 1,
                niO0lO.width_o = 2;
        oper_decoder   niOi0O
        (
        .i({niOiiO}),
        .o(wire_niOi0O_o));
        defparam
                niOi0O.width_i = 1,
                niOi0O.width_o = 2;
        oper_less_than   n00i1O
        (
        .a({{3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1}),
        .b({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n0011i}),
        .cin(1'b1),
        .o(wire_n00i1O_o));
        defparam
                n00i1O.sgate_representation = 0,
                n00i1O.width_a = 7,
                n00i1O.width_b = 7;
        oper_less_than   n0i0il
        (
        .a({n0i01l, n0i1OO, n0i1Ol, n0i1Oi}),
        .b({4{1'b1}}),
        .cin(1'b0),
        .o(wire_n0i0il_o));
        defparam
                n0i0il.sgate_representation = 0,
                n0i0il.width_a = 4,
                n0i0il.width_b = 4;
        oper_less_than   n0il1l
        (
        .a({n0iill, n0iiiO, n0iiil, n0ii0O}),
        .b({4{1'b1}}),
        .cin(1'b0),
        .o(wire_n0il1l_o));
        defparam
                n0il1l.sgate_representation = 0,
                n0il1l.width_a = 4,
                n0il1l.width_b = 4;
        oper_less_than   n0iOiO
        (
        .a({wire_n0ilOl_o[4:1]}),
        .b({1'b0, n0O0li, n0O0iO, 1'b0}),
        .cin(1'b0),
        .o(wire_n0iOiO_o));
        defparam
                n0iOiO.sgate_representation = 0,
                n0iOiO.width_a = 4,
                n0iOiO.width_b = 4;
        oper_less_than   n0l1li
        (
        .a({(~ n0O0ll), 1'b0, {2{1'b1}}}),
        .b({n0iO1l, n0iO1i, n0ilOO, n0ilOi}),
        .cin(1'b1),
        .o(wire_n0l1li_o));
        defparam
                n0l1li.sgate_representation = 0,
                n0l1li.width_a = 4,
                n0l1li.width_b = 4;
        oper_less_than   ni01Oi
        (
        .a({ni01ii, ni010l, ni010i, ni011l}),
        .b({4{1'b1}}),
        .cin(1'b0),
        .o(wire_ni01Oi_o));
        defparam
                ni01Oi.sgate_representation = 0,
                ni01Oi.width_a = 4,
                ni01Oi.width_b = 4;
        oper_less_than   ni0i0O
        (
        .a({ni00OO, ni00Oi, ni00lO, ni00ll}),
        .b({4{1'b1}}),
        .cin(1'b0),
        .o(wire_ni0i0O_o));
        defparam
                ni0i0O.sgate_representation = 0,
                ni0i0O.width_a = 4,
                ni0i0O.width_b = 4;
        oper_less_than   ni0llO
        (
        .a({wire_ni0l1O_o[4:1]}),
        .b({{2{1'b0}}, {2{1'b1}}}),
        .cin(1'b0),
        .o(wire_ni0llO_o));
        defparam
                ni0llO.sgate_representation = 0,
                ni0llO.width_a = 4,
                ni0llO.width_b = 4;
        oper_less_than   ni0OOl
        (
        .a({1'b1, 1'b0, {2{1'b1}}}),
        .b({ni0l0O, ni0l0l, ni0l0i, ni0l1l}),
        .cin(1'b1),
        .o(wire_ni0OOl_o));
        defparam
                ni0OOl.sgate_representation = 0,
                ni0OOl.width_a = 4,
                ni0OOl.width_b = 4;
        oper_less_than   niiO0l
        (
        .a({{3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1}),
        .b({niiill, niiili, niiiiO, niiiil, niiiii, niii0O, niii1l}),
        .cin(1'b1),
        .o(wire_niiO0l_o));
        defparam
                niiO0l.sgate_representation = 0,
                niiO0l.width_a = 7,
                niiO0l.width_b = 7;
        oper_less_than   nlll1O
        (
        .a({{5{1'b0}}, 1'b1, {2{1'b0}}}),
        .b({nlllll, nlllli, nllliO, nlllil, nlllii, nlll0O, nlll0l, nlll0i}),
        .cin(1'b0),
        .o(wire_nlll1O_o));
        defparam
                nlll1O.sgate_representation = 0,
                nlll1O.width_a = 8,
                nlll1O.width_b = 8;
        oper_mux   nl100i
        (
        .data({{11{1'b0}}, nl00Oi, nl0lil, nl0i0i, 1'b0, nl0O1l, {9{1'b0}}, nli10l, nl1i0l, {5{1'b0}}}),
        .o(wire_nl100i_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl100i.width_data = 32,
                nl100i.width_sel = 5;
        oper_mux   nl100l
        (
        .data({{11{1'b0}}, nl00Ol, nl0liO, nl0i0O, 1'b0, nl0O1O, {10{1'b0}}, nl1i0O, {3{1'b0}}, nlil0i, 1'b0}),
        .o(wire_nl100l_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl100l.width_data = 32,
                nl100l.width_sel = 5;
        oper_mux   nl100O
        (
        .data({{11{1'b0}}, nl00OO, nl0lll, nl0iii, 1'b0, nl0O0i, {10{1'b0}}, nl1iii, {3{1'b0}}, 1'b1, 1'b0}),
        .o(wire_nl100O_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl100O.width_data = 32,
                nl100O.width_sel = 5;
        oper_mux   nl101O
        (
        .data({{9{1'b0}}, nl010l, nl00ii, nl00ll, nl0lii, {2{1'b0}}, nl0lOl, {9{1'b0}}, nli11O, nl111i, {3{1'b0}}, 1'b1, 1'b0}),
        .o(wire_nl101O_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl101O.width_data = 32,
                nl101O.width_sel = 5;
        oper_mux   nl10ii
        (
        .data({{11{1'b0}}, nl0i1i, nl0lOi, nl0iil, 1'b0, nl0O0l, {10{1'b0}}, nl1iil, {5{1'b0}}}),
        .o(wire_nl10ii_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10ii.width_data = 32,
                nl10ii.width_sel = 5;
        oper_mux   nl10il
        (
        .data({{11{1'b0}}, nl0i1O, 1'b0, nl0iiO, 1'b0, nl0O0O, {10{1'b0}}, nl1iiO, nlii0i, {2{1'b0}}, nlil0O, nliOiO}),
        .o(wire_nl10il_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10il.width_data = 32,
                nl10il.width_sel = 5;
        oper_mux   nl10iO
        (
        .data({{13{1'b0}}, nl0ili, 1'b0, nl0Oii, {10{1'b0}}, nl1ili, nliill, {3{1'b0}}, 1'b1}),
        .o(wire_nl10iO_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10iO.width_data = 32,
                nl10iO.width_sel = 5;
        oper_mux   nl10li
        (
        .data({{13{1'b0}}, nl0ill, 1'b0, nl0Oil, {10{1'b0}}, nl1ill, nliilO, {2{1'b0}}, 1'b1, 1'b0}),
        .o(wire_nl10li_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10li.width_data = 32,
                nl10li.width_sel = 5;
        oper_mux   nl10ll
        (
        .data({{13{1'b0}}, nl0ilO, 1'b0, nl0OiO, {10{1'b0}}, nl1ilO, nliiOl, {3{1'b0}}, 1'b1}),
        .o(wire_nl10ll_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10ll.width_data = 32,
                nl10ll.width_sel = 5;
        oper_mux   nl10lO
        (
        .data({{13{1'b0}}, nl0iOi, 1'b0, nl0Oli, {10{1'b0}}, nl1iOi, {4{1'b0}}, nll11i}),
        .o(wire_nl10lO_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10lO.width_data = 32,
                nl10lO.width_sel = 5;
        oper_mux   nl10Oi
        (
        .data({{13{1'b0}}, nl0iOl, 1'b1, nl0Oll, {10{1'b0}}, nl1iOl, {4{1'b0}}, nll11l}),
        .o(wire_nl10Oi_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10Oi.width_data = 32,
                nl10Oi.width_sel = 5;
        oper_mux   nl10Ol
        (
        .data({{13{1'b0}}, nl0iOO, 1'b1, nl0OlO, {10{1'b0}}, nl1iOO, {4{1'b0}}, nll11O}),
        .o(wire_nl10Ol_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10Ol.width_data = 32,
                nl10Ol.width_sel = 5;
        oper_mux   nl10OO
        (
        .data({{13{1'b0}}, nl0l1l, 1'b0, nl0OOi, {10{1'b0}}, nl1l1i, nliiOO, {3{1'b0}}, nll10l}),
        .o(wire_nl10OO_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl10OO.width_data = 32,
                nl10OO.width_sel = 5;
        oper_mux   nl1i1i
        (
        .data({{13{1'b0}}, nl0l1O, 1'b0, nl0OOl, {10{1'b0}}, nl1l1l, nlil1l, {4{1'b0}}}),
        .o(wire_nl1i1i_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl1i1i.width_data = 32,
                nl1i1i.width_sel = 5;
        oper_mux   nl1i1l
        (
        .data({{13{1'b0}}, nl0l0i, 1'b0, nl0OOO, {10{1'b0}}, nl1l1O, nlil1O, {3{1'b0}}, nll1ii}),
        .o(wire_nl1i1l_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl1i1l.width_data = 32,
                nl1i1l.width_sel = 5;
        oper_mux   nl1i1O
        (
        .data({{13{1'b0}}, nl0l0O, 1'b0, nli11l, {10{1'b0}}, nl1l0l, {4{1'b0}}, nll1il}),
        .o(wire_nl1i1O_o),
        .sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
        defparam
                nl1i1O.width_data = 32,
                nl1i1O.width_sel = 5;
        oper_selector   n00ill
        (
        .data({wire_n00lii_dataout, 1'b0, wire_n00l1O_dataout}),
        .o(wire_n00ill_o),
        .sel({n00Oii, (n00O0O | n00O1i), n00O0l}));
        defparam
                n00ill.width_data = 3,
                n00ill.width_sel = 3;
        oper_selector   n00iOi
        (
        .data({1'b0, 1'b1, wire_n00l0i_dataout}),
        .o(wire_n00iOi_o),
        .sel({(n00Oii | n00O0O), n00O1i, n00O0l}));
        defparam
                n00iOi.width_data = 3,
                n00iOi.width_sel = 3;
        oper_selector   n00iOO
        (
        .data({wire_n00lil_dataout, (~ nli10il), 1'b0}),
        .o(wire_n00iOO_o),
        .sel({n00Oii, n00O0O, (n00O0l | n00O1i)}));
        defparam
                n00iOO.width_data = 3,
                n00iOO.width_sel = 3;
        oper_selector   n00l1l
        (
        .data({wire_n00liO_dataout, nli10il, 1'b0, nli10ii}),
        .o(wire_n00l1l_o),
        .sel({n00Oii, n00O0O, n00O1i, n00O0l}));
        defparam
                n00l1l.width_data = 4,
                n00l1l.width_sel = 4;
        oper_selector   n1101i
        (
        .data({(~ nl0OO1l), 1'b0, wire_n11ilO_dataout, 1'b1}),
        .o(wire_n1101i_o),
        .sel({n101ll, nl0Olil, n11OOl, n11OOi}));
        defparam
                n1101i.width_data = 4,
                n1101i.width_sel = 4;
        oper_selector   n1110i
        (
        .data({1'b0, wire_n11l1O_dataout, (~ nl0OO1l)}),
        .o(wire_n1110i_o),
        .sel({nl0Ol1O, n101li, n1010i}));
        defparam
                n1110i.width_data = 3,
                n1110i.width_sel = 3;
        oper_selector   n1111i
        (
        .data({1'b0, nl0OOOi, 1'b0, nl0OOOi}),
        .o(wire_n1111i_o),
        .sel({nl0Ol1l, n101iO, n1011l, n1011O}));
        defparam
                n1111i.width_data = 4,
                n1111i.width_sel = 4;
        oper_selector   n111il
        (
        .data({1'b0, 1'b1, wire_n110Ol_dataout, (~ nl0OliO), wire_n110li_dataout, (~ nl0OliO), wire_n1100i_dataout, {2{(~ nl0OliO)}}}),
        .o(wire_n111il_o),
        .sel({nl0Ol0i, n101il, n101ii, n1010O, n1010l, n11OlO, n11Oll, n11Oli, n11OiO}));
        defparam
                n111il.width_data = 9,
                n111il.width_sel = 9;
        oper_selector   n111li
        (
        .data({1'b0, nl0OOiO, wire_n1100l_dataout}),
        .o(wire_n111li_o),
        .sel({nl0Ol0l, n101li, n11Oll}));
        defparam
                n111li.width_data = 3,
                n111li.width_sel = 3;
        oper_selector   n111lO
        (
        .data({nl0OO1l, 1'b0, wire_n11l0i_dataout, wire_n11iOO_dataout, {2{nl0OO1l}}, nl0OO0l, {2{nl0OO1l}}}),
        .o(wire_n111lO_o),
        .sel({n101ll, nl0Ol0O, n101li, n11OOO, n1010i, n11OOl, n1010l, n11Oll, nlOOlOO}));
        defparam
                n111lO.width_data = 9,
                n111lO.width_sel = 9;
        oper_selector   n111Ol
        (
        .data({1'b0, wire_n11O0l_dataout, 1'b0, (~ nl0OOOi)}),
        .o(wire_n111Ol_o),
        .sel({nl0Olii, n101iO, n101li, n1011O}));
        defparam
                n111Ol.width_data = 4,
                n111Ol.width_sel = 4;
        oper_selector   n1Oi0O
        (
        .data({nli11Oi, 1'b0, nli11iO}),
        .o(wire_n1Oi0O_o),
        .sel({n011il, nli110i, n1i0li}));
        defparam
                n1Oi0O.width_data = 3,
                n1Oi0O.width_sel = 3;
        oper_selector   n1OiiO
        (
        .data({wire_n1Olll_dataout, 1'b0, {2{wire_n1Ol1O_dataout}}}),
        .o(wire_n1OiiO_o),
        .sel({n011il, nli110O, n1OOlO, n1i0li}));
        defparam
                n1OiiO.width_data = 4,
                n1OiiO.width_sel = 4;
        oper_selector   n1Oill
        (
        .data({1'b0, 1'b1, (~ nli11li)}),
        .o(wire_n1Oill_o),
        .sel({nli110l, (n011ii | n0111l), n0110O}));
        defparam
                n1Oill.width_data = 3,
                n1Oill.width_sel = 3;
        oper_selector   n1OiOl
        (
        .data({wire_n1OllO_dataout, 1'b0, {2{wire_n1Ol0i_dataout}}}),
        .o(wire_n1OiOl_o),
        .sel({n011il, nli110O, n1OOlO, n1i0li}));
        defparam
                n1OiOl.width_data = 4,
                n1OiOl.width_sel = 4;
        oper_selector   n1Ol1i
        (
        .data({wire_n1OlOi_dataout, 1'b0, (~ n1i1il), 1'b1, {2{wire_n1Ol0l_dataout}}}),
        .o(wire_n1Ol1i_o),
        .sel({n011il, nli11ii, n0110i, n0111i, n1OOlO, n1i0li}));
        defparam
                n1Ol1i.width_data = 6,
                n1Ol1i.width_sel = 6;
        oper_selector   ni101l
        (
        .data({wire_ni10iO_dataout, 1'b0, nliil0l}),
        .o(wire_ni101l_o),
        .sel({ni1i1l, nli1i1l, n0OOli}));
        defparam
                ni101l.width_data = 3,
                ni101l.width_sel = 3;
        oper_selector   ni11lO
        (
        .data({1'b0, nli1i0i, nli1i1O, (~ nliil0l)}),
        .o(wire_ni11lO_o),
        .sel({ni1i1l, ni10OO, ni10Ol, n0OOli}));
        defparam
                ni11lO.width_data = 4,
                ni11lO.width_sel = 4;
        oper_selector   ni11Oi
        (
        .data({wire_ni10il_dataout, 1'b0, (~ nli1i1O)}),
        .o(wire_ni11Oi_o),
        .sel({ni1i1l, nli1i1i, ni10Ol}));
        defparam
                ni11Oi.width_data = 3,
                ni11Oi.width_sel = 3;
        oper_selector   ni11OO
        (
        .data({nli1i0O, (~ nli1i0i), 1'b0}),
        .o(wire_ni11OO_o),
        .sel({ni1i1l, ni10OO, (ni10Ol | n0OOli)}));
        defparam
                ni11OO.width_data = 3,
                ni11OO.width_sel = 3;
        oper_selector   niiOOi
        (
        .data({wire_nil1iO_dataout, 1'b0, wire_nil10l_dataout}),
        .o(wire_niiOOi_o),
        .sel({nil01i, (nil1OO | niiilO), nil1Ol}));
        defparam
                niiOOi.width_data = 3,
                niiOOi.width_sel = 3;
        oper_selector   niiOOO
        (
        .data({1'b0, 1'b1, wire_nil10O_dataout}),
        .o(wire_niiOOO_o),
        .sel({(nil01i | nil1OO), niiilO, nil1Ol}));
        defparam
                niiOOO.width_data = 3,
                niiOOO.width_sel = 3;
        oper_selector   nil10i
        (
        .data({wire_nil1li_dataout, nli1iOl, 1'b0, nli1iOi}),
        .o(wire_nil10i_o),
        .sel({nil01i, nil1OO, niiilO, nil1Ol}));
        defparam
                nil10i.width_data = 4,
                nil10i.width_sel = 4;
        oper_selector   nil11l
        (
        .data({nli1l1i, (~ nli1iOl), 1'b0}),
        .o(wire_nil11l_o),
        .sel({nil01i, nil1OO, (nil1Ol | niiilO)}));
        defparam
                nil11l.width_data = 3,
                nil11l.width_sel = 3;
        oper_selector   nlO0lli
        (
        .data({1'b0, (~ wire_nlili0O_dout)}),
        .o(wire_nlO0lli_o),
        .sel({nl0O0iO, (~ nl0O0iO)}));
        defparam
                nlO0lli.width_data = 2,
                nlO0lli.width_sel = 2;
        oper_selector   nlO0llO
        (
        .data({1'b0, nl0Oi1i, (~ nllO1Oi)}),
        .o(wire_nlO0llO_o),
        .sel({nl0O0li, nlOi1lO, nlOi1ll}));
        defparam
                nlO0llO.width_data = 3,
                nlO0llO.width_sel = 3;
        oper_selector   nlO0lOl
        (
        .data({1'b0, nl0Oi1l, wire_nlO0Oll_dataout}),
        .o(wire_nlO0lOl_o),
        .sel({nl0O0ll, nlOi1Oi, nlOi1lO}));
        defparam
                nlO0lOl.width_data = 3,
                nlO0lOl.width_sel = 3;
        oper_selector   nlO0O0l
        (
        .data({1'b0, nll0lll, (~ nl0Oi0O)}),
        .o(wire_nlO0O0l_o),
        .sel({nl0O0Ol, nlOi01i, nlOi1OO}));
        defparam
                nlO0O0l.width_data = 3,
                nlO0O0l.width_sel = 3;
        oper_selector   nlO0O1i
        (
        .data({1'b0, nl0Oi0l, wire_nlO0OOl_dataout}),
        .o(wire_nlO0O1i_o),
        .sel({nl0O0lO, nlOi1Ol, nlOi1Oi}));
        defparam
                nlO0O1i.width_data = 3,
                nlO0O1i.width_sel = 3;
        oper_selector   nlO0O1O
        (
        .data({1'b0, nl0Oi0O, wire_nlOi11O_dataout}),
        .o(wire_nlO0O1O_o),
        .sel({nl0O0Oi, nlOi1OO, nlOi1Ol}));
        defparam
                nlO0O1O.width_data = 3,
                nlO0O1O.width_sel = 3;
        oper_selector   nlO0Oii
        (
        .data({wire_nlili0O_dout, (~ nll0lll), 1'b0}),
        .o(wire_nlO0Oii_o),
        .sel({nlOi01l, nlOi01i, nl0O0OO}));
        defparam
                nlO0Oii.width_data = 3,
                nlO0Oii.width_sel = 3;
        oper_selector   nlO0OiO
        (
        .data({1'b0, wire_nlOi10i_dataout, wire_nlO0OOO_dataout, wire_nlO0OlO_dataout, nllO1Oi, wire_nlili0O_dout}),
        .o(wire_nlO0OiO_o),
        .sel({((nlOi01l | nlOi01i) | nlOi1OO), nlOi1Ol, nlOi1Oi, nlOi1lO, nlOi1ll, nlO101l}));
        defparam
                nlO0OiO.width_data = 6,
                nlO0OiO.width_sel = 6;
        oper_selector   nlOi0i
        (
        .data({wire_nlOl1i_dataout, (~ nli01iO), 1'b0}),
        .o(wire_nlOi0i_o),
        .sel({nlOOll, nlOi1l, (((nlOOli | nlOOiO) | nlOOil) | nlOOii)}));
        defparam
                nlOi0i.width_data = 3,
                nlOi0i.width_sel = 3;
        oper_selector   nlOi0O
        (
        .data({wire_nlOl1l_dataout, 1'b0, (~ nli01il)}),
        .o(wire_nlOi0O_o),
        .sel({nlOOll, (((nlOOli | nlOOiO) | nlOOil) | nlOi1l), nlOOii}));
        defparam
                nlOi0O.width_data = 3,
                nlOi0O.width_sel = 3;
        oper_selector   nlOiil
        (
        .data({wire_nlOl1O_dataout, nli01iO, nli01il, 1'b0}),
        .o(wire_nlOiil_o),
        .sel({nlOOll, nlOi1l, nlOOii, ((nlOOli | nlOOiO) | nlOOil)}));
        defparam
                nlOiil.width_data = 4,
                nlOiil.width_sel = 4;
        oper_selector   nlOili
        (
        .data({wire_nlOl0i_dataout, 1'b0, 1'b1}),
        .o(wire_nlOili_o),
        .sel({nlOOll, (((nlOOli | nlOOil) | nlOOii) | nlOi1l), nlOOiO}));
        defparam
                nlOili.width_data = 3,
                nlOili.width_sel = 3;
        oper_selector   nlOilO
        (
        .data({wire_nlOl0l_dataout, 1'b0, 1'b1}),
        .o(wire_nlOilO_o),
        .sel({nlOOll, (((nlOOli | nlOOiO) | nlOOii) | nlOi1l), nlOOil}));
        defparam
                nlOilO.width_data = 3,
                nlOilO.width_sel = 3;
        oper_selector   nlOOO0i
        (
        .data({1'b0, nl0OliO, (~ nl0OO1l)}),
        .o(wire_nlOOO0i_o),
        .sel({nl0OiOi, n11OiO, nlOOlOO}));
        defparam
                nlOOO0i.width_data = 3,
                nlOOO0i.width_sel = 3;
        oper_selector   nlOOOil
        (
        .data({1'b0, nl0OliO, wire_n1101O_dataout}),
        .o(wire_nlOOOil_o),
        .sel({nl0OiOl, n11OlO, n11Oll}));
        defparam
                nlOOOil.width_data = 3,
                nlOOOil.width_sel = 3;
        oper_selector   nlOOOli
        (
        .data({1'b0, wire_n110lO_dataout, wire_n110iO_dataout}),
        .o(wire_nlOOOli_o),
        .sel({nl0OiOO, n101ii, n1010l}));
        defparam
                nlOOOli.width_data = 3,
                nlOOOli.width_sel = 3;
        oper_selector   nlOOOlO
        (
        .data({1'b0, wire_n11O0i_dataout, wire_n11l1l_dataout, {2{nl0OO1O}}, wire_n11iOl_dataout, wire_n11ill_dataout}),
        .o(wire_nlOOOlO_o),
        .sel({nl0Ol1i, n101iO, n101li, n1011l, n1011i, n11OOO, n11OOl}));
        defparam
                nlOOOlO.width_data = 7,
                nlOOOlO.width_sel = 7;
        oper_selector   nlOOOOO
        (
        .data({(~ nl0OO1O), 1'b0}),
        .o(wire_nlOOOOO_o),
        .sel({n1011l, (~ n1011l)}));
        defparam
                nlOOOOO.width_data = 2,
                nlOOOOO.width_sel = 2;
        assign
                gmii_rx_d = {n0O1li, n0O1iO, n0O1il, n0O1ii, n0O10O, n0O10l, n0O10i, n0O11O},
                gmii_rx_dv = n0O1ll,
                gmii_rx_err = n0O1Oi,
                hd_ena = nl011l,
                led_an = nliOOiO,
                led_char_err = niO0O,
                led_col = niOiiO,
                led_crs = n010ll,
                led_disp_err = niOiO,
                led_link = niO1i,
                mii_col = niOiiO,
                mii_crs = niO0li,
                mii_rx_d = {n0ll1l, n0ll1i, n0liOO, n0liOl},
                mii_rx_dv = n0liOi,
                mii_rx_err = n0llli,
                nl0O00i = (nllOi0i & (~ nllOi1O)),
                nl0O00l = ((~ (nlO101i ^ nlOO01O)) & nl0O00O),
                nl0O00O = ((((((((((((((~ (nlO111i ^ nlOO11l)) & (~ (nlO111l ^ nlOO10i))) & (~ (nlO111O ^ nlOO10l))) & (~ (nlO110i ^ nlOO10O))) & (~ (nlO110l ^ nlOO1ii))) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))),
                nl0O01i = (nllOi1l & (~ nllO1Ol)),
                nl0O01l = (nlO11OO & nl0O01O),
                nl0O01O = ((((((((((((((((~ (nlO111i ^ nlOO11l)) & (~ (nlO111l ^ nlOO10i))) & (~ (nlO111O ^ nlOO10l))) & (~ (nlO110i ^ nlOO10O))) & (~ (nlO110l ^ nlOO1ii))) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))) & (~ (nlO11OO ^ nlOO01l))) & (~ (nlO101i ^ nlOO01O))),
                nl0O0ii = ((((((((((((((((~ nlO101i) & (~ nlO11OO)) & (~ nlO11Ol)) & (~ nlO11Oi)) & (~ nlO11lO)) & (~ nlO11ll)) & (~ nlO11li)) & (~ nlO11iO)) & (~ nlO11il)) & (~ nlO11ii)) & (~ nlO110O)) & (~ nlO110l)) & (~ nlO110i)) & (~ nlO111O)) & (~ nlO111l)) & (~ nlO111i)),
                nl0O0il = (nlOi1OO & nllO1Oi),
                nl0O0iO = (((((nlOi01i | nlOi1OO) | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll),
                nl0O0li = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1Ol) | nlOi1Oi) | nlO101l),
                nl0O0ll = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1Ol) | nlOi1ll) | nlO101l),
                nl0O0lO = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1lO) | nlOi1ll) | nlO101l),
                nl0O0Oi = (((((nlOi01l | nlOi01i) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
                nl0O0Ol = (((((nlOi01l | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
                nl0O0OO = (((((nlOi1OO | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
                nl0O10i = ((nliilOl & (~ nliilOi)) & (~ nliillO)),
                nl0O10l = (((((nlil1Ol & nlil1Oi) & (~ nlil1lO)) & (~ nlil1ll)) & (~ nlil1li)) & nlil10i),
                nl0O10O = ((nlil01l & (~ nlil01i)) & (~ nlil1OO)),
                nl0O11O = (((((nliilll & nliilli) & (~ nliiliO)) & (~ nliilil)) & (~ nliilii)) & nliil1i),
                nl0O1ii = ((((((((((((((((((((~ (nliOOli ^ nl0i0i)) & (~ (nliOOll ^ nl0i0O))) & (~ (nliOOlO ^ nl0iii))) & (~ (nliOOOi ^ nl0iil))) & (~ (nliOOOl ^ nl0iiO))) & (~ (nliOOOO ^ nl0ili))) & (~ (nll111i ^ nl0ill))) & (~ (nll111l ^ nl0ilO))) & (~ (nll111O ^ nl0iOi))) & (~ (nll110i ^ nl0iOl))) & (~ (nll110l ^ nl0iOO))) & (~ (nll110O ^ nl0l1l))) & (~ (nll11ii ^ nl0l1O))) & (~ (nll11il ^ nl0l0i))) & (~ (nll11iO ^ nl0l0O))) & (~ (nll11li ^ nl0lii))) & (~ (nll11ll ^ nl0lil))) & (~ (nll11lO ^ nl0liO))) & (~ (nll11Oi ^ nl0lll))) & (~ (nll11Ol ^ nl0lOi))),
                nl0O1il = ((~ nl0O1iO) & nlOl10i),
                nl0O1iO = ((nll001i & nll01OO) & (~ nll01lO)),
                nl0O1li = ((((((((((((((((((((~ (nllil0l ^ nl0i0i)) & (~ (nllil0O ^ nl0i0O))) & (~ (nllilii ^ nl0iii))) & (~ (nllilil ^ nl0iil))) & (~ (nlliliO ^ nl0iiO))) & (~ (nllilli ^ nl0ili))) & (~ (nllilll ^ nl0ill))) & (~ (nllillO ^ nl0ilO))) & (~ (nllilOi ^ nl0iOi))) & (~ (nllilOl ^ nl0iOl))) & (~ (nllilOO ^ nl0iOO))) & (~ (nlliO1i ^ nl0l1l))) & (~ (nlliO1l ^ nl0l1O))) & (~ (nlliO1O ^ nl0l0i))) & (~ (nlliO0i ^ nl0l0O))) & (~ (nlliO0l ^ nl0lii))) & (~ (nlliO0O ^ nl0lil))) & (~ (nlliOii ^ nl0liO))) & (~ (nlliOil ^ nl0lll))) & (~ (nlliOiO ^ nl0lOi))),
                nl0O1ll = (wire_nlO0O1i_o | (wire_nlO0lOl_o | (wire_nlO0Oii_o | wire_nlO0O1O_o))),
                nl0O1lO = ((nlOi01l | wire_nlO0O1O_o) | nl0O1Oi),
                nl0O1Oi = (nlOi1Oi & wire_nlO0lOl_o),
                nl0O1Ol = ((((((((((((((~ (nlO111i ^ nllOi0l)) & (~ (nlO111l ^ nllOO1i))) & (~ (nlO111O ^ nllOO1l))) & (~ (nlO110i ^ nllOO1O))) & (~ (nlO110l ^ nllOO0i))) & (~ (nlO110O ^ nllOO0l))) & (~ (nlO11ii ^ nllOO0O))) & (~ (nlO11il ^ nllOOii))) & (~ (nlO11iO ^ nllOOil))) & (~ (nlO11li ^ nllOOiO))) & (~ (nlO11ll ^ nllOOli))) & (~ (nlO11lO ^ nllOOll))) & (~ (nlO11Oi ^ nllOOlO))) & (~ (nlO11Ol ^ nllOOOi))),
                nl0O1OO = ((((((((wire_nlO0lli_o ^ nlO101l) | (nlOi1ll ^ wire_nlO0llO_o)) | (nlOi1lO ^ wire_nlO0lOl_o)) | (nlOi1Oi ^ wire_nlO0O1i_o)) | (nlOi1Ol ^ wire_nlO0O1O_o)) | (nlOi1OO ^ wire_nlO0O0l_o)) | (nlOi01i ^ wire_nlO0Oii_o)) | (nlOi01l ^ wire_nlO0OiO_o)),
                nl0Oi0i = (nllOOOO & nllO1Oi),
                nl0Oi0l = (nllO1lO & nlliOli),
                nl0Oi0O = ((~ nllOOOO) & nllO1Oi),
                nl0Oi1i = (nll0lll & nll01il),
                nl0Oi1l = (((~ nllOOOO) | (~ nllO1Oi)) & nll0lll),
                nl0Oi1O = (nllO1lO & (~ nlliOli)),
                nl0Oiii = ((((nll11OO | (~ nliOlOi)) | wire_nliliil_dout) | ((((~ nlOi1lO) & (~ nlOi1ll)) & (~ nlO101l)) & nlOO00i)) | (nlOi01O ^ wire_nlili0O_dout)),
                nl0Oiil = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & n10lil) & n10lii) & (~ n10l0O)),
                nl0OiiO = (n1010O | n1010l),
                nl0Oili = (wire_n111il_o & (n11Oll | (n11OlO | nl0OiiO))),
                nl0Oill = (wire_n111il_o & (nlOOlOO | (n11OiO | (n11Oli | nl0OiiO)))),
                nl0OilO = (wire_n111il_o | wire_n1111O_dataout),
                nl0OiOi = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli),
                nl0OiOl = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11Oli) | n11OiO) | nlOOlOO),
                nl0OiOO = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n1010O) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Ol0i = ((((((((((n101ll | n101li) | n101iO) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOlOO),
                nl0Ol0l = ((((((((((((((((n101ll | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Ol0O = ((((((((((n101iO | n101il) | n101ii) | n1010O) | n1011O) | n1011l) | n1011i) | n11OOi) | n11OlO) | n11Oli) | n11OiO),
                nl0Ol1i = ((((((((((((n101ll | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Ol1l = (((((((((((((((n101ll | n101li) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Ol1O = ((((((((((((((((n101ll | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Olii = (((((((((((((((n101ll | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0Olil = (((((((((((((((n101li | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
                nl0OliO = (n10lOl & nl0Olli),
                nl0Olli = (((((((n10lOi & n10llO) & n10lll) & n10lli) & (~ n10liO)) & n10lil) & n10lii) & n10l0O),
                nl0Olll = (n10OlO & nl0OO0l),
                nl0OllO = ((~ n10OlO) & nl0OlOO),
                nl0OlOi = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & n10lil) & (~ n10lii)) & n10l0O),
                nl0OlOl = (n10OlO & nl0OlOO),
                nl0OlOO = (n10lOl & nl0OlOi),
                nl0OO0i = ((~ nll0i0l) & (~ nl0OO0l)),
                nl0OO0l = (n10lOl & nl0OOil),
                nl0OO0O = (nll0i0l & ((~ n10lOl) & n10l0i)),
                nl0OO1i = ((~ n10OlO) & (~ n10lOl)),
                nl0OO1l = (n10OlO & nl0OO0l),
                nl0OO1O = (n10lOl | n10l0l),
                nl0OOii = (nll0i0l & (n10l0i & ((n10lOl & (~ nl0OOll)) & (~ nl0OOil)))),
                nl0OOil = (((((((n10lOi & (~ n10llO)) & n10lll) & n10lli) & n10liO) & n10lil) & (~ n10lii)) & (~ n10l0O)),
                nl0OOiO = (nll0i0l & nl0OOli),
                nl0OOli = (n10lOl & nl0OOll),
                nl0OOll = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & (~ n10lil)) & n10lii) & n10l0O),
                nl0OOlO = ((~ nll0i0l) & n10l0l),
                nl0OOOi = ((~ n10lOl) & (nl0OOOO | nl0OOOl)),
                nl0OOOl = (((((((n10lOi & (~ n10llO)) & n10lll) & n10lli) & (~ n10liO)) & n10lil) & (~ n10lii)) & n10l0O),
                nl0OOOO = ((((((((~ n10lOi) & n10llO) & (~ n10lll)) & (~ n10lli)) & (~ n10liO)) & (~ n10lil)) & n10lii) & (~ n10l0O)),
                nli000l = ((nli000O | ((~ n11ll) & n10il)) | n11OO),
                nli000O = (nlii00i & (~ n10lO)),
                nli001i = (((((~ address[0]) & address[1]) & address[2]) & address[3]) & (~ address[4])),
                nli001l = (nli01Ol & (~ nlli1i)),
                nli00ii = (nli00il | ((~ n101i) & n1i1l)),
                nli00il = (nlii00i & (~ n1i0O)),
                nli00iO = (nli0iii & n1l1i),
                nli00li = (nli00ll | (((~ nli0iii) | n1iOO) & n1l1i)),
                nli00ll = (nlii00i & (~ n1l0O)),
                nli00lO = (nli0i0i & n1O0i),
                nli00Oi = (nli00Ol | (((~ nli0i0i) | n1O1O) & n1O0i)),
                nli00Ol = (nli0i0l & (~ n1Oll)),
                nli00OO = (nlii00i & (~ n01lO)),
                nli010l = (((((((nlllll & nlllli) & nllliO) & nlllil) & nlllii) & nlll0O) & nlll0l) & (~ nlll0i)),
                nli010O = (nl00ii & wire_nlll1O_o),
                nli011i = (((((~ nlO1Ol) & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & (~ nlO1li)),
                nli01ii = (wire_nlOi0O_o | wire_nlOi0i_o),
                nli01il = (nlliOO | nlliOi),
                nli01iO = (nlliOO | nlli1i),
                nli01li = (nli001l & (~ nlliOi)),
                nli01ll = ((~ read) & write),
                nli01lO = ((nli01Ol & (~ nlliOi)) & nli01Oi),
                nli01Oi = ((((address[0] & (~ address[1])) & address[2]) & (~ address[3])) & (~ address[4])),
                nli01Ol = (read & (~ write)),
                nli01OO = (nli001l & nli001i),
                nli0i0i = (n11Ol & n1lii),
                nli0i0l = (nlii00i | nli0i0O),
                nli0i0O = ((~ n11Ol) & n1OlO),
                nli0i1i = (nli0i1O & (~ n00ll)),
                nli0i1l = (n1i1l | n011O),
                nli0i1O = (nlii00i | nli0i0O),
                nli0iii = ((~ n11lO) & n1iiO),
                nli0iil = (n1O0i | n01OO),
                nli0iiO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & (~ nl1iO)),
                nli0ili = (((~ nl1ii) & nli0l1l) | (nl1ii & nli0l1i)),
                nli0ill = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & (~ nl1li)) & nl1iO),
                nli0ilO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & nl1ll) & nl1li) & nl1iO),
                nli0iOi = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & nl1lO) & (~ nl1ll)) & nl1li) & nl1iO),
                nli0iOl = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & nl1Oi) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & nl1iO),
                nli0iOO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & nl1iO),
                nli0l0O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & (~ nl1li)) & nl1iO),
                nli0l1i = (nl10l & (~ wire_nl0ii_runningdisp[0])),
                nli0l1l = (nl10l & wire_nl0ii_runningdisp[0]),
                nli0l1O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & (~ nl1iO)),
                nli0lOO = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & nl1ll) & nl1li) & nl1iO),
                nli0O0O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                nli0O1i = (((((((nl01l & (~ nl1OO)) & nl1Ol) & nl1Oi) & (~ nl1lO)) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                nli0Oll = (((((((nl01l & (~ nl1OO)) & nl1Ol) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                nli100i = ((~ n00Oll) & (~ n00Oli)),
                nli100l = ((~ n00Oll) & n00Oli),
                nli100O = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & n0011i),
                nli101i = (nlOl11i | n01l0l),
                nli101l = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & (~ n0011i)),
                nli101O = (((((((~ n001iO) & (~ n001il)) & (~ n001ii)) & n0010O) & (~ n0010l)) & (~ n0010i)) & (~ n0011i)),
                nli10ii = (n00Oil | nli10ll),
                nli10il = (n00Oil | (~ nli10ll)),
                nli10iO = ((~ n00Oil) & (~ n0l11l)),
                nli10li = ((~ n00Oil) & (nli10ll & (~ n0l11l))),
                nli10ll = (n00Oll & (~ n00Oli)),
                nli10lO = ((~ n00lOO) & n001li),
                nli10Oi = (nlil1il & n0li0O),
                nli10Ol = (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])),
                nli10OO = (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])),
                nli110i = (((((((((((((n011ii | n0110O) | n0110l) | n0110i) | n0111O) | n0111l) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOlO) | n1OOll) | n1OOli) | n1OOiO),
                nli110l = ((((((((((((n011il | n0110l) | n0110i) | n0111O) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOlO) | n1OOll) | n1OOli) | n1OOiO) | n1i0li),
                nli110O = ((((((((((((n011ii | n0110O) | n0110l) | n0110i) | n0111O) | n0111l) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOll) | n1OOli) | n1OOiO),
                nli111i = (wire_n1Ol1i_o & n1i1il),
                nli111l = ((~ n011il) & wire_n1Ol1i_o),
                nli111O = (wire_n1Oill_o & niii0l),
                nli11ii = ((((((((((n011ii | n0110O) | n0110l) | n0111O) | n0111l) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOll) | n1OOli) | n1OOiO),
                nli11il = (nli11ll & wire_n1i11O_dout),
                nli11iO = ((~ wire_n1i10i_dout) & (~ wire_n1i11O_dout)),
                nli11li = ((~ nii00l) | (~ wire_n1i11O_dout)),
                nli11ll = ((niii0l & nii00l) & n1i1il),
                nli11lO = ((((~ niii0l) & nii00l) & (~ n1i1il)) & wire_n1i11O_dout),
                nli11Oi = (((wire_n1i1ii_dout & (~ wire_n1i10i_dout)) & (~ n1i1il)) & (~ wire_n1i11O_dout)),
                nli11Ol = (nlOl11i & nlOiOOi),
                nli11OO = ((~ nli101i) & n0l11l),
                nli1i0i = (nliil0l & (niO1ii & (~ ni1lOl))),
                nli1i0l = (nliil0l & ((~ niO1ii) & ni1lOl)),
                nli1i0O = (nliil0l & (niO1ii & ni1lOl)),
                nli1i1i = (ni10OO | n0OOli),
                nli1i1l = (ni10OO | ni10Ol),
                nli1i1O = (nliil0l & ((~ niO1ii) & (~ ni1lOl))),
                nli1iii = (nliil0l & nli1l1O),
                nli1iil = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & (~ niii1l)),
                nli1iiO = (((((((~ niiill) & (~ niiili)) & (~ niiiiO)) & niiiil) & (~ niiiii)) & (~ niii0O)) & (~ niii1l)),
                nli1ili = ((~ nil00l) & (~ nil00i)),
                nli1ill = ((~ nil00l) & nil00i),
                nli1ilO = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & niii1l),
                nli1iOi = (nil01l | nli1l1l),
                nli1iOl = (nil01l | (~ nli1l1l)),
                nli1iOO = ((~ ni0lii) & (~ nil01l)),
                nli1l0i = (niO00i & (~ niO01O)),
                nli1l0l = (((((~ nl1Oll) & (~ nl1Oli)) & nl1OiO) & (~ nl1Oil)) & nl1l0O),
                nli1l0O = (nll00i & (nlii1O & (nl00Oi & nl00ll))),
                nli1l1i = ((~ nil01l) & ((~ ni0lii) & nli1l1l)),
                nli1l1l = (nil00l & (~ nil00i)),
                nli1l1O = (nliil0l & (niO1ii & (~ ni0O0O))),
                nli1lii = ((~ nl00Oi) & nl00ll),
                nli1lil = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & nlO1li),
                nli1liO = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & nlO1ll) & (~ nlO1li)),
                nli1lli = (nli1lll & nlO1OO),
                nli1lll = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & (~ nlO1li)),
                nli1lOl = (nli1lOO & nlO1OO),
                nli1lOO = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & nlO1ll) & nlO1li),
                nli1O0i = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & (~ nlO1li)),
                nli1O0l = (((((~ nlO1Ol) & (~ nlO1Oi)) & nlO1lO) & nlO1ll) & (~ nlO1li)),
                nli1O1i = (nli1O1l & nlO1OO),
                nli1O1l = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & nlO1ll) & (~ nlO1li)),
                nli1O1O = (nli1O0i & nlO1OO),
                nli1OiO = (nli1Oli & nlO1OO),
                nli1Oli = (((((~ nlO1Ol) & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & (~ nlO1li)),
                nli1Oll = (((((~ nlO1Ol) & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & nlO1li),
                nli1OOO = (nli011i & nlO1OO),
                nlii00i = ((nlili | nli0O) | (~ (nlii00l14 ^ nlii00l13))),
                nlii0iO = 1'b0,
                nlii0li = (reset_tx_clk | nliiiiO),
                nlii0ll = (reset_rx_clk | nliii0O),
                nlii0lO = 1'b1,
                nlii11i = (((((((nl01l & (~ nl1OO)) & (~ nl1Ol)) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                nlii1il = (((((((nl01l & nl1OO) & nl1Ol) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                nlii1Oi = ((((((((~ nl01l) & (~ nl1OO)) & (~ nl1Ol)) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
                pcs_pwrdn_out = nliO0O,
                readdata = {nlO1il, nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O, nlO11l, nlO11i, nllOOO, nllOOl, nllOOi, nllOlO, nllOll, nllOli, nllOiO, nllOil},
                reconfig_fromgxb = {{4{1'b0}}, wire_nl0il_dprioout},
                rx_clk = wire_nl00l_clkout,
                rx_clkena = nlil1il,
                rx_recovclkout = wire_nl00O_clockout,
                set_10 = (((~ nl010i) & (~ nl011O)) & (nliii1l2 ^ nliii1l1)),
                set_100 = ((~ nl010i) & nl011O),
                set_1000 = ((nl010i & (~ nl011O)) & (nlii0OO4 ^ nlii0OO3)),
                tx_clk = wire_nl00l_clkout,
                tx_clkena = nliil0l,
                txp = wire_nl00i_dataout,
                waitrequest = nllllO;
endmodule //sgmii
//synopsys translate_on
//VALID FILE
Line No.	Rev	Author	Line
1	9	jefflieu	`//IP Functional Simulation Model`
2	20	jefflieu	`//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:10:19:19:54:28:SJ cbx_simgen 2012:10:19:19:52:08:SJ VERSION_END`
3	9	jefflieu	`// synthesis VERILOG_INPUT_VERSION VERILOG_2001`
4			`// altera message_off 10463`
5
6
7
8	20	jefflieu	`// Copyright (C) 1991-2012 Altera Corporation`
9	9	jefflieu	`// Your use of Altera Corporation's design tools, logic functions`
10			`// and other software and tools, and its AMPP partner logic`
11			`// functions, and any output files from any of the foregoing`
12			`// (including device programming or simulation files), and any`
13			`// associated documentation or information are expressly subject`
14			`// to the terms and conditions of the Altera Program License`
15			`// Subscription Agreement, Altera MegaCore Function License`
16			`// Agreement, or other applicable license agreement, including,`
17			`// without limitation, that your use is for the sole purpose of`
18			`// programming logic devices manufactured by Altera and sold by`
19			`// Altera or its authorized distributors. Please refer to the`
20			`// applicable agreement for further details.`
21
22			`// You may only use these simulation model output files for simulation`
23			`// purposes and expressly not for synthesis or any other purposes (in which`
24			`// event Altera disclaims all warranties of any kind).`
25
26
27			`//synopsys translate_off`
28
29	20	jefflieu	`//synthesis_resources = altera_std_synchronizer 8 altera_std_synchronizer_bundle 3 altpll 1 altsyncram 2 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 lut 942 mux21 1096 oper_add 27 oper_decoder 4 oper_less_than 11 oper_mux 16 oper_selector 42`
30	9	jefflieu	`timescale 1 ps / 1 ps
31			`module sgmii`
32			`(`
33			`address,`
34			`clk,`
35			`gmii_rx_d,`
36			`gmii_rx_dv,`
37			`gmii_rx_err,`
38			`gmii_tx_d,`
39			`gmii_tx_en,`
40			`gmii_tx_err,`
41			`gxb_cal_blk_clk,`
42			`gxb_pwrdn_in,`
43			`hd_ena,`
44			`led_an,`
45			`led_char_err,`
46			`led_col,`
47			`led_crs,`
48			`led_disp_err,`
49			`led_link,`
50			`mii_col,`
51			`mii_crs,`
52			`mii_rx_d,`
53			`mii_rx_dv,`
54			`mii_rx_err,`
55			`mii_tx_d,`
56			`mii_tx_en,`
57			`mii_tx_err,`
58			`pcs_pwrdn_out,`
59			`read,`
60			`readdata,`
61			`reconfig_busy,`
62			`reconfig_clk,`
63			`reconfig_fromgxb,`
64			`reconfig_togxb,`
65			`ref_clk,`
66			`reset,`
67			`reset_rx_clk,`
68			`reset_tx_clk,`
69			`rx_clk,`
70			`rx_clkena,`
71			`rx_recovclkout,`
72			`rxp,`
73			`set_10,`
74			`set_100,`
75			`set_1000,`
76			`tx_clk,`
77			`tx_clkena,`
78			`txp,`
79			`waitrequest,`
80			`write,`
81			`writedata) /* synthesis synthesis_clearbox=1 */;`
82			`input [4:0] address;`
83			`input clk;`
84			`output [7:0] gmii_rx_d;`
85			`output gmii_rx_dv;`
86			`output gmii_rx_err;`
87			`input [7:0] gmii_tx_d;`
88			`input gmii_tx_en;`
89			`input gmii_tx_err;`
90			`input gxb_cal_blk_clk;`
91			`input gxb_pwrdn_in;`
92			`output hd_ena;`
93			`output led_an;`
94			`output led_char_err;`
95			`output led_col;`
96			`output led_crs;`
97			`output led_disp_err;`
98			`output led_link;`
99			`output mii_col;`
100			`output mii_crs;`
101			`output [3:0] mii_rx_d;`
102			`output mii_rx_dv;`
103			`output mii_rx_err;`
104			`input [3:0] mii_tx_d;`
105			`input mii_tx_en;`
106			`input mii_tx_err;`
107			`output pcs_pwrdn_out;`
108			`input read;`
109			`output [15:0] readdata;`
110			`input reconfig_busy;`
111			`input reconfig_clk;`
112	20	jefflieu	`output [4:0] reconfig_fromgxb;`
113	9	jefflieu	`input [3:0] reconfig_togxb;`
114			`input ref_clk;`
115			`input reset;`
116			`input reset_rx_clk;`
117			`input reset_tx_clk;`
118			`output rx_clk;`
119			`output rx_clkena;`
120			`output rx_recovclkout;`
121			`input rxp;`
122			`output set_10;`
123			`output set_100;`
124			`output set_1000;`
125			`output tx_clk;`
126			`output tx_clkena;`
127			`output txp;`
128			`output waitrequest;`
129			`input write;`
130			`input [15:0] writedata;`
131
132	20	jefflieu	`wire wire_n1i10i_dout;`
133			`wire wire_n1i10O_dout;`
134			`wire wire_n1i11O_dout;`
135	9	jefflieu	`wire wire_n1i1ii_dout;`
136	20	jefflieu	`wire wire_nlili0O_dout;`
137			`wire wire_nliliii_dout;`
138			`wire wire_nliliil_dout;`
139			`wire wire_nliliiO_dout;`
140			`wire [1:0] wire_n01ill_dout;`
141			`wire [1:0] wire_n01ilO_dout;`
142			`wire [15:0] wire_n1i10l_dout;`
143			`wire [5:0] wire_nl01O_clk;`
144			`wire wire_nl01O_fref;`
145			`wire wire_nl01O_icdrclk;`
146			`wire wire_nl01O_locked;`
147	9	jefflieu	`wire [9:0] wire_n00OOO_q_b;`
148			`wire [9:0] wire_ni1O0i_q_b;`
149	20	jefflieu	`wire wire_nl0iO_nonusertocmu;`
150			`wire wire_nl0il_dpriodisableout;`
151			`wire wire_nl0il_dprioout;`
152			`wire wire_nl0il_quadresetout;`
153			`wire [3:0] wire_nl0il_rxanalogresetout;`
154			`wire [3:0] wire_nl0il_rxcrupowerdown;`
155			`wire [3:0] wire_nl0il_rxdigitalresetout;`
156			`wire [3:0] wire_nl0il_rxibpowerdown;`
157			`wire [1599:0] wire_nl0il_rxpcsdprioout;`
158			`wire [1199:0] wire_nl0il_rxpmadprioout;`
159			`wire [3:0] wire_nl0il_txanalogresetout;`
160			`wire [3:0] wire_nl0il_txdetectrxpowerdown;`
161			`wire [3:0] wire_nl0il_txdigitalresetout;`
162			`wire [3:0] wire_nl0il_txdividerpowerdown;`
163			`wire [3:0] wire_nl0il_txobpowerdown;`
164			`wire [599:0] wire_nl0il_txpcsdprioout;`
165			`wire [1199:0] wire_nl0il_txpmadprioout;`
166			`wire wire_nl0ii_cdrctrllocktorefclkout;`
167			`wire wire_nl0ii_clkout;`
168			`wire [1:0] wire_nl0ii_ctrldetect;`
169			`wire [19:0] wire_nl0ii_dataout;`
170			`wire [1:0] wire_nl0ii_disperr;`
171			`wire [399:0] wire_nl0ii_dprioout;`
172			`wire [1:0] wire_nl0ii_errdetect;`
173			`wire [1:0] wire_nl0ii_patterndetect;`
174			`wire wire_nl0ii_rlv;`
175			`wire [1:0] wire_nl0ii_runningdisp;`
176			`wire [1:0] wire_nl0ii_syncstatus;`
177			`wire wire_nl00O_clockout;`
178			`wire wire_nl00O_diagnosticlpbkout;`
179			`wire [299:0] wire_nl00O_dprioout;`
180			`wire wire_nl00O_freqlocked;`
181			`wire [9:0] wire_nl00O_recoverdataout;`
182			`wire wire_nl00O_reverselpbkout;`
183			`wire wire_nl00O_signaldetect;`
184			`wire wire_nl00l_clkout;`
185			`wire [9:0] wire_nl00l_dataout;`
186			`wire [149:0] wire_nl00l_dprioout;`
187			`wire wire_nl00l_txdetectrx;`
188			`wire wire_nl00i_clockout;`
189			`wire wire_nl00i_dataout;`
190			`wire [299:0] wire_nl00i_dprioout;`
191			`wire wire_nl00i_seriallpbkout;`
192			`reg nli000i55;`
193			`reg nli000i56;`
194			`reg nli001O57;`
195			`reg nli001O58;`
196			`reg nli010i59;`
197			`reg nli010i60;`
198			`reg nli011l63;`
199			`reg nli011l64;`
200			`reg nli011O61;`
201			`reg nli011O62;`
202			`reg nli0l0i53;`
203			`reg nli0l0i54;`
204			`reg nli0lii51;`
205			`reg nli0lii52;`
206			`reg nli0liO49;`
207			`reg nli0liO50;`
208			`reg nli0lll47;`
209			`reg nli0lll48;`
210			`reg nli0lOi45;`
211			`reg nli0lOi46;`
212			`reg nli0O0i41;`
213			`reg nli0O0i42;`
214			`reg nli0O1l43;`
215			`reg nli0O1l44;`
216			`reg nli0Oii39;`
217			`reg nli0Oii40;`
218			`reg nli0OiO37;`
219			`reg nli0OiO38;`
220			`reg nli0OlO35;`
221			`reg nli0OlO36;`
222			`reg nli0OOl33;`
223			`reg nli0OOl34;`
224			`reg nli1llO79;`
225			`reg nli1llO80;`
226			`reg nli1lOi77;`
227			`reg nli1lOi78;`
228			`reg nli1O0O75;`
229			`reg nli1O0O76;`
230			`reg nli1Oii73;`
231			`reg nli1Oii74;`
232			`reg nli1Oil71;`
233			`reg nli1Oil72;`
234			`reg nli1OlO69;`
235			`reg nli1OlO70;`
236			`reg nli1OOi67;`
237			`reg nli1OOi68;`
238			`reg nli1OOl65;`
239			`reg nli1OOl66;`
240			`reg nlii00l13;`
241			`reg nlii00l14;`
242			`reg nlii01i19;`
243			`reg nlii01i20;`
244			`reg nlii01l17;`
245			`reg nlii01l18;`
246			`reg nlii01O15;`
247			`reg nlii01O16;`
248			`reg nlii0ii11;`
249			`reg nlii0ii12;`
250			`reg nlii0il10;`
251			`reg nlii0il9;`
252			`reg nlii0Oi7;`
253			`reg nlii0Oi8;`
254			`reg nlii0Ol5;`
255			`reg nlii0Ol6;`
256			`reg nlii0OO3;`
257			`reg nlii0OO4;`
258			`reg nlii10i29;`
259			`reg nlii10i30;`
260			`reg nlii10O27;`
261			`reg nlii10O28;`
262			`reg nlii11l31;`
263			`reg nlii11l32;`
264			`reg nlii1iO25;`
265			`reg nlii1iO26;`
266			`reg nlii1ll23;`
267			`reg nlii1ll24;`
268			`reg nlii1Ol21;`
269			`reg nlii1Ol22;`
270			`reg nliii1l1;`
271			`reg nliii1l2;`
272			`reg n00iO;`
273			`reg n011l;`
274			`reg n011O;`
275	9	jefflieu	`reg n01ll;`
276	20	jefflieu	`reg n01Ol;`
277			`reg n01OO;`
278	9	jefflieu	`reg n10ii;`
279	20	jefflieu	`reg n10il;`
280			`reg n11OO;`
281			`reg n1i1l;`
282			`reg n1l1i;`
283			`reg n1O0i;`
284			`reg n00ll;`
285			`reg n01lO;`
286			`reg n101i;`
287			`reg n10lO;`
288	9	jefflieu	`reg n1i0O;`
289	20	jefflieu	`reg n1iiO;`
290	9	jefflieu	`reg n1ill;`
291	20	jefflieu	`reg n1iOO;`
292	9	jefflieu	`reg n1l0O;`
293	20	jefflieu	`reg n1lii;`
294			`reg n1llO;`
295			`reg n1O1i;`
296			`reg n1O1l;`
297	9	jefflieu	`reg n1O1O;`
298	20	jefflieu	`reg n1Oll;`
299	9	jefflieu	`reg n1OlO;`
300	20	jefflieu	`reg n00Oii;`
301			`reg n00Oll;`
302			`reg n00OOl;`
303			`reg n01iil;`
304			`reg n01ili;`
305	9	jefflieu	`reg n0i01l;`
306			`reg n0i10i;`
307			`reg n0i10l;`
308			`reg n0i11i;`
309			`reg n0i11l;`
310			`reg n0i11O;`
311			`reg n0i1iO;`
312			`reg n0i1li;`
313			`reg n0i1ll;`
314			`reg n0i1Ol;`
315			`reg n0i1OO;`
316	20	jefflieu	`reg n0i0l;`
317			`reg n0iii;`
318	9	jefflieu	`reg n0i1Oi;`
319			`reg n0ii0O;`
320			`reg n0i0iO;`
321			`reg n0i0li;`
322			`reg n0i0ll;`
323			`reg n0i0lO;`
324			`reg n0i0Oi;`
325			`reg n0ii0i;`
326			`reg n0ii1l;`
327			`reg n0ii1O;`
328			`reg n0iiil;`
329			`reg n0iiiO;`
330			`reg n0iill;`
331			`reg n0iOii;`
332			`reg n0iO0i;`
333			`reg n0010i;`
334			`reg n0010l;`
335			`reg n0010O;`
336	20	jefflieu	`reg n0011i;`
337	9	jefflieu	`reg n001ii;`
338			`reg n001il;`
339			`reg n001iO;`
340			`reg n001li;`
341			`reg n00lOO;`
342			`reg n00O0l;`
343			`reg n00O0O;`
344			`reg n00O1i;`
345			`reg n00Oil;`
346			`reg n00OiO;`
347			`reg n00Oli;`
348			`reg n00OlO;`
349	20	jefflieu	`reg n01l0l;`
350			`reg n01l0O;`
351			`reg n01lOi;`
352			`reg n01lOl;`
353	9	jefflieu	`reg n01lOO;`
354			`reg n01O0i;`
355			`reg n01O0l;`
356			`reg n01O0O;`
357			`reg n01O1i;`
358			`reg n01O1l;`
359			`reg n01O1O;`
360			`reg n01Oii;`
361			`reg n01OiO;`
362			`reg n01OOO;`
363			`reg n0ilOi;`
364			`reg n0ilOO;`
365			`reg n0iO1i;`
366			`reg n0iO1l;`
367			`reg n0l01i;`
368			`reg n0l01O;`
369			`reg n0l11l;`
370			`reg n0l1iO;`
371			`reg n0l1ll;`
372			`reg n0l1lO;`
373			`reg n0l1Oi;`
374			`reg n0l1Ol;`
375			`reg n0l1OO;`
376			`reg n0iOil;`
377			`reg n0iOli;`
378			`reg n0iOll;`
379			`reg n0iOlO;`
380			`reg n0iOOi;`
381			`reg n0iOOl;`
382			`reg n0iOOO;`
383			`reg n0l0ll;`
384			`reg n0l11i;`
385			`reg n0li0O;`
386			`reg n0liil;`
387			`reg n0lili;`
388			`reg n0liOi;`
389			`reg n0liOl;`
390			`reg n0liOO;`
391			`reg n0ll1i;`
392			`reg n0ll1l;`
393			`reg n0ll1O;`
394			`reg n0llli;`
395			`reg n0llll;`
396			`reg n0lllO;`
397			`reg n0llOi;`
398			`reg n0llOl;`
399			`reg n0llOO;`
400			`reg n0O10i;`
401			`reg n0O10l;`
402			`reg n0O10O;`
403			`reg n0O11O;`
404			`reg n0O1ii;`
405			`reg n0O1il;`
406			`reg n0O1iO;`
407			`reg n0O1li;`
408			`reg n0O1ll;`
409			`reg n0O1Oi;`
410			`reg n0O0ll;`
411			`reg n0O0Oi;`
412			`reg n0Oiil;`
413	20	jefflieu	`reg n101ll;`
414			`reg nlOi01l;`
415	9	jefflieu	`reg n0lO0O;`
416			`reg n0lO1i;`
417			`reg n0O0iO;`
418			`reg n0O11i;`
419			`reg n0Oi1i;`
420			`reg n0Oili;`
421	20	jefflieu	`reg nlil01i;`
422			`reg nlil01l;`
423	9	jefflieu	`reg nlil01O;`
424	20	jefflieu	`reg nlil10i;`
425			`reg nlil1li;`
426			`reg nlil1ll;`
427	9	jefflieu	`reg nlil1lO;`
428	20	jefflieu	`reg nlil1Oi;`
429			`reg nlil1Ol;`
430			`reg nlil1OO;`
431			`reg nlili1i;`
432	9	jefflieu	`reg n0O0li;`
433			`reg n0O0lO;`
434			`reg n0OilO;`
435	20	jefflieu	`reg nlil0OO;`
436			`reg nlil1il;`
437			`reg nlili1l;`
438			`reg n01i0O;`
439			`reg n01iii;`
440	9	jefflieu	`reg n0OiOi;`
441			`reg n0OiOl;`
442			`reg n0OiOO;`
443			`reg n0Ol1l;`
444			`reg n0Ol0i;`
445			`reg n0Ol0l;`
446			`reg n0Ol0O;`
447			`reg n0Ol1O;`
448			`reg n0Olii;`
449			`reg n0Olil;`
450			`reg n0OliO;`
451			`reg n0Olli;`
452			`reg n0Olll;`
453			`reg n0OO1l;`
454	20	jefflieu	`reg n110l;`
455			`reg n11ii;`
456			`reg nl010i;`
457			`reg nllllO;`
458			`reg nlOOll;`
459			`reg n11il;`
460			`reg n11iO;`
461			`reg n11li;`
462			`reg n11ll;`
463			`reg n11lO;`
464			`reg n11Ol;`
465			`wire wire_n11Oi_CLRN;`
466	9	jefflieu	`reg ni00ll;`
467			`reg ni001i;`
468			`reg ni001l;`
469			`reg ni001O;`
470			`reg ni00ii;`
471			`reg ni00il;`
472			`reg ni00iO;`
473			`reg ni00lO;`
474			`reg ni00Oi;`
475			`reg ni00OO;`
476			`reg ni01Ol;`
477			`reg ni01OO;`
478			`reg ni010i;`
479			`reg ni010l;`
480			`reg ni01ii;`
481			`reg ni1O0l;`
482			`reg ni1O0O;`
483			`reg ni1Oii;`
484			`reg ni1Oil;`
485			`reg ni1OiO;`
486			`reg ni1OOi;`
487			`reg ni1OOl;`
488			`reg ni1OOO;`
489			`reg ni011l;`
490			`reg ni0lli;`
491			`reg ni0l0i;`
492			`reg ni0l0l;`
493			`reg ni0l0O;`
494			`reg ni0l1l;`
495			`reg ni0O0O;`
496			`reg ni1i1l;`
497			`reg ni0OOi;`
498			`reg ni0OOO;`
499			`reg nii10i;`
500			`reg nii10l;`
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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [sgmii.vo] - Blame information for rev 20

Line No.	Rev	Author	Line
1	9	jefflieu	`//IP Functional Simulation Model`
2	20	jefflieu	`//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:10:19:19:54:28:SJ cbx_simgen 2012:10:19:19:52:08:SJ VERSION_END`
3	9	jefflieu	`// synthesis VERILOG_INPUT_VERSION VERILOG_2001`
4			`// altera message_off 10463`
5
6
7
8	20	jefflieu	`// Copyright (C) 1991-2012 Altera Corporation`
9	9	jefflieu	`// Your use of Altera Corporation's design tools, logic functions`
10			`// and other software and tools, and its AMPP partner logic`
11			`// functions, and any output files from any of the foregoing`
12			`// (including device programming or simulation files), and any`
13			`// associated documentation or information are expressly subject`
14			`// to the terms and conditions of the Altera Program License`
15			`// Subscription Agreement, Altera MegaCore Function License`
16			`// Agreement, or other applicable license agreement, including,`
17			`// without limitation, that your use is for the sole purpose of`
18			`// programming logic devices manufactured by Altera and sold by`
19			`// Altera or its authorized distributors. Please refer to the`
20			`// applicable agreement for further details.`
21
22			`// You may only use these simulation model output files for simulation`
23			`// purposes and expressly not for synthesis or any other purposes (in which`
24			`// event Altera disclaims all warranties of any kind).`
25
26
27			`//synopsys translate_off`
28
29	20	jefflieu	`//synthesis_resources = altera_std_synchronizer 8 altera_std_synchronizer_bundle 3 altpll 1 altsyncram 2 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 lut 942 mux21 1096 oper_add 27 oper_decoder 4 oper_less_than 11 oper_mux 16 oper_selector 42`
30	9	jefflieu	`timescale 1 ps / 1 ps
31			`module sgmii`
32			`(`
33			`address,`
34			`clk,`
35			`gmii_rx_d,`
36			`gmii_rx_dv,`
37			`gmii_rx_err,`
38			`gmii_tx_d,`
39			`gmii_tx_en,`
40			`gmii_tx_err,`