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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [sgmii_constraints.sdc] - Blame information for rev 20

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1 9 jefflieu 
#####################################################################################
2 
# Copyright (C) 1991-2009 Altera Corporation
3 
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
4 
# support information,  device programming or simulation file,  and any other
5 
# associated  documentation or information  provided by  Altera  or a partner
6 
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
7 
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
8 
# other  use  of such  megafunction  design,  netlist,  support  information,
9 
# device programming or simulation file,  or any other  related documentation
10 
# or information  is prohibited  for  any  other purpose,  including, but not
11 
# limited to  modification,  reverse engineering,  de-compiling, or use  with
12 
# any other  silicon devices,  unless such use is  explicitly  licensed under
13 
# a separate agreement with  Altera  or a megafunction partner.  Title to the
14 
# intellectual property,  including patents,  copyrights,  trademarks,  trade
15 
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
16 
# support  information,  device programming or simulation file,  or any other
17 
# related documentation or information provided by  Altera  or a megafunction
18 
# partner, remains with Altera, the megafunction partner, or their respective
19 
# licensors. No other licenses, including any licenses needed under any third
20 
# party's intellectual property, are provided herein.
21 
#####################################################################################
22 
 
23 
#####################################################################################
24 
# Altera Triple-Speed Ethernet Megacore SDC file for use with the Quartus II
25 
# TimeQuest Timing Analyzer
26 
#
27 
# To add this SDC file to your Quartus II project execute the following TCL
28 
# command in the Quartus II TCL console:
29 
# set_global_assignment -name SDC_FILE "sgmii"_constraints.sdc
30 
#
31 20 jefflieu 
# Generated on Sat Nov 10 09:38:18 SGT 2012
32 9 jefflieu 
#
33 
#####################################################################################
34 
 
35 
 
36 
 
37 
 
38 
 
39 
# *************************************************************
40 
# Customer modifiable constraints, value is set default by constraints
41 
# *************************************************************
42 
 
43 
# Hierarchical path to the TSE
44 
set SYSTEM_PATH_PREFIX ""
45 
 
46 
# Frequency of network-side interface clocks or reference clocks
47 
set TSE_CLOCK_FREQUENCY "125 MHz"
48 
 
49 
# Frequency of FIFO data interface clocks
50 
set FIFO_CLOCK_FREQUENCY "100 MHz"
51 
 
52 
# Frequency of control and status interface clock
53 
set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz"
54 
 
55 
# Name the clocks that will be coming into the tse core named changed from top level
56 
set  TX_CLK             "tx_clk"
57 
set  RX_CLK             "rx_clk"
58 
set  CLK                "clk"
59 
set  FF_TX_CLK          "ff_tx_clk"
60 
set  FF_RX_CLK          "ff_rx_clk"
61 
set  TBI_TX_CLK         "tbi_tx_clk"
62 
set  TBI_RX_CLK         "tbi_rx_clk"
63 
set  REF_CLK            "ref_clk"
64 
 
65 
 
66 
 
67 
 
68 
 
69 
# **************************************************************************************************
70 
# ********************** Please do not modify anything beyond this line ****************************
71 
# *********** The script might not work correctly if the following lines are modified **************
72 
# **************************************************************************************************
73 
 
74 
# Generated TSE variation - Do not modify
75 
# General Option
76 
set IS_SOPC 0
77 
set VARIATION_NAME "sgmii"
78 
set DEVICE_FAMILY "CYCLONEIVGX"
79 
 
80 
# MAC Option
81 
set IS_MAC 0
82 
set NUMBER_OF_CHANNEL 1
83 
set IS_SMALLMAC 0
84 
set IS_SMALLMAC_GIGE 0
85 
set IS_FIFOLESS 0
86 
set IS_HALFDUPLEX 0
87 
set MII_INTERFACE "MII_GMII"
88 
 
89 
# PCS Option
90 
set IS_PCS 1
91 
set IS_SGMII 1
92 
 
93 
# PMA Option
94 
set IS_PMA 1
95 
set TRANSCEIVER_TYPE 0
96 
 
97 
# GXB Option
98 
set IS_POWERDOWN 1
99 
 
100 
 
101 
 
102 
if { [ expr ($TRANSCEIVER_TYPE == 0)]} {
103 
        set CLOCK_1  "U_RXCLK"
104 
        set CLOCK_2 "U_TXCLK"
105 
} else {
106 
        set CLOCK_1 "U_RXCLK"
107 
        set CLOCK_2 "U_TXCLK"
108 
}
109 
 
110 
if { [ expr ($IS_SOPC == 1) ]} {
111 
   set FROM_THE_VARIATION_NAME "_from_the_$VARIATION_NAME"
112 
   set TO_THE_VARIATION_NAME "_to_the_$VARIATION_NAME"
113 
} else {
114 
   set FROM_THE_VARIATION_NAME ""
115 
   set TO_THE_VARIATION_NAME ""
116 
}
117 
 
118 
 
119 
#**************************************************************
120 
# Time Information
121 
#**************************************************************
122 
# Uncommenting the following derive_pll_clocks lines
123 
# will instruct the TimeQuest Timing Analyzer to automatically
124 
# create derived clocks for all PLL outputs for all PLLs in a
125 
# Quartus design.
126 
 
127 
# If the PLL inputs and outputs are not constrained elsewhere,
128 
# uncomment the next line to automatically constrain all PLL input
129 
# and output clocks.
130 
 
131 
# derive_pll_clocks
132 
 
133 
# If the PLL inputs and outputs are not constrained elsewhere,
134 
# and derive_pll_clocks is not apply, user will get Critical warnings
135 
# Critical Warning: Register-to-register paths between different clock
136 
# domains is not recommended if one of the clocks is from GXB
137 
# transmitter channel.
138 
# Critical Warning: Register-to-register paths between different clock
139 
# domains is not recommended if one of the clocks is from GXB
140 
# receiver channel.
141 
# This Critical Warning can be safely ignore and it will gone if
142 
# PLL inputs and outputs clock are properly constraint.
143 
 
144 
#**************************************************************
145 
# Create Clock
146 
#**************************************************************
147 
 
148 
#Constrain timing for half duplex logic
149 
#  - Direct path as we are confirmed of this path
150 
if { [ expr ( $IS_FIFOLESS == 0 )] } {
151 
 
152 
#  mac
153 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0)] } {
154 
      #Constrain MAC control interface clock
155 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
156 
 
157 
      #Constrain MAC FIFO data interface clocks
158 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
159 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
160 
 
161 
      #Constrain MAC network-side interface clocks
162 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TX_CLK]
163 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $RX_CLK]
164 
   }
165 
 
166 
   #  macPcs
167 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
168 
      #Constrain MAC PCS control interface clock
169 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
170 
 
171 
      #Constrain MAC PCS FIFO data interface clocks
172 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
173 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
174 
 
175 
      #Constrain MAC PCS network-side interface clocks
176 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
177 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
178 
   }
179 
 
180 
   #  macPcsPma
181 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
182 
 
183 
      #Constrain transceiver reference clock
184 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports  $REF_CLK]
185 
 
186 
      #Constrain MAC PCS control interface clock
187 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
188 
 
189 
      #Constrain MAC PCS FIFO data interface clocks
190 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
191 
      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
192 
   }
193 
 
194 
   #  pcs
195 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
196 
 
197 
          #Cut the timing path betweeen unrelated clock domains
198 
 
199 
   }
200 
 
201 
   #  pcsPma
202 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
203 
      #Constrain PCS control interface clock
204 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports $CLK]
205 
 
206 
      #Constrain transceiver reference clock
207 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports  $REF_CLK]
208 
   }
209 
 
210 
   #  macPcsSgmii
211 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
212 
   }
213 
 
214 
   # macPcsNoSgmii
215 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
216 
 
217 
   }
218 
 
219 
   #  macPcsPmaSgmii
220 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
221 
   }
222 
 
223 
   #  macPcsPmaNoSgmii
224 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0)] } {
225 
   }
226 
 
227 
   #  pmaAlt4Gxb
228 
   if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
229 
   }
230 
 
231 
   #  pcsSgmii
232 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
233 
      #Constrain PCS GMII/MII interface clocks
234 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
235 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
236 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
237 
    }
238 
 
239 
   #  pcsNoSgmii
240 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
241 
      #Constrain PCS control interface clock
242 
      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
243 
 
244 
      #Constrain PCS network-side interface clocks
245 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
246 
      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
247 
 
248 
   }
249 
 
250 
   #  pcsPmaSgmii
251 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
252 
      #Constrain PCS GMII/MII interface clocks
253 
   }
254 
 
255 
 
256 
   #  pcsPmaNoSgmii
257 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
258 
   }
259 
 
260 
   #  macPcsPmaLvdsSgmii
261 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
262 
     #Cut the timing path betweeen unrelated clock domains
263 
   }
264 
 
265 
   #  macPcsPmaLvdsNoSgmii
266 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
267 
   }
268 
 
269 
   #  macPcsPmaTransceiverSgmii=
270 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
271 
      #Cut the timing path betweeen unrelated clock domains
272 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
273 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
274 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
275 
   }
276 
 
277 
   #  macPcsPmaTransceiverNoSgmii=
278 
   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
279 
      #Cut the timing path betweeen unrelated clock domains
280 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
281 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
282 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
283 
   }
284 
 
285 
   #  pcsPmaLvdsSgmii=
286 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
287 
      #Cut the timing path betweeen unrelated clock domains
288 
   }
289 
 
290 
   #  pcsPmaLvdsNoSgmii
291 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
292 
   }
293 
 
294 
   #  pcsPmaTransceiverSgmii
295 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"])) ] } {
296 
      #Cut the timing path betweeen unrelated clock domains
297 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TSE_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
298 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
299 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group  [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
300 
   }
301 
 
302 
   #  pcsPmaTransceiverNoSgmii
303 
   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
304 
      #Cut the timing path betweeen unrelated clock domains
305 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
306 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
307 
      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
308 
   }
309 
 
310 
   # Universal Clock Group setter
311 
 
312 
   set clocks_list [get_clocks *]
313 
 
314 
   foreach_in_collection clock $clocks_list {
315 
        set name [get_clock_info -name $clock]
316 
        if {[ expr [regexp "altera_tse" $name] == 1]} {
317 
 
318 
            # Do not cut timing path for LVDS RX clock with ref_clk as they are related
319 
            if {[ expr [regexp "ALTLVDS_RX_component" $name] || [regexp $REF_CLK $name]]} {
320 
                if { [ expr ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 1)] } {
321 
                    set_clock_groups -asynchronous -group [get_clocks "altera_tse_${REF_CLK}* *|ALTLVDS_RX_component|auto_generated|rx[0]|clk0 *|ALTLVDS_RX_component|auto_generated|pll|clk[0]"]
322 
                    if {[expr ([string match $DEVICE_FAMILY "STRATIXV"])]} {
323 
                                                set_clock_groups -asynchronous -group [get_clocks "altera_tse_${REF_CLK}* *|ALTLVDS_RX_component|auto_generated|rx[0]|dpaclkin[0]"]
324 
                                        }
325 
                } else {
326 
                    set_clock_groups -asynchronous -group [get_clocks $name]
327 
                }
328 
            } else {
329 
                set_clock_groups -asynchronous -group [get_clocks $name]
330 
            }
331 
        }
332 
    }
333 
 
334 
 
335 
} else {
336 
 
337 
#  multiChannelFifoless
338 
 
339 
 
340 
#**************************************************************
341 
# Set Parameter
342 
#**************************************************************
343 
#**************************************************************
344 
 
345 
#**************************************************************
346 
# Create Clock
347 
#**************************************************************
348 
#**************************************************************
349 
 
350 
#All clocks used by TSE is named with prefix "altera_tse"
351 
#Constrain MAC PCS control interface clock
352 
 
353 
if { [ expr $IS_SOPC == 0 ] } {
354 
        create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_sys_clk [ get_ports "$CLK"]
355 
}
356 
 
357 
if { [ expr ($IS_FIFOLESS == 1) ] } {
358 
   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
359 
                if { [ expr ($IS_SOPC == 0) ] } {
360 
                        create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_tx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
361 
                        create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_rx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
362 
                } else {
363 
                        create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_rx_clk_${x}_out" ]
364 
                        create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_tx_clk_${x}_out" ]
365 
                }
366 
   }
367 
}
368 
 
369 
# Mac
370 
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) ] } {
371 
   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
372 
                create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tx_clk_${x}$TO_THE_VARIATION_NAME" ]
373 
                create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}rx_clk_${x}$TO_THE_VARIATION_NAME" ]
374 
   }}
375 
 
376 
# MacPcs
377 
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
378 
   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
379 
                create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_tx_clk_${x}$TO_THE_VARIATION_NAME" ]
380 
                create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_rx_clk_${x}$TO_THE_VARIATION_NAME" ]
381 
   }}
382 
 
383 
# MacPcsPma
384 
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
385 
        #Constrain transceiver reference clock
386 
        create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports  "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
387 
}
388 
 
389 
# MacPcs+SGMII
390 
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
391 
        #Constrain transceiver reference clock
392 
        create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports  "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
393 
}
394 
 
395 
# MacPcs+SGMII ( with or without PMA )
396 
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_SGMII == 1)] } {
397 
 
398 
}
399 
 
400 
#  pmaAlt4Gxb
401 
if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
402 
 
403 
}
404 
 
405 
#  macPcsPmaLvdsSgmii
406 
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
407 
        #Cut the timing path betweeen unrelated clock domains
408 
}
409 
 
410 
#  macPcsPmaLvdsNoSgmii
411 
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
412 
}
413 
 
414 
#  macPcsPmaTransceiverSgmii=
415 
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
416 
        #Cut the timing path betweeen unrelated clock domains
417 
}
418 
 
419 
#  macPcsPmaTransceiverNoSgmii=
420 
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
421 
        #Cut the timing path betweeen unrelated clock domains
422 
}
423 
 
424 
if { [ expr ($IS_SOPC == 0) ] } {
425 
        if { [ expr ($IS_FIFOLESS == 1) ] } {
426 
                create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_rx_afull_clk  [get_ports "${SYSTEM_PATH_PREFIX}rx_afull_clk$TO_THE_VARIATION_NAME" ]
427 
        }
428 
}
429 
 
430 
 
431 
set clocks_list [get_clocks *]
432 
 
433 
foreach_in_collection clock $clocks_list {
434 
    set name [get_clock_info -name $clock]
435 
    if {[ expr [regexp "altera_tse" $name] == 1]} {
436 
 
437 
        # Do not cut timing path for LVDS RX clock with ref_clk as they are related
438 
        if {[ expr [regexp "ALTLVDS_RX_component" $name] || [regexp $REF_CLK $name]]} {
439 
            if { [ expr ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 1)] } {
440 
                set_clock_groups -asynchronous -group [get_clocks "altera_tse_${REF_CLK}* *|ALTLVDS_RX_component|auto_generated|rx[0]|clk0 *|ALTLVDS_RX_component|auto_generated|pll|clk[0]"]
441 
            } else {
442 
                set_clock_groups -asynchronous -group [get_clocks $name]
443 
            }
444 
        } else {
445 
            set_clock_groups -asynchronous -group [get_clocks $name]
446 
        }
447 
    }
448 
}
449 
 
450 
 
451 
#**************************************************************
452 
# Set False Path
453 
#**************************************************************
454 
if { [ expr ($IS_SGMII == 1)] } {
455 
    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
456 
    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|b_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
457 
    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|wr_g_rptr[*]}]
458 
    set_false_path -from [get_registers {*|altera_tse_top_sgmii*:U_SGMII|altera_tse_colision_detect:U_COL|state*}] -to [get_registers {*|altera_tse_fifoless_mac_tx:U_TX|gm_rx_col_reg*}]
459 
    set_false_path -from [get_registers {*|altera_tse_a_fifo_34:RX_STATUS|wr_g_ptr_reg[*]}] -to [get_registers {*|altera_tse_a_fifo_34:RX_STATUS|wr_g_rptr[*]}]
460 
}
461 
 
462 
}
463 
 
464 
if { [ expr ($IS_HALFDUPLEX == 8) ] } {
465 
#Constrain timing for half duplex logic
466 
   if { [ expr ($IS_FIFOLESS == 0) ] } {
467 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
468 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
469 
      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
470 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
471 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
472 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
473 
      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
474 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
475 
      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|eop[1]]
476 
      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|sop[1]]
477 
      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers  *|altera_tse_mac_tx:U_TX|rd_1[*]]
478 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
479 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
480 
   }
481 
}
482 
 
483 
if { [ expr ($IS_HALFDUPLEX == 32) ] } {
484 
#Constrain timing for half duplex logic
485 
   if { [ expr ($IS_FIFOLESS == 0) ] } {
486 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
487 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
488 
      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
489 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
490 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
491 
      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
492 
      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
493 
      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
494 
      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
495 
   }
496 
}
497 
 
498 
if { [ expr ($IS_HALFDUPLEX == 8) ] } {
499 
#Constrain timing for half duplex logic
500 
   if { [ expr ($IS_FIFOLESS == 1) ] } {
501 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
502 
      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
503 
      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
504 
 
505 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
506 
      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
507 
      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
508 
   }
509 
}
510 
 

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