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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: ethgen2.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/ethgen2.v,v $
//
// $Revision: #1 $
// $Date: 2012/06/21 $
// Check in by : $Author: swbranch $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// MII Interface Ethernet Traffic Generator
//
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps
//`include "common_header.verilog" 
 
module ethgenerator2 (reset,
   rx_clk,
   rxd,
   rx_dv,
   rx_er,
   sop,
   eop,
   ethernet_speed,
   mii_mode,
   rgmii_mode,
   mac_reverse,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   cntstart,
   cntstep,
   ipg_len,
   payload_err,
   prmbl_err,
   crc_err,
   vlan_en,
   stack_vlan,
   pause_gen,
   pad_en,
   phy_err,
   end_err,
   data_only,
   carrier_sense,
   false_carrier,
   carrier_extend,
   carrier_extend_error,
   start,
   done);
parameter thold = 1'b 1;
input   reset; //  active high
input   rx_clk;
output   [7:0] rxd;
output   rx_dv;
output   rx_er;
output   sop; //  pulse with first character
output   eop; //  pulse with last  character
input   ethernet_speed;
input   mii_mode; //  4-bit Nibbles (Fast Ethernet)
input   rgmii_mode; //  4-bit DDR (Reduced Gigabit)
input   mac_reverse; //  1: dst/src are sent MSB first
input   [47:0] dst; //  destination address
input   [47:0] src; //  source address
input   [4:0] prmble_len; //  length of preamble
input   [15:0] pquant; //  Pause Quanta value
input   [15:0] vlan_ctl; //  VLAN control info
input   [15:0] len; //  Length of payload
input   [15:0] frmtype; //  if non-null: type field instead length
input   [7:0] cntstart; //  payload data counter start (first byte of payload)
input   [7:0] cntstep; //  payload counter step (2nd byte in paylaod)
input   [15:0] ipg_len; //  inter packet gap (delay after CRC)  
input   payload_err; //  generate payload pattern error (last payload byte is wrong)
input   prmbl_err;
input   crc_err;
input   vlan_en;
input   stack_vlan;
input   pause_gen;
input   pad_en;
input   phy_err;
input   end_err; //  keep rx_dv high one cycle after end of frame
input   data_only; //  if set omits preamble, padding, CRC
input   carrier_sense;
input   false_carrier;
input   carrier_extend;
input   carrier_extend_error;
input   start;
output   done;
//  GMII receive interface: To be connected to MAC RX
wire    [7:0] rxd;
wire    rx_dv;
//  Additional FIFO controls for FIFO test scenarios
wire    rx_er;
wire    sop;
//  Mode of Operation
wire    eop;
reg     done;
reg    gmii_clk;
wire    [7:0] gmii_d;
wire    gmii_en;
reg     gmii_en_d;
reg     gmii_err_d;
 
reg     gmii_10_100_en_d;
reg     gmii_10_100_err_d;
 
 
wire    gmii_er;
wire    sop_gen; //  pulse with first character
wire    eop_gen; //  pulse with last  character
wire    done_gen;
reg     eop_int; //  pulse with last  character
reg     sop_m;
reg     eop_m;
reg     [1:0] start_gen;
reg     clk_div2;
wire    [3:0] nib1;
reg     rgmii_en_er;
reg     rgmii_10_100_en_er;
reg     rgmii_10_100_en_er_d;
reg     rgmii_10_100_en_er_d2;
reg     rgmii_en_er_f;
reg     rgmii_10_100_en_er_f;
reg     [3:0] rgmii_dat;
reg     [3:0] rgmii_dat_f; //  save upper nibble for falling edge
reg     mii_en;
reg     mii_er;
wire    [3:0] mii_dat;
//  divide clock for nibble transfers 8-bit pathes
 
initial
   begin
      clk_div2 <= 1'b 0;
      start_gen <= 2'b 00;
   end
 
always @(posedge reset or posedge rx_clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      clk_div2 <= 1'b 0;
      start_gen <= 2'b 00;
      end
   else
      begin
      clk_div2 <= ~clk_div2;
      if (start == 1'b 1)
         begin
         start_gen <= {2{1'b 1}};
         end
      else
         begin
         start_gen[1:0] <= {1'b 0, start_gen[1]};   //  make it longer for MII mode
         end
      end
   end
//  multiplex GMII into RGMII/MII
initial
   begin
      rgmii_en_er <= 1'b 0;
      rgmii_en_er_f <= 1'b 0;
      rgmii_dat <= {4{1'b 0}};
      rgmii_dat_f <= {4{1'b 0}};
      sop_m <= 1'b 0;
      eop_m <= 1'b 0;
      gmii_en_d <= 1'b 0;
      gmii_err_d <= 1'b 0;
      mii_en <= 1'b 0;
      mii_er <= 1'b 0;
   end
 
always @(posedge reset or gmii_clk)
   begin : process_2
   if (reset == 1'b 1)
      begin
      rgmii_en_er <= 1'b 0;
      rgmii_en_er_f <= 1'b 0;
      rgmii_dat <= {4{1'b 0}};
      rgmii_dat_f <= {4{1'b 0}};
      sop_m <= 1'b 0;
      eop_m <= 1'b 0;
      gmii_en_d <= 1'b 0;
      gmii_err_d<= 1'b 0;
      end
   else
      begin
//  DDR
      if (gmii_clk == 1'b 1)
         begin
         gmii_en_d <= gmii_en;
         done <= done_gen & ~gmii_en;
//  FIFO signaling in right clock edge
         sop_m <= sop_gen;
         eop_int <= eop_gen;
                 if (mii_mode == 1'b 1 | rgmii_mode == 1'b1 & ethernet_speed == 1'b0)
            begin
//  not in MII, then EOP is 1 clock cycle already
            eop_m <= 1'b 0;
            end
         else
            begin
            eop_m <= eop_gen;
            end
//  Data and Control
         rgmii_dat <= #(thold) gmii_d[3:0];
         rgmii_dat_f <= gmii_d[7:4];
 
                 rgmii_en_er <= #(thold) gmii_en;
                 rgmii_en_er_f <= #(thold) gmii_er;
 
         mii_en <= #(thold) gmii_en;
         mii_er <= #(thold) gmii_er;
         end
      else
         begin
                 rgmii_en_er <= #(thold) rgmii_en_er_f ^ gmii_en_d;
         rgmii_dat <= #(thold) rgmii_dat_f; //  produce upper nibble 
 
 
                 if (mii_mode == 1'b 1 | rgmii_mode == 1'b1 & ethernet_speed == 1'b0)
            begin
            sop_m <= 1'b 0;
            eop_m <= eop_int;
            end
         end
      end
   end
 
 
//  multiplex GMII into RGMII/MII
initial
   begin
      rgmii_10_100_en_er <= 1'b 0;
      rgmii_10_100_en_er_f <= 1'b 0;
      gmii_10_100_en_d <= 1'b 0;
      gmii_10_100_err_d<= 1'b 0;
      rgmii_10_100_en_er_d <= 1'b0;
      rgmii_10_100_en_er_d2 <= 1'b0;
   end
 
always @(posedge reset or rx_clk)
   begin
   if (reset == 1'b 1)
      begin
      rgmii_10_100_en_er <= 1'b 0;
      rgmii_10_100_en_er_f <= 1'b 0;
      gmii_10_100_en_d <= 1'b 0;
      gmii_10_100_err_d<= 1'b 0;
      rgmii_10_100_en_er_d <= 1'b0;
      rgmii_10_100_en_er_d2 <= 1'b0;
 
      end
   else
      begin
        //  DDR
              if (rx_clk == 1'b 1)
                 begin
                 gmii_10_100_en_d <= gmii_en;
                 rgmii_10_100_en_er <= #(thold) gmii_en;
                 rgmii_10_100_en_er_f <= #(thold) gmii_er;
                 rgmii_10_100_en_er_d <= rgmii_10_100_en_er;
                 rgmii_10_100_en_er_d2 <= rgmii_10_100_en_er_d;
 
                 end
              else
                 begin
                 rgmii_10_100_en_er <= #(thold) rgmii_10_100_en_er_f ^ gmii_10_100_en_d;
                 rgmii_10_100_en_er_d <= rgmii_10_100_en_er;
                 rgmii_10_100_en_er_d2 <= rgmii_10_100_en_er_d;
                 end
       end
   end
 
 
 
 
 
//  connect clock
 
 
always @ (*)
 
 begin
   if (ethernet_speed == 1'b 0)
     begin
      if (rgmii_mode == 1'b1|mii_mode == 1'b1)
       gmii_clk <= clk_div2;
     end
   else
     begin
       gmii_clk <= rx_clk;
 end
 
 end
 
 
//  connect output ports
assign rxd[7:4] = rgmii_mode == 1'b 1 | mii_mode == 1'b 1 |
    reset == 1'b 1 ? 4'b 0000 :
    gmii_d[7:4];
assign rxd[3:0] = rgmii_mode == 1'b 1 | mii_mode == 1'b 1 | reset == 1'b 1 ? rgmii_dat : gmii_d[3:0];
assign rx_dv = reset == 1'b 1 ? 1'b 0 :
    rgmii_mode == 1'b 1 ? (ethernet_speed == 1'b1) ? rgmii_en_er: rgmii_10_100_en_er_d2 :
    mii_mode == 1'b 1 ? mii_en :
    gmii_en;
assign rx_er = reset == 1'b 1 ? 1'b 0 :
    rgmii_mode == 1'b 1 ? 1'b 0 :
    mii_mode == 1'b 1 ? mii_er :
    gmii_er;
assign #(thold) sop = rgmii_mode == 1'b 1 | mii_mode == 1'b 1 ? sop_m :
    sop_gen;
assign #(thold) eop = rgmii_mode == 1'b 1 | mii_mode == 1'b 1 ? eop_m :
    eop_gen;
 
ethgenerator #(2) gmii_gen (.reset(reset),
          //  active high
          .rx_clk(gmii_clk),
          .enable(1'b1),
          .rxd(gmii_d),
          .rx_dv(gmii_en),
          .rx_er(gmii_er),
          .sop(sop_gen),
          .eop(eop_gen),
          .mac_reverse(mac_reverse),
          .dst(dst),
          .src(src),
          .prmble_len(prmble_len),
          .pquant(pquant),
          .vlan_ctl(vlan_ctl),
          .len(len),
          .frmtype(frmtype),
          .cntstart(cntstart),
          .cntstep(cntstep),
          .ipg_len(ipg_len),
          .payload_err(payload_err),
          .prmbl_err(prmbl_err),
          .crc_err(crc_err),
          .vlan_en(vlan_en),
          .stack_vlan(stack_vlan),
          .pause_gen(pause_gen),
          .pad_en(pad_en),
          .phy_err(phy_err),
          .end_err(end_err),
          .data_only(data_only),
          .runt_gen(1'b0) ,
          .long_pause(1'b0) ,
          .carrier_sense(carrier_sense),
          .false_carrier(false_carrier),
          .carrier_extend(carrier_extend),
          .carrier_extend_error(carrier_extend_error),
          .start(start_gen[0]),
          .done(done_gen));
//  GMII Generator
//  --------------
 
endmodule // module ethgenerator2
 

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [ethgen2.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: ethgen2.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/ethgen2.v,v $`
8			`//`
9			`// $Revision: #1 $`
10	20	jefflieu	`// $Date: 2012/06/21 $`
11			`// Check in by : $Author: swbranch $`
12	9	jefflieu	`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// MII Interface Ethernet Traffic Generator`
19			`//`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps
29			//`include "common_header.verilog"
30
31			`module ethgenerator2 (reset,`
32			`rx_clk,`
33			`rxd,`
34			`rx_dv,`
35			`rx_er,`
36			`sop,`
37			`eop,`
38			`ethernet_speed,`
39			`mii_mode,`
40			`rgmii_mode,`
41			`mac_reverse,`
42			`dst,`
43			`src,`
44			`prmble_len,`
45			`pquant,`
46			`vlan_ctl,`
47			`len,`
48			`frmtype,`
49			`cntstart,`
50			`cntstep,`
51			`ipg_len,`
52			`payload_err,`
53			`prmbl_err,`
54			`crc_err,`
55			`vlan_en,`
56			`stack_vlan,`
57			`pause_gen,`
58			`pad_en,`
59			`phy_err,`
60			`end_err,`
61			`data_only,`
62			`carrier_sense,`
63			`false_carrier,`
64			`carrier_extend,`
65			`carrier_extend_error,`
66			`start,`
67			`done);`
68			`parameter thold = 1'b 1;`
69			`input reset; // active high`
70			`input rx_clk;`
71			`output [7:0] rxd;`
72			`output rx_dv;`
73			`output rx_er;`
74			`output sop; // pulse with first character`
75			`output eop; // pulse with last character`
76			`input ethernet_speed;`
77			`input mii_mode; // 4-bit Nibbles (Fast Ethernet)`
78			`input rgmii_mode; // 4-bit DDR (Reduced Gigabit)`
79			`input mac_reverse; // 1: dst/src are sent MSB first`
80			`input [47:0] dst; // destination address`
81			`input [47:0] src; // source address`
82			`input [4:0] prmble_len; // length of preamble`
83			`input [15:0] pquant; // Pause Quanta value`
84			`input [15:0] vlan_ctl; // VLAN control info`
85			`input [15:0] len; // Length of payload`
86			`input [15:0] frmtype; // if non-null: type field instead length`
87			`input [7:0] cntstart; // payload data counter start (first byte of payload)`
88			`input [7:0] cntstep; // payload counter step (2nd byte in paylaod)`
89			`input [15:0] ipg_len; // inter packet gap (delay after CRC)`
90			`input payload_err; // generate payload pattern error (last payload byte is wrong)`
91			`input prmbl_err;`
92			`input crc_err;`
93			`input vlan_en;`
94			`input stack_vlan;`
95			`input pause_gen;`
96			`input pad_en;`
97			`input phy_err;`
98			`input end_err; // keep rx_dv high one cycle after end of frame`
99			`input data_only; // if set omits preamble, padding, CRC`
100			`input carrier_sense;`
101			`input false_carrier;`
102			`input carrier_extend;`
103			`input carrier_extend_error;`
104			`input start;`
105			`output done;`
106			`// GMII receive interface: To be connected to MAC RX`
107			`wire [7:0] rxd;`
108			`wire rx_dv;`
109			`// Additional FIFO controls for FIFO test scenarios`
110			`wire rx_er;`
111			`wire sop;`
112			`// Mode of Operation`
113			`wire eop;`
114			`reg done;`
115			`reg gmii_clk;`
116			`wire [7:0] gmii_d;`
117			`wire gmii_en;`
118			`reg gmii_en_d;`
119			`reg gmii_err_d;`
120
121			`reg gmii_10_100_en_d;`
122			`reg gmii_10_100_err_d;`
123
124
125			`wire gmii_er;`
126			`wire sop_gen; // pulse with first character`
127			`wire eop_gen; // pulse with last character`
128			`wire done_gen;`
129			`reg eop_int; // pulse with last character`
130			`reg sop_m;`
131			`reg eop_m;`
132			`reg [1:0] start_gen;`
133			`reg clk_div2;`
134			`wire [3:0] nib1;`
135			`reg rgmii_en_er;`
136			`reg rgmii_10_100_en_er;`
137			`reg rgmii_10_100_en_er_d;`
138			`reg rgmii_10_100_en_er_d2;`
139			`reg rgmii_en_er_f;`
140			`reg rgmii_10_100_en_er_f;`
141			`reg [3:0] rgmii_dat;`
142			`reg [3:0] rgmii_dat_f; // save upper nibble for falling edge`
143			`reg mii_en;`
144			`reg mii_er;`
145			`wire [3:0] mii_dat;`
146			`// divide clock for nibble transfers 8-bit pathes`
147
148			`initial`
149			`begin`
150			`clk_div2 <= 1'b 0;`
151			`start_gen <= 2'b 00;`
152			`end`
153
154			`always @(posedge reset or posedge rx_clk)`
155			`begin : process_1`
156			`if (reset == 1'b 1)`
157			`begin`
158			`clk_div2 <= 1'b 0;`
159			`start_gen <= 2'b 00;`
160			`end`
161			`else`
162			`begin`
163			`clk_div2 <= ~clk_div2;`
164			`if (start == 1'b 1)`
165			`begin`
166			`start_gen <= {2{1'b 1}};`
167			`end`
168			`else`
169			`begin`
170			`start_gen[1:0] <= {1'b 0, start_gen[1]}; // make it longer for MII mode`
171			`end`
172			`end`
173			`end`
174			`// multiplex GMII into RGMII/MII`
175			`initial`
176			`begin`
177			`rgmii_en_er <= 1'b 0;`
178			`rgmii_en_er_f <= 1'b 0;`
179			`rgmii_dat <= {4{1'b 0}};`
180			`rgmii_dat_f <= {4{1'b 0}};`
181			`sop_m <= 1'b 0;`
182			`eop_m <= 1'b 0;`
183			`gmii_en_d <= 1'b 0;`
184			`gmii_err_d <= 1'b 0;`
185			`mii_en <= 1'b 0;`
186			`mii_er <= 1'b 0;`
187			`end`
188
189			`always @(posedge reset or gmii_clk)`
190			`begin : process_2`
191			`if (reset == 1'b 1)`
192			`begin`
193			`rgmii_en_er <= 1'b 0;`
194			`rgmii_en_er_f <= 1'b 0;`
195			`rgmii_dat <= {4{1'b 0}};`
196			`rgmii_dat_f <= {4{1'b 0}};`
197			`sop_m <= 1'b 0;`
198			`eop_m <= 1'b 0;`
199			`gmii_en_d <= 1'b 0;`
200			`gmii_err_d<= 1'b 0;`
201			`end`
202			`else`
203			`begin`
204			`// DDR`
205			`if (gmii_clk == 1'b 1)`
206			`begin`
207			`gmii_en_d <= gmii_en;`
208			`done <= done_gen & ~gmii_en;`
209			`// FIFO signaling in right clock edge`
210			`sop_m <= sop_gen;`
211			`eop_int <= eop_gen;`
212			`if (mii_mode == 1'b 1 \| rgmii_mode == 1'b1 & ethernet_speed == 1'b0)`
213			`begin`
214			`// not in MII, then EOP is 1 clock cycle already`
215			`eop_m <= 1'b 0;`
216			`end`
217			`else`
218			`begin`
219			`eop_m <= eop_gen;`
220			`end`
221			`// Data and Control`
222			`rgmii_dat <= #(thold) gmii_d[3:0];`
223			`rgmii_dat_f <= gmii_d[7:4];`
224
225			`rgmii_en_er <= #(thold) gmii_en;`
226			`rgmii_en_er_f <= #(thold) gmii_er;`
227
228			`mii_en <= #(thold) gmii_en;`
229			`mii_er <= #(thold) gmii_er;`
230			`end`
231			`else`
232			`begin`
233			`rgmii_en_er <= #(thold) rgmii_en_er_f ^ gmii_en_d;`
234			`rgmii_dat <= #(thold) rgmii_dat_f; // produce upper nibble`
235
236
237			`if (mii_mode == 1'b 1 \| rgmii_mode == 1'b1 & ethernet_speed == 1'b0)`
238			`begin`
239			`sop_m <= 1'b 0;`
240			`eop_m <= eop_int;`
241			`end`
242			`end`
243			`end`
244			`end`
245
246
247			`// multiplex GMII into RGMII/MII`
248			`initial`
249			`begin`
250			`rgmii_10_100_en_er <= 1'b 0;`
251			`rgmii_10_100_en_er_f <= 1'b 0;`
252			`gmii_10_100_en_d <= 1'b 0;`
253			`gmii_10_100_err_d<= 1'b 0;`
254			`rgmii_10_100_en_er_d <= 1'b0;`
255			`rgmii_10_100_en_er_d2 <= 1'b0;`
256			`end`
257
258			`always @(posedge reset or rx_clk)`
259			`begin`
260			`if (reset == 1'b 1)`
261			`begin`
262			`rgmii_10_100_en_er <= 1'b 0;`
263			`rgmii_10_100_en_er_f <= 1'b 0;`
264			`gmii_10_100_en_d <= 1'b 0;`
265			`gmii_10_100_err_d<= 1'b 0;`
266			`rgmii_10_100_en_er_d <= 1'b0;`
267			`rgmii_10_100_en_er_d2 <= 1'b0;`
268
269			`end`
270			`else`
271			`begin`
272			`// DDR`
273			`if (rx_clk == 1'b 1)`
274			`begin`
275			`gmii_10_100_en_d <= gmii_en;`
276			`rgmii_10_100_en_er <= #(thold) gmii_en;`
277			`rgmii_10_100_en_er_f <= #(thold) gmii_er;`
278			`rgmii_10_100_en_er_d <= rgmii_10_100_en_er;`
279			`rgmii_10_100_en_er_d2 <= rgmii_10_100_en_er_d;`
280
281			`end`
282			`else`
283			`begin`
284			`rgmii_10_100_en_er <= #(thold) rgmii_10_100_en_er_f ^ gmii_10_100_en_d;`
285			`rgmii_10_100_en_er_d <= rgmii_10_100_en_er;`
286			`rgmii_10_100_en_er_d2 <= rgmii_10_100_en_er_d;`
287			`end`
288			`end`
289			`end`
290
291
292
293
294
295			`// connect clock`
296
297
298			`always @ (*)`
299
300			`begin`
301			`if (ethernet_speed == 1'b 0)`
302			`begin`
303			`if (rgmii_mode == 1'b1\|mii_mode == 1'b1)`
304			`gmii_clk <= clk_div2;`
305			`end`
306			`else`
307			`begin`
308			`gmii_clk <= rx_clk;`
309			`end`
310
311			`end`
312
313
314			`// connect output ports`
315			`assign rxd[7:4] = rgmii_mode == 1'b 1 \| mii_mode == 1'b 1 \|`
316			`reset == 1'b 1 ? 4'b 0000 :`
317			`gmii_d[7:4];`
318			`assign rxd[3:0] = rgmii_mode == 1'b 1 \| mii_mode == 1'b 1 \| reset == 1'b 1 ? rgmii_dat : gmii_d[3:0];`
319			`assign rx_dv = reset == 1'b 1 ? 1'b 0 :`
320			`rgmii_mode == 1'b 1 ? (ethernet_speed == 1'b1) ? rgmii_en_er: rgmii_10_100_en_er_d2 :`
321			`mii_mode == 1'b 1 ? mii_en :`
322			`gmii_en;`
323			`assign rx_er = reset == 1'b 1 ? 1'b 0 :`
324			`rgmii_mode == 1'b 1 ? 1'b 0 :`
325			`mii_mode == 1'b 1 ? mii_er :`
326			`gmii_er;`
327			`assign #(thold) sop = rgmii_mode == 1'b 1 \| mii_mode == 1'b 1 ? sop_m :`
328			`sop_gen;`
329			`assign #(thold) eop = rgmii_mode == 1'b 1 \| mii_mode == 1'b 1 ? eop_m :`
330			`eop_gen;`
331
332			`ethgenerator #(2) gmii_gen (.reset(reset),`
333			`// active high`
334			`.rx_clk(gmii_clk),`
335			`.enable(1'b1),`
336			`.rxd(gmii_d),`
337			`.rx_dv(gmii_en),`
338			`.rx_er(gmii_er),`
339			`.sop(sop_gen),`
340			`.eop(eop_gen),`
341			`.mac_reverse(mac_reverse),`
342			`.dst(dst),`
343			`.src(src),`
344			`.prmble_len(prmble_len),`
345			`.pquant(pquant),`
346			`.vlan_ctl(vlan_ctl),`
347			`.len(len),`
348			`.frmtype(frmtype),`
349			`.cntstart(cntstart),`
350			`.cntstep(cntstep),`
351			`.ipg_len(ipg_len),`
352			`.payload_err(payload_err),`
353			`.prmbl_err(prmbl_err),`
354			`.crc_err(crc_err),`
355			`.vlan_en(vlan_en),`
356			`.stack_vlan(stack_vlan),`
357			`.pause_gen(pause_gen),`
358			`.pad_en(pad_en),`
359			`.phy_err(phy_err),`
360			`.end_err(end_err),`
361			`.data_only(data_only),`
362			`.runt_gen(1'b0) ,`
363			`.long_pause(1'b0) ,`
364			`.carrier_sense(carrier_sense),`
365			`.false_carrier(false_carrier),`
366			`.carrier_extend(carrier_extend),`
367			`.carrier_extend_error(carrier_extend_error),`
368			`.start(start_gen[0]),`
369			`.done(done_gen));`
370			`// GMII Generator`
371			`// --------------`
372
373			`endmodule // module ethgenerator2`
374