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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: ethgen32.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/ethgen32.v,v $
//
// $Revision: #1 $
// $Date: 2012/06/21 $
// Check in by : $Author: swbranch $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// Ethernet Traffic Generator for 32 bit MAC Atlantic client interface
// Instantiated in top_ethgenerator32 (top_ethgen32.v)
//
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
 
`timescale 1 ns / 10 ps // timescale for following modules
 
module ethgenerator32 (reset,
   rx_clk,
   rxd,
   rx_dv,
   rx_er,
   sop,
   eop,
   mac_reverse,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   cntstart,
   cntstep,
   ipg_len,
   payload_err,
   prmbl_err,
   crc_err,
   vlan_en,
   stack_vlan,
   pause_gen,
   pad_en,
   phy_err,
   end_err,
   data_only,
   start,
   done);
parameter thold = 1'b 1;
parameter ENABLE_SHIFT16 = 1'b 0;
 
input   reset; //  active high
input   rx_clk;
output   [7:0] rxd;
output   rx_dv;
output   rx_er;
output   sop; //  pulse with first character
output   eop; //  pulse with last  character
input   mac_reverse; //  1: dst/src are sent MSB first
input   [47:0] dst; //  destination address
input   [47:0] src; //  source address
input   [3:0] prmble_len; //  length of preamble
input   [15:0] pquant; //  Pause Quanta value
input   [15:0] vlan_ctl; //  VLAN control info
input   [15:0] len; //  Length of payload
input   [15:0] frmtype; //  if non-null: type field instead length
input   [7:0] cntstart; //  payload data counter start (first byte of payload)
input   [7:0] cntstep; //  payload counter step (2nd byte in paylaod)
input   [15:0] ipg_len; //  inter packet gap (delay after CRC)  
input   payload_err; //  generate payload pattern error (last payload byte is wrong)
input   prmbl_err;
input   crc_err;
input   vlan_en;
input   stack_vlan;
input   pause_gen;
input   pad_en;
input   phy_err;
input   end_err; //  keep rx_dv high one cycle after end of frame
input   data_only; //  if set omits preamble, padding, CRC
input   start;
output   done;
//  GMII receive interface: To be connected to MAC RX
reg     [7:0] rxd;
reg     rx_dv;
//  Additional FIFO controls for FIFO test scenarios
reg     rx_er;
reg     sop;
//  Frame Contents definitions
reg     eop;
reg     done;
reg     imac_reverse; //  1: dst/src are sent MSB first
reg     [47:0] idst; //  destination address
reg     [47:0] isrc; //  source address
reg     [3:0] iprmble_len; //  length of preamble
reg     [15:0] ipquant; //  Pause Quanta value
reg     [15:0] ivlan_ctl; //  VLAN control info
reg     [15:0] ilen; //  Length of payload
reg     [15:0] ifrmtype; //  if non-null: type field instead length
reg     [7:0] icntstart; //  payload data counter start (first byte of payload)
reg     [7:0] icntstep; //  payload counter step (2nd byte in paylaod)
reg     [15:0] iipg_len; //  inter packet gap
reg     ipayload_err;
reg     iprmbl_err;
reg     icrc_err;
reg     ivlan_en;
reg     istack_vlan;
reg     ipause_gen;
reg     ipad_en;
reg     iphy_err;
reg     iend_err;
reg     idata_only;
//  internal
 
// TYPE state_typ:
parameter state_typ_s_idle = 0;
parameter state_typ_s_prmbl = 1;
parameter state_typ_s_sfd = 2;
parameter state_typ_s_dst = 3;
parameter state_typ_s_src = 4;
parameter state_typ_s_pause = 5;
parameter state_typ_s_tag = 6;
parameter state_typ_s_len = 7;
parameter state_typ_s_data = 8;
parameter state_typ_s_pad = 9;
parameter state_typ_s_crc = 10;
parameter state_typ_s_enderr = 11;
parameter state_typ_s_ipg = 12;
parameter state_typ_s_stack = 13;
parameter state_typ_s_Dword32Aligned = 14;
 
 
reg     [3:0] state;
reg     [3:0] last_state;
reg     [3:0] last_state_dly; //  delayed one again
reg     [31:0] crc32;
reg     [31:0] count;
reg     [31:0] poscnt; //  position in frame starts at first dst byte
reg     [7:0] datacnt;
reg     [7:0] rxdata; //  next data to put on the line
reg     sop_int;
//  -----------------------------------
//  capture command when start asserted
//  -----------------------------------
reg     [31:0]  process_2_crctmp;
reg     [3:0]  V2V_process_2_i;
integer  process_7_hi;
integer  process_7_lo;
reg     [31:0]  process_7_cnttmp;
integer  V2V_process_7_i;
 
always @(posedge rx_clk or posedge reset)
   begin : process_1
   if (reset == 1'b 1)
      begin
      imac_reverse <= 1'b 0;    //  1: dst/src are sent MSB first
      idst <= {48{1'b 0}};  //  destination address
      isrc <= {48{1'b 0}};  //  source address
      iprmble_len <= 0; //  length of preamble
      ipquant <= {16{1'b 0}};   //  Pause Quanta value
      ivlan_ctl <= {16{1'b 0}}; //  VLAN control info
      ilen <= {16{1'b 0}};  //  Length of payload
      ifrmtype <= {16{1'b 0}};  //  if non-null: type field instead length
      icntstart <= 0;   //  payload data counter start (first byte of payload)
      icntstep <= 0;    //  payload counter step (2nd byte in paylaod)
      iipg_len <= 0;
      ipayload_err <= 1'b 0;
      iprmbl_err <= 1'b 0;
      icrc_err <= 1'b 0;
      ivlan_en <= 1'b 0;
      istack_vlan <= 1'b 0;
      ipause_gen <= 1'b 0;
      ipad_en <= 1'b 0;
      iphy_err <= 1'b 0;
      iend_err <= 1'b 0;
      idata_only <= 1'b 0;
      end
   else
      begin
      if (start == 1'b 1 & state == state_typ_s_idle)
         begin
         imac_reverse <= mac_reverse;   //  1: dst/src are sent MSB first
         idst <= dst;   //  destination address
         isrc <= src;   //  source address
         iprmble_len <= prmble_len; //  length of preamble
         ipquant <= pquant; //  Pause Quanta value
         ivlan_ctl <= vlan_ctl; //  VLAN control info
         ilen <= len;   //  Length of payload
         ifrmtype <= frmtype;   //  if non-null: type field instead length
         icntstart <= cntstart; //  payload data counter start (first byte of payload)
         icntstep <= cntstep;   //  payload counter step (2nd byte in paylaod)
         iipg_len <= ipg_len;
         ipayload_err <= payload_err;
         iprmbl_err <= prmbl_err;
         icrc_err <= crc_err;
         ivlan_en <= vlan_en;
         istack_vlan <= stack_vlan;
         ipause_gen <= pause_gen;
         ipad_en <= pad_en;
         iphy_err <= phy_err;
         iend_err <= end_err;
         idata_only <= data_only;
         end
      end
   end
//  ----------------------------------------------
//  CRC calculation over all bytes except preamble
//  ----------------------------------------------
always @(negedge rx_clk or posedge reset)
   begin : process_2
   if (reset == 1'b 1)
      begin
      crc32 <= {32{1'b 1}};
      end
   else
      begin
//  need it ahead
      if (last_state == state_typ_s_sfd)
         begin
         crc32 <= {32{1'b 1}};  //  RESET CRC at start of DST
         end
      else if (state != state_typ_s_idle & state != state_typ_s_prmbl &
    last_state != state_typ_s_crc )
         begin
         process_2_crctmp = crc32;
 
         for (V2V_process_2_i = 0; V2V_process_2_i <= 7; V2V_process_2_i = V2V_process_2_i + 1)
            begin
            if ((rxdata[V2V_process_2_i] ^ process_2_crctmp[31]) == 1'b 1)
               begin
               process_2_crctmp = (process_2_crctmp << 1);  //  shift in a 0, will be xor'ed to 1 by the polynom
               process_2_crctmp = process_2_crctmp ^ 32'h 04C11DB7;
               end
            else
               begin
               process_2_crctmp = (process_2_crctmp << 1);  //  shift in a 0
               end
            end
//  process all bits we have here
         crc32 <= process_2_crctmp;
         end
      end
   end
//  ----------------------------------------------
//  Push RX Data on GMII and 
//  produce PHY error if requested during SRC address transmission
//  ----------------------------------------------
always @(posedge rx_clk or posedge reset)
   begin : process_3
   if (reset == 1'b 1)
      begin
      rxd <= {8{1'b 0}};
      rx_dv <= 1'b 0;
      rx_er <= 1'b 0;
      end
   else
      begin
      if (last_state == state_typ_s_idle | last_state == state_typ_s_ipg)
         begin
         rxd <= #(thold) {8{1'b 0}};
         rx_dv <= #(thold) 1'b 0;
//  Data and DV 
         end
      else
         begin
         rxd <= #(thold) rxdata;
         rx_dv <= #(thold) 1'b 1;
//  PHY error in SRC field
         if (last_state == state_typ_s_src & count == 2 &
    iphy_err == 1'b 1)
            begin
            rx_er <= #(thold) 1'b 1;
            end
         else
            begin
            rx_er <= #(thold) 1'b 0;
            end
         end
      end
   end
//  ----------------------------------------------
//  SOP and EOP generation (helper for FIFO testing)
//  ----------------------------------------------
always @(posedge rx_clk or posedge reset)
   begin : process_4
   if (reset == 1'b 1)
      begin
      sop <= 1'b 0;
      sop_int <= 1'b 0;
      eop <= 1'b 0;
      end
   else
      begin
      if (last_state == state_typ_s_idle & state != state_typ_s_idle)
         begin
         sop_int <= 1'b 1;
         end
      else
         begin
         sop_int <= 1'b 0;
         end
      if (last_state != state_typ_s_idle & state == state_typ_s_idle |
    last_state != state_typ_s_ipg & state == state_typ_s_ipg)
         begin
         if (~(last_state == state_typ_s_ipg & state == state_typ_s_idle))
            begin
//  if from ipg to idle, eop has been pulsed already
            eop <= #(thold) 1'b 1;
            end
         end
      else
         begin
         eop <= #(thold) 1'b 0;
         end
      sop <= #(thold) sop_int;  //  need 1 delay
      end
   end
//  ----------------------------------------------
//  Position Counter: Starts with first octet of destination address
//  ----------------------------------------------
always @(posedge rx_clk or posedge reset)
   begin : process_5
   if (reset == 1'b 1)
      begin
      poscnt <= 0;
      end
   else
      begin
      if (state == state_typ_s_sfd | state == state_typ_s_idle &
    start == 1'b 1)
         begin
//  in the data_only case necessary
         poscnt <= 0;   //  is 1 with the first byte sent (prmbl or DST)
         end
      else
         begin
         if (poscnt < 65535)
            begin
            poscnt <= poscnt + 1'b 1;
            end
         end
      end
   end
//  ----------------------------------------------
//  Done indication
//  ----------------------------------------------
always @(posedge rx_clk or posedge reset)
   begin : process_6
   if (reset == 1'b 1)
      begin
      done <= 1'b 1;
      end
   else
      begin
      if (state == state_typ_s_idle)
         begin
         done <= ~start;
         end
      else
         begin
         done <= 1'b 0;
         end
      end
   end
//  ----------------------------------------------
//  Generator State Machine
//  ----------------------------------------------
always @(posedge rx_clk or posedge reset)
   begin : process_7
   if (reset == 1'b 1)
      begin
      state <= state_typ_s_idle;
      last_state <= state_typ_s_idle;
      rxdata <= {8{1'b X}};
      count <= 0;
      end
   else
      begin
//  remember last state and increment internal counter
      last_state <= state;
      last_state_dly <= last_state; //  for viewing only
      if (count < 65535)
         begin
         process_7_cnttmp = count + 1'b 1;
         end
      else
         begin
         process_7_cnttmp = count;
         end
      case (state)
      state_typ_s_idle:
         begin
         if (start == 1'b 1)
            begin
            if (data_only == 1'b 1)
               begin
//  data only then skip preamble
               if (ENABLE_SHIFT16 == 1'b0)
               state <= state_typ_s_dst;
               else
                state <= state_typ_s_Dword32Aligned;
 
               process_7_cnttmp = 1'b 0;
               end
            else
               begin
               state <= state_typ_s_prmbl;
               process_7_cnttmp = 1'b 1;
               end
            end
         rxdata <= {8{1'b X}};
         end
      state_typ_s_prmbl:
         begin
         if (iprmble_len <= process_7_cnttmp)
            begin
//  one earlier
            state <= state_typ_s_sfd;
            end
         rxdata <= 8'h 55;
         end
      state_typ_s_sfd:
         begin
         state <= state_typ_s_dst;
         process_7_cnttmp = 1'b 0;
         if (iprmbl_err == 1'b 1)
            begin
            rxdata <= 8'h F5;   //  preamble error
            end
         else
            begin
            rxdata <= 8'h D5;
            end
         end
 
     state_typ_s_Dword32Aligned:
        begin
        if (count == 1)
           begin
           state <= state_typ_s_dst;
           process_7_cnttmp = 1'b 0;
           end
        case (count)
            1'b 0:
               begin
               rxdata[7:0] <= 8'h 00;
               end
            1'b 1:
               begin
               rxdata[7:0] <= 8'h 00;
               end
            default:
               ;
        endcase
        end
 
      state_typ_s_dst:
         begin
         if (count == 5)
            begin
            state <= state_typ_s_src;
            process_7_cnttmp = 1'b 0;
            end
         case (count)
         1'b 0:
            begin
            rxdata[7:0] <= idst[7:0];
            end
         1'b 1:
            begin
            rxdata[7:0] <= idst[15:8];
            end
         2'b 10:
            begin
            rxdata[7:0] <= idst[23:16];
            end
         2'b 11:
            begin
            rxdata[7:0] <= idst[31:24];
            end
         3'b 100:
            begin
            rxdata[7:0] <= idst[39:32];
            end
         3'b 101:
            begin
            rxdata[7:0] <= idst[47:40];
            end
         default:
            ;
         endcase
         end
      state_typ_s_src:
         begin
         if (count == 5)
            begin
            if (ipause_gen == 1'b 1)
               begin
               state <= state_typ_s_pause;  // if( mac_reverse='1' ) then
// hi := 47-(count*8);
// lo := 40-(count*8);
// else 
// hi := (count*8)+7;
// lo := (count*8);
// end if;
// rxdata(7 downto 0) <= idst(hi downto lo);
               end
            else if (ivlan_en == 1'b 1 )
               begin
               state <= state_typ_s_tag;    //  VLAN follows
               end
            else
               begin
               state <= state_typ_s_len;    //  normal frame
               end
            process_7_cnttmp = 1'b 0;
            end
// if( mac_reverse='1' ) then
         case (count)
         1'b 0:
            begin
            rxdata[7:0] <= isrc[7:0];
            end
         1'b 1:
            begin
            rxdata[7:0] <= isrc[15:8];
            end
         2'b 10:
            begin
            rxdata[7:0] <= isrc[23:16];
            end
         2'b 11:
            begin
            rxdata[7:0] <= isrc[31:24];
            end
         3'b 100:
            begin
            rxdata[7:0] <= isrc[39:32];
            end
         3'b 101:
            begin
            rxdata[7:0] <= isrc[47:40];
            end
         default:
            ;
         endcase
         end
      state_typ_s_pause:
         begin
         if (count == 0)
            begin
            rxdata <= 8'h 88;   // hi := 47-(count*8);
// lo := 40-(count*8);
// else 
// hi := (count*8)+7;
// lo := (count*8);
// end if;
// rxdata(7 downto 0) <= isrc(hi downto lo);
            end
         else if (count == 1 )
            begin
            rxdata <= 8'h 08;
            end
         else if (count == 2 )
            begin
            rxdata <= 8'h 00;
            end
         else if (count == 3 )
            begin
            rxdata <= 8'h 01;
            end
         else if (count == 4 )
            begin
            rxdata <= pquant[15:8];
            end
         else if (count == 5 )
            begin
            rxdata <= pquant[7:0];
            if (ipad_en == 1'b 1)
               begin
               state <= state_typ_s_pad;
               end
            else
               begin
               state <= state_typ_s_crc;    //  error non-padded pause frame
               end
            process_7_cnttmp = 1'b 0;
            end
         end
      state_typ_s_tag:
         begin
         if (count == 0)
            begin
            rxdata <= 8'h 81;
            end
         else if (count == 1 )
            begin
            rxdata <= 8'h 00;
            end
         else if (count == 2 )
            begin
            rxdata <= ivlan_ctl[15:8];
            end
         else if (count == 3 )
            begin
 
                if (istack_vlan==1'b0)
                begin
 
                        rxdata <= ivlan_ctl[7:0];
                        state  <= state_typ_s_len;
                        process_7_cnttmp = 1'b 0;
                end
                else
                begin
 
                        rxdata <= ivlan_ctl[7:0];
                        state  <= state_typ_s_stack;
                        process_7_cnttmp = 1'b 0;
 
                end
            end
         end
      state_typ_s_stack:
         begin
         if (count == 0)
            begin
            rxdata <= 8'h 81;
            end
         else if (count == 1 )
            begin
            rxdata <= 8'h 00;
            end
         else if (count == 2 )
            begin
            rxdata <= ivlan_ctl[15:8];
            end
         else if (count == 3 )
            begin
 
                rxdata <= ivlan_ctl[7:0];
                state  <= state_typ_s_len;
                process_7_cnttmp = 1'b 0;
 
            end
         end
      state_typ_s_len:
         begin
         if (count == 0)
            begin
            if (ifrmtype != 0)
               begin
               rxdata <= ifrmtype[15:8];
               end
            else
               begin
               rxdata <= ilen[15:8];    //  MSB
               end
            end
         else if (count == 1 )
            begin
            if (ifrmtype != 0)
               begin
               rxdata <= ifrmtype[7:0];
               end
            else
               begin
               rxdata <= ilen[7:0]; //  LSB
               end
//  if zero length frame go directly to pad
            if (ilen == 0)
               begin
               if (idata_only == 1'b 1 & iend_err == 1'b 1)
                  begin
                  state <= state_typ_s_enderr;
                  end
               else if (idata_only == 1'b 1 )
                  begin
                  state <= state_typ_s_idle;    //  stop immediately
                  end
               else if (ipad_en == 1'b 1 )
                  begin
                  state <= state_typ_s_pad;
                  end
               else
                  begin
                  state <= state_typ_s_crc;
                  end
               end
            else
               begin
               state <= state_typ_s_data;
               end
            process_7_cnttmp = 1'b 0;
            end
         end
      state_typ_s_data:
         begin
         if (count == 0)
            begin
            rxdata <= icntstart;    //  first the init
            datacnt <= icntstart;
            end
         else if (count == 1 )
            begin
            rxdata <= icntstep; //  then the step
            end
         else
            begin
            rxdata <= datacnt;  //  then data
            datacnt <= (datacnt + icntstep) % 256;
            end
//  check end of payload
         if (count >= ilen - 1'b 1)
            begin
            if (idata_only == 1'b 1)
               begin
               if (iend_err == 1'b 1)
                  begin
                  state <= state_typ_s_enderr;
                  end
               else if (iipg_len != 0 )
                  begin
                  state <= state_typ_s_ipg;
                  process_7_cnttmp = 1'b 0;
                  end
               else
                  begin
                  state <= state_typ_s_idle;
                  end
               end
            else if (poscnt < 6'b 111100 - 1'b 1 & ipad_en ==
    1'b 1 )
               begin
//  need to pad ?
               state <= state_typ_s_pad;
               end
            else
               begin
               state <= state_typ_s_crc;
               process_7_cnttmp = 1'b 0;
               end
//  modify last data byte if payload error was requested
            if (ipayload_err == 1'b 1)
               begin
               rxdata <= rxdata;    //  just keep the old value signals error
               end
            end
         end
      state_typ_s_pad:
         begin
         rxdata <= {8{1'b 0}};  //  PAD BYTE
         if (poscnt >= 6'b 111100 - 1'b 1)
            begin
            state <= state_typ_s_crc;
            process_7_cnttmp = 1'b 0;
            end
         end
      state_typ_s_crc:
         begin
         process_7_hi = 5'b 11111 - count * 8;
//  send CRC inverted, MSB of most significant byte first
 
         for (V2V_process_7_i = 0; V2V_process_7_i <= 7; V2V_process_7_i = V2V_process_7_i + 1)
            begin
            rxdata[V2V_process_7_i] <= crc32[process_7_hi - V2V_process_7_i] ^ 1'b 1;   //  first LSB is CRC MSB
            end
         if (count == 2 & icrc_err == 1'b 1)
            begin
            rxdata <= rxdata ^ 8'h FF;  //  produce some wrong number
            end
         if (count == 3)
            begin
            if (iend_err == 1'b 1)
               begin
               state <= state_typ_s_enderr;
               end
            else if (iipg_len > 0 )
               begin
               state <= state_typ_s_ipg;
               process_7_cnttmp = 1'b 1;
               end
            else
               begin
               state <= state_typ_s_idle;
               end
            end
         end
      state_typ_s_enderr:
         begin
         if (iipg_len == 0)
            begin
//  delay dv going low by one cycle
            state <= state_typ_s_idle;
            end
         else
            begin
            state <= state_typ_s_ipg;
            process_7_cnttmp = 1'b 1;
            end
         end
      state_typ_s_ipg:
         begin
         if (count >= iipg_len)
            begin
//  wait after last
            state <= state_typ_s_idle;
            end
         end
      endcase
      count <= process_7_cnttmp;    //  load the counter with the new value                   
      end
   end
 
//  local copied (registered) commands 
//  ----------------------------------
 
endmodule // 
 

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [ethgen32.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: ethgen32.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/ethgen32.v,v $`
8			`//`
9			`// $Revision: #1 $`
10	20	jefflieu	`// $Date: 2012/06/21 $`
11			`// Check in by : $Author: swbranch $`
12	9	jefflieu	`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// Ethernet Traffic Generator for 32 bit MAC Atlantic client interface`
19			`// Instantiated in top_ethgenerator32 (top_ethgen32.v)`
20			`//`
21			`//`
22			`// ALTERA Confidential and Proprietary`
23			`// Copyright 2006 (c) Altera Corporation`
24			`// All rights reserved`
25			`//`
26			`// -------------------------------------------------------------------------`
27			`// -------------------------------------------------------------------------`
28
29
30			`timescale 1 ns / 10 ps // timescale for following modules
31
32			`module ethgenerator32 (reset,`
33			`rx_clk,`
34			`rxd,`
35			`rx_dv,`
36			`rx_er,`
37			`sop,`
38			`eop,`
39			`mac_reverse,`
40			`dst,`
41			`src,`
42			`prmble_len,`
43			`pquant,`
44			`vlan_ctl,`
45			`len,`
46			`frmtype,`
47			`cntstart,`
48			`cntstep,`
49			`ipg_len,`
50			`payload_err,`
51			`prmbl_err,`
52			`crc_err,`
53			`vlan_en,`
54			`stack_vlan,`
55			`pause_gen,`
56			`pad_en,`
57			`phy_err,`
58			`end_err,`
59			`data_only,`
60			`start,`
61			`done);`
62			`parameter thold = 1'b 1;`
63			`parameter ENABLE_SHIFT16 = 1'b 0;`
64
65			`input reset; // active high`
66			`input rx_clk;`
67			`output [7:0] rxd;`
68			`output rx_dv;`
69			`output rx_er;`
70			`output sop; // pulse with first character`
71			`output eop; // pulse with last character`
72			`input mac_reverse; // 1: dst/src are sent MSB first`
73			`input [47:0] dst; // destination address`
74			`input [47:0] src; // source address`
75			`input [3:0] prmble_len; // length of preamble`
76			`input [15:0] pquant; // Pause Quanta value`
77			`input [15:0] vlan_ctl; // VLAN control info`
78			`input [15:0] len; // Length of payload`
79			`input [15:0] frmtype; // if non-null: type field instead length`
80			`input [7:0] cntstart; // payload data counter start (first byte of payload)`
81			`input [7:0] cntstep; // payload counter step (2nd byte in paylaod)`
82			`input [15:0] ipg_len; // inter packet gap (delay after CRC)`
83			`input payload_err; // generate payload pattern error (last payload byte is wrong)`
84			`input prmbl_err;`
85			`input crc_err;`
86			`input vlan_en;`
87			`input stack_vlan;`
88			`input pause_gen;`
89			`input pad_en;`
90			`input phy_err;`
91			`input end_err; // keep rx_dv high one cycle after end of frame`
92			`input data_only; // if set omits preamble, padding, CRC`
93			`input start;`
94			`output done;`
95			`// GMII receive interface: To be connected to MAC RX`
96			`reg [7:0] rxd;`
97			`reg rx_dv;`
98			`// Additional FIFO controls for FIFO test scenarios`
99			`reg rx_er;`
100			`reg sop;`
101			`// Frame Contents definitions`
102			`reg eop;`
103			`reg done;`
104			`reg imac_reverse; // 1: dst/src are sent MSB first`
105			`reg [47:0] idst; // destination address`
106			`reg [47:0] isrc; // source address`
107			`reg [3:0] iprmble_len; // length of preamble`
108			`reg [15:0] ipquant; // Pause Quanta value`
109			`reg [15:0] ivlan_ctl; // VLAN control info`
110			`reg [15:0] ilen; // Length of payload`
111			`reg [15:0] ifrmtype; // if non-null: type field instead length`
112			`reg [7:0] icntstart; // payload data counter start (first byte of payload)`
113			`reg [7:0] icntstep; // payload counter step (2nd byte in paylaod)`
114			`reg [15:0] iipg_len; // inter packet gap`
115			`reg ipayload_err;`
116			`reg iprmbl_err;`
117			`reg icrc_err;`
118			`reg ivlan_en;`
119			`reg istack_vlan;`
120			`reg ipause_gen;`
121			`reg ipad_en;`
122			`reg iphy_err;`
123			`reg iend_err;`
124			`reg idata_only;`
125			`// internal`
126
127			`// TYPE state_typ:`
128			`parameter state_typ_s_idle = 0;`
129			`parameter state_typ_s_prmbl = 1;`
130			`parameter state_typ_s_sfd = 2;`
131			`parameter state_typ_s_dst = 3;`
132			`parameter state_typ_s_src = 4;`
133			`parameter state_typ_s_pause = 5;`
134			`parameter state_typ_s_tag = 6;`
135			`parameter state_typ_s_len = 7;`
136			`parameter state_typ_s_data = 8;`
137			`parameter state_typ_s_pad = 9;`
138			`parameter state_typ_s_crc = 10;`
139			`parameter state_typ_s_enderr = 11;`
140			`parameter state_typ_s_ipg = 12;`
141			`parameter state_typ_s_stack = 13;`
142			`parameter state_typ_s_Dword32Aligned = 14;`
143
144
145			`reg [3:0] state;`
146			`reg [3:0] last_state;`
147			`reg [3:0] last_state_dly; // delayed one again`
148			`reg [31:0] crc32;`
149			`reg [31:0] count;`
150			`reg [31:0] poscnt; // position in frame starts at first dst byte`
151			`reg [7:0] datacnt;`
152			`reg [7:0] rxdata; // next data to put on the line`
153			`reg sop_int;`
154			`// -----------------------------------`
155			`// capture command when start asserted`
156			`// -----------------------------------`
157			`reg [31:0] process_2_crctmp;`
158			`reg [3:0] V2V_process_2_i;`
159			`integer process_7_hi;`
160			`integer process_7_lo;`
161			`reg [31:0] process_7_cnttmp;`
162			`integer V2V_process_7_i;`
163
164			`always @(posedge rx_clk or posedge reset)`
165			`begin : process_1`
166			`if (reset == 1'b 1)`
167			`begin`
168			`imac_reverse <= 1'b 0; // 1: dst/src are sent MSB first`
169			`idst <= {48{1'b 0}}; // destination address`
170			`isrc <= {48{1'b 0}}; // source address`
171			`iprmble_len <= 0; // length of preamble`
172			`ipquant <= {16{1'b 0}}; // Pause Quanta value`
173			`ivlan_ctl <= {16{1'b 0}}; // VLAN control info`
174			`ilen <= {16{1'b 0}}; // Length of payload`
175			`ifrmtype <= {16{1'b 0}}; // if non-null: type field instead length`
176			`icntstart <= 0; // payload data counter start (first byte of payload)`
177			`icntstep <= 0; // payload counter step (2nd byte in paylaod)`
178			`iipg_len <= 0;`
179			`ipayload_err <= 1'b 0;`
180			`iprmbl_err <= 1'b 0;`
181			`icrc_err <= 1'b 0;`
182			`ivlan_en <= 1'b 0;`
183			`istack_vlan <= 1'b 0;`
184			`ipause_gen <= 1'b 0;`
185			`ipad_en <= 1'b 0;`
186			`iphy_err <= 1'b 0;`
187			`iend_err <= 1'b 0;`
188			`idata_only <= 1'b 0;`
189			`end`
190			`else`
191			`begin`
192			`if (start == 1'b 1 & state == state_typ_s_idle)`
193			`begin`
194			`imac_reverse <= mac_reverse; // 1: dst/src are sent MSB first`
195			`idst <= dst; // destination address`
196			`isrc <= src; // source address`
197			`iprmble_len <= prmble_len; // length of preamble`
198			`ipquant <= pquant; // Pause Quanta value`
199			`ivlan_ctl <= vlan_ctl; // VLAN control info`
200			`ilen <= len; // Length of payload`
201			`ifrmtype <= frmtype; // if non-null: type field instead length`
202			`icntstart <= cntstart; // payload data counter start (first byte of payload)`
203			`icntstep <= cntstep; // payload counter step (2nd byte in paylaod)`
204			`iipg_len <= ipg_len;`
205			`ipayload_err <= payload_err;`
206			`iprmbl_err <= prmbl_err;`
207			`icrc_err <= crc_err;`
208			`ivlan_en <= vlan_en;`
209			`istack_vlan <= stack_vlan;`
210			`ipause_gen <= pause_gen;`
211			`ipad_en <= pad_en;`
212			`iphy_err <= phy_err;`
213			`iend_err <= end_err;`
214			`idata_only <= data_only;`
215			`end`
216			`end`
217			`end`
218			`// ----------------------------------------------`
219			`// CRC calculation over all bytes except preamble`
220			`// ----------------------------------------------`
221			`always @(negedge rx_clk or posedge reset)`
222			`begin : process_2`
223			`if (reset == 1'b 1)`
224			`begin`
225			`crc32 <= {32{1'b 1}};`
226			`end`
227			`else`
228			`begin`
229			`// need it ahead`
230			`if (last_state == state_typ_s_sfd)`
231			`begin`
232			`crc32 <= {32{1'b 1}}; // RESET CRC at start of DST`
233			`end`
234			`else if (state != state_typ_s_idle & state != state_typ_s_prmbl &`
235			`last_state != state_typ_s_crc )`
236			`begin`
237			`process_2_crctmp = crc32;`
238
239			`for (V2V_process_2_i = 0; V2V_process_2_i <= 7; V2V_process_2_i = V2V_process_2_i + 1)`
240			`begin`
241			`if ((rxdata[V2V_process_2_i] ^ process_2_crctmp[31]) == 1'b 1)`
242			`begin`
243			`process_2_crctmp = (process_2_crctmp << 1); // shift in a 0, will be xor'ed to 1 by the polynom`
244			`process_2_crctmp = process_2_crctmp ^ 32'h 04C11DB7;`
245			`end`
246			`else`
247			`begin`
248			`process_2_crctmp = (process_2_crctmp << 1); // shift in a 0`
249			`end`
250			`end`
251			`// process all bits we have here`
252			`crc32 <= process_2_crctmp;`
253			`end`
254			`end`
255			`end`
256			`// ----------------------------------------------`
257			`// Push RX Data on GMII and`
258			`// produce PHY error if requested during SRC address transmission`
259			`// ----------------------------------------------`
260			`always @(posedge rx_clk or posedge reset)`
261			`begin : process_3`
262			`if (reset == 1'b 1)`
263			`begin`
264			`rxd <= {8{1'b 0}};`
265			`rx_dv <= 1'b 0;`
266			`rx_er <= 1'b 0;`
267			`end`
268			`else`
269			`begin`
270			`if (last_state == state_typ_s_idle \| last_state == state_typ_s_ipg)`
271			`begin`
272			`rxd <= #(thold) {8{1'b 0}};`
273			`rx_dv <= #(thold) 1'b 0;`
274			`// Data and DV`
275			`end`
276			`else`
277			`begin`
278			`rxd <= #(thold) rxdata;`
279			`rx_dv <= #(thold) 1'b 1;`
280			`// PHY error in SRC field`
281			`if (last_state == state_typ_s_src & count == 2 &`
282			`iphy_err == 1'b 1)`
283			`begin`
284			`rx_er <= #(thold) 1'b 1;`
285			`end`
286			`else`
287			`begin`
288			`rx_er <= #(thold) 1'b 0;`
289			`end`
290			`end`
291			`end`
292			`end`
293			`// ----------------------------------------------`
294			`// SOP and EOP generation (helper for FIFO testing)`
295			`// ----------------------------------------------`
296			`always @(posedge rx_clk or posedge reset)`
297			`begin : process_4`
298			`if (reset == 1'b 1)`
299			`begin`
300			`sop <= 1'b 0;`
301			`sop_int <= 1'b 0;`
302			`eop <= 1'b 0;`
303			`end`
304			`else`
305			`begin`
306			`if (last_state == state_typ_s_idle & state != state_typ_s_idle)`
307			`begin`
308			`sop_int <= 1'b 1;`
309			`end`
310			`else`
311			`begin`
312			`sop_int <= 1'b 0;`
313			`end`
314			`if (last_state != state_typ_s_idle & state == state_typ_s_idle \|`
315			`last_state != state_typ_s_ipg & state == state_typ_s_ipg)`
316			`begin`
317			`if (~(last_state == state_typ_s_ipg & state == state_typ_s_idle))`
318			`begin`
319			`// if from ipg to idle, eop has been pulsed already`
320			`eop <= #(thold) 1'b 1;`
321			`end`
322			`end`
323			`else`
324			`begin`
325			`eop <= #(thold) 1'b 0;`
326			`end`
327			`sop <= #(thold) sop_int; // need 1 delay`
328			`end`
329			`end`
330			`// ----------------------------------------------`
331			`// Position Counter: Starts with first octet of destination address`
332			`// ----------------------------------------------`
333			`always @(posedge rx_clk or posedge reset)`
334			`begin : process_5`
335			`if (reset == 1'b 1)`
336			`begin`
337			`poscnt <= 0;`
338			`end`
339			`else`
340			`begin`
341			`if (state == state_typ_s_sfd \| state == state_typ_s_idle &`
342			`start == 1'b 1)`
343			`begin`
344			`// in the data_only case necessary`
345			`poscnt <= 0; // is 1 with the first byte sent (prmbl or DST)`
346			`end`
347			`else`
348			`begin`
349			`if (poscnt < 65535)`
350			`begin`
351			`poscnt <= poscnt + 1'b 1;`
352			`end`
353			`end`
354			`end`
355			`end`
356			`// ----------------------------------------------`
357			`// Done indication`
358			`// ----------------------------------------------`
359			`always @(posedge rx_clk or posedge reset)`
360			`begin : process_6`
361			`if (reset == 1'b 1)`
362			`begin`
363			`done <= 1'b 1;`
364			`end`
365			`else`
366			`begin`
367			`if (state == state_typ_s_idle)`
368			`begin`
369			`done <= ~start;`
370			`end`
371			`else`
372			`begin`
373			`done <= 1'b 0;`
374			`end`
375			`end`
376			`end`
377			`// ----------------------------------------------`
378			`// Generator State Machine`
379			`// ----------------------------------------------`
380			`always @(posedge rx_clk or posedge reset)`
381			`begin : process_7`
382			`if (reset == 1'b 1)`
383			`begin`
384			`state <= state_typ_s_idle;`
385			`last_state <= state_typ_s_idle;`
386			`rxdata <= {8{1'b X}};`
387			`count <= 0;`
388			`end`
389			`else`
390			`begin`
391			`// remember last state and increment internal counter`
392			`last_state <= state;`
393			`last_state_dly <= last_state; // for viewing only`
394			`if (count < 65535)`
395			`begin`
396			`process_7_cnttmp = count + 1'b 1;`
397			`end`
398			`else`
399			`begin`
400			`process_7_cnttmp = count;`
401			`end`
402			`case (state)`
403			`state_typ_s_idle:`
404			`begin`
405			`if (start == 1'b 1)`
406			`begin`
407			`if (data_only == 1'b 1)`
408			`begin`
409			`// data only then skip preamble`
410			`if (ENABLE_SHIFT16 == 1'b0)`
411			`state <= state_typ_s_dst;`
412			`else`
413			`state <= state_typ_s_Dword32Aligned;`
414
415			`process_7_cnttmp = 1'b 0;`
416			`end`
417			`else`
418			`begin`
419			`state <= state_typ_s_prmbl;`
420			`process_7_cnttmp = 1'b 1;`
421			`end`
422			`end`
423			`rxdata <= {8{1'b X}};`
424			`end`
425			`state_typ_s_prmbl:`
426			`begin`
427			`if (iprmble_len <= process_7_cnttmp)`
428			`begin`
429			`// one earlier`
430			`state <= state_typ_s_sfd;`
431			`end`
432			`rxdata <= 8'h 55;`
433			`end`
434			`state_typ_s_sfd:`
435			`begin`
436			`state <= state_typ_s_dst;`
437			`process_7_cnttmp = 1'b 0;`
438			`if (iprmbl_err == 1'b 1)`
439			`begin`
440			`rxdata <= 8'h F5; // preamble error`
441			`end`
442			`else`
443			`begin`
444			`rxdata <= 8'h D5;`
445			`end`
446			`end`
447
448			`state_typ_s_Dword32Aligned:`
449			`begin`
450			`if (count == 1)`
451			`begin`
452			`state <= state_typ_s_dst;`
453			`process_7_cnttmp = 1'b 0;`
454			`end`
455			`case (count)`
456			`1'b 0:`
457			`begin`
458			`rxdata[7:0] <= 8'h 00;`
459			`end`
460			`1'b 1:`
461			`begin`
462			`rxdata[7:0] <= 8'h 00;`
463			`end`
464			`default:`
465			`;`
466			`endcase`
467			`end`
468
469			`state_typ_s_dst:`
470			`begin`
471			`if (count == 5)`
472			`begin`
473			`state <= state_typ_s_src;`
474			`process_7_cnttmp = 1'b 0;`
475			`end`
476			`case (count)`
477			`1'b 0:`
478			`begin`
479			`rxdata[7:0] <= idst[7:0];`
480			`end`
481			`1'b 1:`
482			`begin`
483			`rxdata[7:0] <= idst[15:8];`
484			`end`
485			`2'b 10:`
486			`begin`
487			`rxdata[7:0] <= idst[23:16];`
488			`end`
489			`2'b 11:`
490			`begin`
491			`rxdata[7:0] <= idst[31:24];`
492			`end`
493			`3'b 100:`
494			`begin`
495			`rxdata[7:0] <= idst[39:32];`
496			`end`
497			`3'b 101:`
498			`begin`
499			`rxdata[7:0] <= idst[47:40];`
500			`end`
501			`default:`
502			`;`
503			`endcase`
504			`end`
505			`state_typ_s_src:`
506			`begin`
507			`if (count == 5)`
508			`begin`
509			`if (ipause_gen == 1'b 1)`
510			`begin`
511			`state <= state_typ_s_pause; // if( mac_reverse='1' ) then`
512			`// hi := 47-(count*8);`
513			`// lo := 40-(count*8);`
514			`// else`
515			`// hi := (count*8)+7;`
516			`// lo := (count*8);`
517			`// end if;`
518			`// rxdata(7 downto 0) <= idst(hi downto lo);`
519			`end`
520			`else if (ivlan_en == 1'b 1 )`
521			`begin`
522			`state <= state_typ_s_tag; // VLAN follows`
523			`end`
524			`else`
525			`begin`
526			`state <= state_typ_s_len; // normal frame`
527			`end`
528			`process_7_cnttmp = 1'b 0;`
529			`end`
530			`// if( mac_reverse='1' ) then`
531			`case (count)`
532			`1'b 0:`
533			`begin`
534			`rxdata[7:0] <= isrc[7:0];`
535			`end`
536			`1'b 1:`
537			`begin`
538			`rxdata[7:0] <= isrc[15:8];`
539			`end`
540			`2'b 10:`
541			`begin`
542			`rxdata[7:0] <= isrc[23:16];`
543			`end`
544			`2'b 11:`
545			`begin`
546			`rxdata[7:0] <= isrc[31:24];`
547			`end`
548			`3'b 100:`
549			`begin`
550			`rxdata[7:0] <= isrc[39:32];`
551			`end`
552			`3'b 101:`
553			`begin`
554			`rxdata[7:0] <= isrc[47:40];`
555			`end`
556			`default:`
557			`;`
558			`endcase`
559			`end`
560			`state_typ_s_pause:`
561			`begin`
562			`if (count == 0)`
563			`begin`
564			`rxdata <= 8'h 88; // hi := 47-(count*8);`
565			`// lo := 40-(count*8);`
566			`// else`
567			`// hi := (count*8)+7;`
568			`// lo := (count*8);`
569			`// end if;`
570			`// rxdata(7 downto 0) <= isrc(hi downto lo);`
571			`end`
572			`else if (count == 1 )`
573			`begin`
574			`rxdata <= 8'h 08;`
575			`end`
576			`else if (count == 2 )`
577			`begin`
578			`rxdata <= 8'h 00;`
579			`end`
580			`else if (count == 3 )`
581			`begin`
582			`rxdata <= 8'h 01;`
583			`end`
584			`else if (count == 4 )`
585			`begin`
586			`rxdata <= pquant[15:8];`
587			`end`
588			`else if (count == 5 )`
589			`begin`
590			`rxdata <= pquant[7:0];`
591			`if (ipad_en == 1'b 1)`
592			`begin`
593			`state <= state_typ_s_pad;`
594			`end`
595			`else`
596			`begin`
597			`state <= state_typ_s_crc; // error non-padded pause frame`
598			`end`
599			`process_7_cnttmp = 1'b 0;`
600			`end`
601			`end`
602			`state_typ_s_tag:`
603			`begin`
604			`if (count == 0)`
605			`begin`
606			`rxdata <= 8'h 81;`
607			`end`
608			`else if (count == 1 )`
609			`begin`
610			`rxdata <= 8'h 00;`
611			`end`
612			`else if (count == 2 )`
613			`begin`
614			`rxdata <= ivlan_ctl[15:8];`
615			`end`
616			`else if (count == 3 )`
617			`begin`
618
619			`if (istack_vlan==1'b0)`
620			`begin`
621
622			`rxdata <= ivlan_ctl[7:0];`
623			`state <= state_typ_s_len;`
624			`process_7_cnttmp = 1'b 0;`
625			`end`
626			`else`
627			`begin`
628
629			`rxdata <= ivlan_ctl[7:0];`
630			`state <= state_typ_s_stack;`
631			`process_7_cnttmp = 1'b 0;`
632
633			`end`
634			`end`
635			`end`
636			`state_typ_s_stack:`
637			`begin`
638			`if (count == 0)`
639			`begin`
640			`rxdata <= 8'h 81;`
641			`end`
642			`else if (count == 1 )`
643			`begin`
644			`rxdata <= 8'h 00;`
645			`end`
646			`else if (count == 2 )`
647			`begin`
648			`rxdata <= ivlan_ctl[15:8];`
649			`end`
650			`else if (count == 3 )`
651			`begin`
652
653			`rxdata <= ivlan_ctl[7:0];`
654			`state <= state_typ_s_len;`
655			`process_7_cnttmp = 1'b 0;`
656
657			`end`
658			`end`
659			`state_typ_s_len:`
660			`begin`
661			`if (count == 0)`
662			`begin`
663			`if (ifrmtype != 0)`
664			`begin`
665			`rxdata <= ifrmtype[15:8];`
666			`end`
667			`else`
668			`begin`
669			`rxdata <= ilen[15:8]; // MSB`
670			`end`
671			`end`
672			`else if (count == 1 )`
673			`begin`
674			`if (ifrmtype != 0)`
675			`begin`
676			`rxdata <= ifrmtype[7:0];`
677			`end`
678			`else`
679			`begin`
680			`rxdata <= ilen[7:0]; // LSB`
681			`end`
682			`// if zero length frame go directly to pad`
683			`if (ilen == 0)`
684			`begin`
685			`if (idata_only == 1'b 1 & iend_err == 1'b 1)`
686			`begin`
687			`state <= state_typ_s_enderr;`
688			`end`
689			`else if (idata_only == 1'b 1 )`
690			`begin`
691			`state <= state_typ_s_idle; // stop immediately`
692			`end`
693			`else if (ipad_en == 1'b 1 )`
694			`begin`
695			`state <= state_typ_s_pad;`
696			`end`
697			`else`
698			`begin`
699			`state <= state_typ_s_crc;`
700			`end`
701			`end`
702			`else`
703			`begin`
704			`state <= state_typ_s_data;`
705			`end`
706			`process_7_cnttmp = 1'b 0;`
707			`end`
708			`end`
709			`state_typ_s_data:`
710			`begin`
711			`if (count == 0)`
712			`begin`
713			`rxdata <= icntstart; // first the init`
714			`datacnt <= icntstart;`
715			`end`
716			`else if (count == 1 )`
717			`begin`
718			`rxdata <= icntstep; // then the step`
719			`end`
720			`else`
721			`begin`
722			`rxdata <= datacnt; // then data`
723			`datacnt <= (datacnt + icntstep) % 256;`
724			`end`
725			`// check end of payload`
726			`if (count >= ilen - 1'b 1)`
727			`begin`
728			`if (idata_only == 1'b 1)`
729			`begin`
730			`if (iend_err == 1'b 1)`
731			`begin`
732			`state <= state_typ_s_enderr;`
733			`end`
734			`else if (iipg_len != 0 )`
735			`begin`
736			`state <= state_typ_s_ipg;`
737			`process_7_cnttmp = 1'b 0;`
738			`end`
739			`else`
740			`begin`
741			`state <= state_typ_s_idle;`
742			`end`
743			`end`
744			`else if (poscnt < 6'b 111100 - 1'b 1 & ipad_en ==`
745			`1'b 1 )`
746			`begin`
747			`// need to pad ?`
748			`state <= state_typ_s_pad;`
749			`end`
750			`else`
751			`begin`
752			`state <= state_typ_s_crc;`
753			`process_7_cnttmp = 1'b 0;`
754			`end`
755			`// modify last data byte if payload error was requested`
756			`if (ipayload_err == 1'b 1)`
757			`begin`
758			`rxdata <= rxdata; // just keep the old value signals error`
759			`end`
760			`end`
761			`end`
762			`state_typ_s_pad:`
763			`begin`
764			`rxdata <= {8{1'b 0}}; // PAD BYTE`
765			`if (poscnt >= 6'b 111100 - 1'b 1)`
766			`begin`
767			`state <= state_typ_s_crc;`
768			`process_7_cnttmp = 1'b 0;`
769			`end`
770			`end`
771			`state_typ_s_crc:`
772			`begin`
773			`process_7_hi = 5'b 11111 - count * 8;`
774			`// send CRC inverted, MSB of most significant byte first`
775
776			`for (V2V_process_7_i = 0; V2V_process_7_i <= 7; V2V_process_7_i = V2V_process_7_i + 1)`
777			`begin`
778			`rxdata[V2V_process_7_i] <= crc32[process_7_hi - V2V_process_7_i] ^ 1'b 1; // first LSB is CRC MSB`
779			`end`
780			`if (count == 2 & icrc_err == 1'b 1)`
781			`begin`
782			`rxdata <= rxdata ^ 8'h FF; // produce some wrong number`
783			`end`
784			`if (count == 3)`
785			`begin`
786			`if (iend_err == 1'b 1)`
787			`begin`
788			`state <= state_typ_s_enderr;`
789			`end`
790			`else if (iipg_len > 0 )`
791			`begin`
792			`state <= state_typ_s_ipg;`
793			`process_7_cnttmp = 1'b 1;`
794			`end`
795			`else`
796			`begin`
797			`state <= state_typ_s_idle;`
798			`end`
799			`end`
800			`end`
801			`state_typ_s_enderr:`
802			`begin`
803			`if (iipg_len == 0)`
804			`begin`
805			`// delay dv going low by one cycle`
806			`state <= state_typ_s_idle;`
807			`end`
808			`else`
809			`begin`
810			`state <= state_typ_s_ipg;`
811			`process_7_cnttmp = 1'b 1;`
812			`end`
813			`end`
814			`state_typ_s_ipg:`
815			`begin`
816			`if (count >= iipg_len)`
817			`begin`
818			`// wait after last`
819			`state <= state_typ_s_idle;`
820			`end`
821			`end`
822			`endcase`
823			`count <= process_7_cnttmp; // load the counter with the new value`
824			`end`
825			`end`
826
827			`// local copied (registered) commands`
828			`// ----------------------------------`
829
830			`endmodule //`
831