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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [ethmon2.v] - Blame information for rev 20

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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: ethmon2.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/ethmon2.v,v $
//
// $Revision: #1 $
// $Date: 2012/06/21 $
// Check in by : $Author: swbranch $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// MII Interface Ethernet Traffic Monitor/Decoder
//
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps
//`include "common_header.verilog" 
 
module ethmonitor2 (reset,
   tx_clk,
   txd,
   tx_dv,
   tx_er,
   tx_sop,
   tx_eop,
   ethernet_speed,
   mii_mode,
   rgmii_mode,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   payload,
   payload_vld,
   is_vlan,
   is_stack_vlan,
   is_pause,
   crc_err,
   prmbl_err,
   len_err,
   payload_err,
   frame_err,
   pause_op_err,
   pause_dst_err,
   mac_err,
   end_err,
   jumbo_en,
   data_only,
   frm_rcvd);
 
input   reset; //  active high
input   tx_clk;
input   [7:0] txd;
input   tx_dv;
input   tx_er;
input   tx_sop;
input   tx_eop;
input   ethernet_speed;
input   mii_mode; //  4-bit Nibbles (Fast Ethernet)
input   rgmii_mode; //  4-bit DDR (Reduced Gigabit)
output   [47:0] dst; //  destination address
output   [47:0] src; //  source address
output   [13:0] prmble_len; //  length of preamble
output   [15:0] pquant; //  Pause Quanta value
output   [15:0] vlan_ctl; //  VLAN control info
output   [15:0] len; //  Length of payload
output   [15:0] frmtype; //  if non-null: type field instead length
output   [7:0] payload;
output   payload_vld;
output   is_vlan;
output   is_stack_vlan;
output   is_pause;
output   crc_err;
output   prmbl_err;
output   len_err;
output   payload_err;
output   frame_err;
output   pause_op_err;
output   pause_dst_err;
output   mac_err;
output   end_err;
input   jumbo_en;
input   data_only;
output   frm_rcvd;
//  GMII transmit interface: To be connected to MAC TX
wire    [47:0] dst;
wire    [47:0] src;
wire    [13:0] prmble_len;
wire    [15:0] pquant;
wire    [15:0] vlan_ctl;
wire    [15:0] len;
wire    [15:0] frmtype;
wire    [7:0] payload;
//  Indicators
wire    payload_vld;
wire    is_vlan;
wire    is_stack_vlan;
wire    is_pause;
wire    crc_err;
wire    prmbl_err;
wire    len_err;
wire    payload_err;
wire    frame_err;
wire    pause_op_err;
wire    pause_dst_err;
wire    mac_err;
//  Control
wire    end_err;
wire    frm_rcvd;
reg     clk_div2;
//  Signals for GMII Monitor
reg    gmii_clk;
wire    [7:0] gmii_d;
wire    gmii_en;
wire    gmii_er;
//  RGMII demultiplexed
 
reg     [7:0] ddr_rgmii_d;
reg     ddr_rgmii_en;
reg     ddr_rgmii_er;
 
reg     [7:0] ddr_rgmii_d_dly1;
reg     ddr_rgmii_en_dly1;
reg     ddr_rgmii_er_dly1;
 
reg     [7:0]  sdr_rgmii_d;
reg     sdr_rgmii_en;
reg     sdr_rgmii_er;
 
reg     PartOfFrameData_1000;
reg     FrameError_1000;
 
wire     [7:0] rgmii_d;
wire     rgmii_en;
wire     rgmii_er;
//  MII demultiplexed
reg     [3:0] mii_d_lo; //  low nibble
reg     [7:0] mii_d;
reg     mii_en;
reg     mii_er;
reg     mii_hi; //  hi nibble is on bus
wire    frm_rcvd_mon;
reg     frm_rcvd_i;
//  demultiplex RGMII 
reg     [7:0] rgmii_10_100_d;
reg     [3:0] rgmii_10_100_d_lo;
reg     rgmii_hi;
 
 
 
//SDR rising edge 
always @(reset or posedge tx_clk)
   begin
   if (reset == 1'b 1)
      begin
      sdr_rgmii_d [3:0] <= {4{1'b 0}};    //  rising edge
      sdr_rgmii_en      <= 1'b 0;
      end
   else
      begin
      sdr_rgmii_d[3:0]  <= #2 txd[3:0];   //  low nibble 
      sdr_rgmii_en      <= #2 tx_dv; //  dv in 1st half of clock
      end
   end
 
//SDR falling edge 
always @(reset or negedge tx_clk)
   begin
   if (reset == 1'b 1)
      begin
      sdr_rgmii_d[7:4] <= {4{1'b 0}};    //  falling edge
      sdr_rgmii_er     <= 1'b 0;
      end
   else
      begin
      sdr_rgmii_d[7:4] <= #2 txd[3:0];   //  high nibble on rising edge
      sdr_rgmii_er     <= #2 tx_dv;
      end
   end
 
//DDR edges 
always @(reset or posedge tx_clk)
   begin
   if (reset == 1'b 1)
      begin
      ddr_rgmii_d       <= {8{1'b 0}};
      ddr_rgmii_en      <= 1'b 0;
      ddr_rgmii_er      <= 1'b 0;
 
      ddr_rgmii_d_dly1  <= {8{1'b 0}};
      ddr_rgmii_en_dly1 <= 1'b 0;
      ddr_rgmii_er_dly1 <= 1'b 0;
 
      end
   else
      begin
      ddr_rgmii_d  <= sdr_rgmii_d;
      ddr_rgmii_en <= sdr_rgmii_en;
      ddr_rgmii_er <= sdr_rgmii_er;
 
      ddr_rgmii_d_dly1  <= ddr_rgmii_d;
      ddr_rgmii_en_dly1 <= ddr_rgmii_en;
      ddr_rgmii_er_dly1 <= ddr_rgmii_er;
 
      end
   end
 
//demultiplex rgmii 10/100  
always @(posedge reset or posedge tx_clk)
   begin
   if (reset == 1'b 1)
      begin
      rgmii_10_100_d <= {8{1'b 0}};
      rgmii_10_100_d_lo <= {4{1'b 0}};   //  low nibble
      end
   else
      begin
//  prepare that we can have a start at any clock cycle.
      if (tx_dv == 1'b 0 & sdr_rgmii_en == 1'b 0)
         begin
         rgmii_hi <= 1'b 0;
         end
      else
         begin
         rgmii_hi <= ~rgmii_hi;
         end
//  read two nibbles
      if (rgmii_hi == 1'b 0)
         begin
         rgmii_10_100_d_lo <= txd[3:0];  //  low nibble first
         end
      else
         begin
         rgmii_10_100_d[7:0] <= #(5.000000e-01) {txd[3:0], rgmii_10_100_d_lo};    //  hi nibble and all internal dv
         end
          end
   end
 
//Frame markers
always @(posedge reset or posedge tx_clk)
      begin
   if (reset == 1'b 1)
         begin
      PartOfFrameData_1000  <= 1'b 0;
      FrameError_1000       <= 1'b 0;
         end
      else
         begin
 
          if (ddr_rgmii_en_dly1 == 1'b1 && ddr_rgmii_en == 1'b0)
           begin
              PartOfFrameData_1000  <= 1'b 0;
              FrameError_1000       <= 1'b 0;
           end
          else if (ddr_rgmii_en_dly1 == 1'b0)
           begin
              PartOfFrameData_1000  <= 1'b 0;
              FrameError_1000       <= 1'b 0;
         end
          else if (ddr_rgmii_d !== 8'hD5)
           begin
              PartOfFrameData_1000  <= 1'b 1;
           end
 
           // Generate Frame Error
           if (ddr_rgmii_en == 1'b1 && ddr_rgmii_er == 1'b0)
              FrameError_1000      <= 1'b1;
           else if ( (ddr_rgmii_en_dly1 == 1'b1 && ddr_rgmii_en == 1'b0) | ddr_rgmii_d_dly1 == 1'b0)
              FrameError_1000      <= 1'b0;
      end
   end
 
 
assign rgmii_d  = ethernet_speed == 1'b1 ? ddr_rgmii_d_dly1 : rgmii_10_100_d ;
assign rgmii_en = PartOfFrameData_1000;
assign rgmii_er = FrameError_1000;
 
//always @ (posedge reset or posedge gmii_clk)
//
// begin
//   if (reset == 1'b 1)
//     begin
//      rgmii_10_100_d  <= 8{1'b0};    
//      rgmii_10_100_en <= 1'b0;    
//      rgmii_10_100_er <= 1'b0;    
//     end
//   else
//     begin
//      rgmii_10_100_d  <= 8{1'b0};    
//      rgmii_10_100_en <= 1'b0;    
//      rgmii_10_100_er <= 1'b0;    
//     end
//
// end
 
 
 
//  demultiplex MII 
always @(posedge reset or posedge tx_clk)
   begin : process_2
   if (reset == 1'b 1)
      begin
      mii_d <= {8{1'b 0}};
      mii_d_lo <= {4{1'b 0}};   //  low nibble
      mii_en <= 1'b 0;
      mii_er <= 1'b 0;
      mii_hi <= 1'b 0;
      frm_rcvd_i <= 1'b 0;
      clk_div2 <= 1'b 0;
      end
   else
      begin
      clk_div2 <= ~clk_div2;
//  prepare that we can have a start at any clock cycle.
      if (tx_dv == 1'b 0 & mii_en == 1'b 0)
         begin
         mii_hi <= 1'b 0;
         end
      else
         begin
         mii_hi <= ~mii_hi;
         end
//  read two nibbles
      if (mii_hi == 1'b 0)
         begin
         mii_d_lo <= txd[3:0];  //  low nibble first
         end
      else
         begin
         mii_d[7:0] <= #(5.000000e-01) {txd[3:0], mii_d_lo};    //  hi nibble and all internal dv
         mii_en <= #(5.000000e-01) tx_dv;
         mii_er <= #(5.000000e-01) tx_er;
         end
//  frame received indication only for 1 clock cycle
      if (frm_rcvd_mon == 1'b 1 & frm_rcvd_i == 1'b 0)
         begin
         frm_rcvd_i <= 1'b 1;
         end
      else
         begin
         frm_rcvd_i <= 1'b 0;
         end
      end
   end
 
 
 
//  connect Model Signals
 
 
//assign gmii_clk = mii_mode == 1'b 0 ? tx_clk : 
//    clk_div2;
 
 
 
always @ (*)
 
 begin
   if (ethernet_speed == 1'b 0)
     begin
      if (rgmii_mode == 1'b1|mii_mode == 1'b1)
       gmii_clk <= clk_div2;
     end
   else
     begin
      if (rgmii_mode == 1'b1 & mii_mode == 1'b0)
       gmii_clk <= tx_clk;
     end
 
 end
 
 
assign gmii_d = rgmii_mode == 1'b 1 ? rgmii_d :
    mii_mode == 1'b 1 ? mii_d :
    txd;
assign gmii_en = (rgmii_mode == 1'b 1 & ethernet_speed == 1'b1) ? rgmii_en :
    (mii_mode == 1'b 1|ethernet_speed == 1'b0) ? mii_en :
    tx_dv;
assign gmii_er = rgmii_mode == 1'b 1 ? rgmii_er :
    mii_mode == 1'b 1 ? mii_er :
    tx_er;
assign frm_rcvd = (mii_mode == 1'b 1|ethernet_speed == 1'b0) ? frm_rcvd_i :
    frm_rcvd_mon;
//  connect GMII Monitor
//  --------------------
ethmonitor gmii_mon (.reset(reset),
          //  active high
          .tx_clk(gmii_clk),
          .txd(gmii_d),
          .tx_dv(gmii_en),
          .tx_er(gmii_er),
          .tx_sop(tx_sop),
          .tx_eop(tx_eop),
          .dst(dst),
          .src(src),
          .prmble_len(prmble_len),
          .pquant(pquant),
          .vlan_ctl(vlan_ctl),
          .len(len),
          .frmtype(frmtype),
          .payload(payload),
          .payload_vld(payload_vld),
          .is_vlan(is_vlan),
          .is_stack_vlan(is_stack_vlan),
          .is_pause(is_pause),
          .crc_err(crc_err),
          .prmbl_err(prmbl_err),
          .len_err(len_err),
          .payload_err(payload_err),
          .frame_err(frame_err),
          .pause_op_err(pause_op_err),
          .pause_dst_err(pause_dst_err),
          .mac_err(mac_err),
          .end_err(end_err),
          .jumbo_en(jumbo_en),
          .data_only(data_only),
          .frm_rcvd(frm_rcvd_mon));
//  GMII Monitor
 
endmodule // module ethmonitor2
 

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [ethmon2.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: ethmon2.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/ethmon2.v,v $`
8			`//`
9			`// $Revision: #1 $`
10	20	jefflieu	`// $Date: 2012/06/21 $`
11			`// Check in by : $Author: swbranch $`
12	9	jefflieu	`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// MII Interface Ethernet Traffic Monitor/Decoder`
19			`//`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps
29			//`include "common_header.verilog"
30
31			`module ethmonitor2 (reset,`
32			`tx_clk,`
33			`txd,`
34			`tx_dv,`
35			`tx_er,`
36			`tx_sop,`
37			`tx_eop,`
38			`ethernet_speed,`
39			`mii_mode,`
40			`rgmii_mode,`
41			`dst,`
42			`src,`
43			`prmble_len,`
44			`pquant,`
45			`vlan_ctl,`
46			`len,`
47			`frmtype,`
48			`payload,`
49			`payload_vld,`
50			`is_vlan,`
51			`is_stack_vlan,`
52			`is_pause,`
53			`crc_err,`
54			`prmbl_err,`
55			`len_err,`
56			`payload_err,`
57			`frame_err,`
58			`pause_op_err,`
59			`pause_dst_err,`
60			`mac_err,`
61			`end_err,`
62			`jumbo_en,`
63			`data_only,`
64			`frm_rcvd);`
65
66			`input reset; // active high`
67			`input tx_clk;`
68			`input [7:0] txd;`
69			`input tx_dv;`
70			`input tx_er;`
71			`input tx_sop;`
72			`input tx_eop;`
73			`input ethernet_speed;`
74			`input mii_mode; // 4-bit Nibbles (Fast Ethernet)`
75			`input rgmii_mode; // 4-bit DDR (Reduced Gigabit)`
76			`output [47:0] dst; // destination address`
77			`output [47:0] src; // source address`
78			`output [13:0] prmble_len; // length of preamble`
79			`output [15:0] pquant; // Pause Quanta value`
80			`output [15:0] vlan_ctl; // VLAN control info`
81			`output [15:0] len; // Length of payload`
82			`output [15:0] frmtype; // if non-null: type field instead length`
83			`output [7:0] payload;`
84			`output payload_vld;`
85			`output is_vlan;`
86			`output is_stack_vlan;`
87			`output is_pause;`
88			`output crc_err;`
89			`output prmbl_err;`
90			`output len_err;`
91			`output payload_err;`
92			`output frame_err;`
93			`output pause_op_err;`
94			`output pause_dst_err;`
95			`output mac_err;`
96			`output end_err;`
97			`input jumbo_en;`
98			`input data_only;`
99			`output frm_rcvd;`
100			`// GMII transmit interface: To be connected to MAC TX`
101			`wire [47:0] dst;`
102			`wire [47:0] src;`
103			`wire [13:0] prmble_len;`
104			`wire [15:0] pquant;`
105			`wire [15:0] vlan_ctl;`
106			`wire [15:0] len;`
107			`wire [15:0] frmtype;`
108			`wire [7:0] payload;`
109			`// Indicators`
110			`wire payload_vld;`
111			`wire is_vlan;`
112			`wire is_stack_vlan;`
113			`wire is_pause;`
114			`wire crc_err;`
115			`wire prmbl_err;`
116			`wire len_err;`
117			`wire payload_err;`
118			`wire frame_err;`
119			`wire pause_op_err;`
120			`wire pause_dst_err;`
121			`wire mac_err;`
122			`// Control`
123			`wire end_err;`
124			`wire frm_rcvd;`
125			`reg clk_div2;`
126			`// Signals for GMII Monitor`
127			`reg gmii_clk;`
128			`wire [7:0] gmii_d;`
129			`wire gmii_en;`
130			`wire gmii_er;`
131			`// RGMII demultiplexed`
132
133			`reg [7:0] ddr_rgmii_d;`
134			`reg ddr_rgmii_en;`
135			`reg ddr_rgmii_er;`
136
137			`reg [7:0] ddr_rgmii_d_dly1;`
138			`reg ddr_rgmii_en_dly1;`
139			`reg ddr_rgmii_er_dly1;`
140
141			`reg [7:0] sdr_rgmii_d;`
142			`reg sdr_rgmii_en;`
143			`reg sdr_rgmii_er;`
144
145			`reg PartOfFrameData_1000;`
146			`reg FrameError_1000;`
147
148			`wire [7:0] rgmii_d;`
149			`wire rgmii_en;`
150			`wire rgmii_er;`
151			`// MII demultiplexed`
152			`reg [3:0] mii_d_lo; // low nibble`
153			`reg [7:0] mii_d;`
154			`reg mii_en;`
155			`reg mii_er;`
156			`reg mii_hi; // hi nibble is on bus`
157			`wire frm_rcvd_mon;`
158			`reg frm_rcvd_i;`
159			`// demultiplex RGMII`
160			`reg [7:0] rgmii_10_100_d;`
161			`reg [3:0] rgmii_10_100_d_lo;`
162			`reg rgmii_hi;`
163
164
165
166			`//SDR rising edge`
167			`always @(reset or posedge tx_clk)`
168			`begin`
169			`if (reset == 1'b 1)`
170			`begin`
171			`sdr_rgmii_d [3:0] <= {4{1'b 0}}; // rising edge`
172			`sdr_rgmii_en <= 1'b 0;`
173			`end`
174			`else`
175			`begin`
176			`sdr_rgmii_d[3:0] <= #2 txd[3:0]; // low nibble`
177			`sdr_rgmii_en <= #2 tx_dv; // dv in 1st half of clock`
178			`end`
179			`end`
180
181			`//SDR falling edge`
182			`always @(reset or negedge tx_clk)`
183			`begin`
184			`if (reset == 1'b 1)`
185			`begin`
186			`sdr_rgmii_d[7:4] <= {4{1'b 0}}; // falling edge`
187			`sdr_rgmii_er <= 1'b 0;`
188			`end`
189			`else`
190			`begin`
191			`sdr_rgmii_d[7:4] <= #2 txd[3:0]; // high nibble on rising edge`
192			`sdr_rgmii_er <= #2 tx_dv;`
193			`end`
194			`end`
195
196			`//DDR edges`
197			`always @(reset or posedge tx_clk)`
198			`begin`
199			`if (reset == 1'b 1)`
200			`begin`
201			`ddr_rgmii_d <= {8{1'b 0}};`
202			`ddr_rgmii_en <= 1'b 0;`
203			`ddr_rgmii_er <= 1'b 0;`
204
205			`ddr_rgmii_d_dly1 <= {8{1'b 0}};`
206			`ddr_rgmii_en_dly1 <= 1'b 0;`
207			`ddr_rgmii_er_dly1 <= 1'b 0;`
208
209			`end`
210			`else`
211			`begin`
212			`ddr_rgmii_d <= sdr_rgmii_d;`
213			`ddr_rgmii_en <= sdr_rgmii_en;`
214			`ddr_rgmii_er <= sdr_rgmii_er;`
215
216			`ddr_rgmii_d_dly1 <= ddr_rgmii_d;`
217			`ddr_rgmii_en_dly1 <= ddr_rgmii_en;`
218			`ddr_rgmii_er_dly1 <= ddr_rgmii_er;`
219
220			`end`
221			`end`
222
223			`//demultiplex rgmii 10/100`
224			`always @(posedge reset or posedge tx_clk)`
225			`begin`
226			`if (reset == 1'b 1)`
227			`begin`
228			`rgmii_10_100_d <= {8{1'b 0}};`
229			`rgmii_10_100_d_lo <= {4{1'b 0}}; // low nibble`
230			`end`
231			`else`
232			`begin`
233			`// prepare that we can have a start at any clock cycle.`
234			`if (tx_dv == 1'b 0 & sdr_rgmii_en == 1'b 0)`
235			`begin`
236			`rgmii_hi <= 1'b 0;`
237			`end`
238			`else`
239			`begin`
240			`rgmii_hi <= ~rgmii_hi;`
241			`end`
242			`// read two nibbles`
243			`if (rgmii_hi == 1'b 0)`
244			`begin`
245			`rgmii_10_100_d_lo <= txd[3:0]; // low nibble first`
246			`end`
247			`else`
248			`begin`
249			`rgmii_10_100_d[7:0] <= #(5.000000e-01) {txd[3:0], rgmii_10_100_d_lo}; // hi nibble and all internal dv`
250			`end`
251			`end`
252			`end`
253
254			`//Frame markers`
255			`always @(posedge reset or posedge tx_clk)`
256			`begin`
257			`if (reset == 1'b 1)`
258			`begin`
259			`PartOfFrameData_1000 <= 1'b 0;`
260			`FrameError_1000 <= 1'b 0;`
261			`end`
262			`else`
263			`begin`
264
265			`if (ddr_rgmii_en_dly1 == 1'b1 && ddr_rgmii_en == 1'b0)`
266			`begin`
267			`PartOfFrameData_1000 <= 1'b 0;`
268			`FrameError_1000 <= 1'b 0;`
269			`end`
270			`else if (ddr_rgmii_en_dly1 == 1'b0)`
271			`begin`
272			`PartOfFrameData_1000 <= 1'b 0;`
273			`FrameError_1000 <= 1'b 0;`
274			`end`
275			`else if (ddr_rgmii_d !== 8'hD5)`
276			`begin`
277			`PartOfFrameData_1000 <= 1'b 1;`
278			`end`
279
280			`// Generate Frame Error`
281			`if (ddr_rgmii_en == 1'b1 && ddr_rgmii_er == 1'b0)`
282			`FrameError_1000 <= 1'b1;`
283			`else if ( (ddr_rgmii_en_dly1 == 1'b1 && ddr_rgmii_en == 1'b0) \| ddr_rgmii_d_dly1 == 1'b0)`
284			`FrameError_1000 <= 1'b0;`
285			`end`
286			`end`
287
288
289			`assign rgmii_d = ethernet_speed == 1'b1 ? ddr_rgmii_d_dly1 : rgmii_10_100_d ;`
290			`assign rgmii_en = PartOfFrameData_1000;`
291			`assign rgmii_er = FrameError_1000;`
292
293			`//always @ (posedge reset or posedge gmii_clk)`
294			`//`
295			`// begin`
296			`// if (reset == 1'b 1)`
297			`// begin`
298			`// rgmii_10_100_d <= 8{1'b0};`
299			`// rgmii_10_100_en <= 1'b0;`
300			`// rgmii_10_100_er <= 1'b0;`
301			`// end`
302			`// else`
303			`// begin`
304			`// rgmii_10_100_d <= 8{1'b0};`
305			`// rgmii_10_100_en <= 1'b0;`
306			`// rgmii_10_100_er <= 1'b0;`
307			`// end`
308			`//`
309			`// end`
310
311
312
313			`// demultiplex MII`
314			`always @(posedge reset or posedge tx_clk)`
315			`begin : process_2`
316			`if (reset == 1'b 1)`
317			`begin`
318			`mii_d <= {8{1'b 0}};`
319			`mii_d_lo <= {4{1'b 0}}; // low nibble`
320			`mii_en <= 1'b 0;`
321			`mii_er <= 1'b 0;`
322			`mii_hi <= 1'b 0;`
323			`frm_rcvd_i <= 1'b 0;`
324			`clk_div2 <= 1'b 0;`
325			`end`
326			`else`
327			`begin`
328			`clk_div2 <= ~clk_div2;`
329			`// prepare that we can have a start at any clock cycle.`
330			`if (tx_dv == 1'b 0 & mii_en == 1'b 0)`
331			`begin`
332			`mii_hi <= 1'b 0;`
333			`end`
334			`else`
335			`begin`
336			`mii_hi <= ~mii_hi;`
337			`end`
338			`// read two nibbles`
339			`if (mii_hi == 1'b 0)`
340			`begin`
341			`mii_d_lo <= txd[3:0]; // low nibble first`
342			`end`
343			`else`
344			`begin`
345			`mii_d[7:0] <= #(5.000000e-01) {txd[3:0], mii_d_lo}; // hi nibble and all internal dv`
346			`mii_en <= #(5.000000e-01) tx_dv;`
347			`mii_er <= #(5.000000e-01) tx_er;`
348			`end`
349			`// frame received indication only for 1 clock cycle`
350			`if (frm_rcvd_mon == 1'b 1 & frm_rcvd_i == 1'b 0)`
351			`begin`
352			`frm_rcvd_i <= 1'b 1;`
353			`end`
354			`else`
355			`begin`
356			`frm_rcvd_i <= 1'b 0;`
357			`end`
358			`end`
359			`end`
360
361
362
363			`// connect Model Signals`
364
365
366			`//assign gmii_clk = mii_mode == 1'b 0 ? tx_clk :`
367			`// clk_div2;`
368
369
370
371			`always @ (*)`
372
373			`begin`
374			`if (ethernet_speed == 1'b 0)`
375			`begin`
376			`if (rgmii_mode == 1'b1\|mii_mode == 1'b1)`
377			`gmii_clk <= clk_div2;`
378			`end`
379			`else`
380			`begin`
381			`if (rgmii_mode == 1'b1 & mii_mode == 1'b0)`
382			`gmii_clk <= tx_clk;`
383			`end`
384
385			`end`
386
387
388			`assign gmii_d = rgmii_mode == 1'b 1 ? rgmii_d :`
389			`mii_mode == 1'b 1 ? mii_d :`
390			`txd;`
391			`assign gmii_en = (rgmii_mode == 1'b 1 & ethernet_speed == 1'b1) ? rgmii_en :`
392			`(mii_mode == 1'b 1\|ethernet_speed == 1'b0) ? mii_en :`
393			`tx_dv;`
394			`assign gmii_er = rgmii_mode == 1'b 1 ? rgmii_er :`
395			`mii_mode == 1'b 1 ? mii_er :`
396			`tx_er;`
397			`assign frm_rcvd = (mii_mode == 1'b 1\|ethernet_speed == 1'b0) ? frm_rcvd_i :`
398			`frm_rcvd_mon;`
399			`// connect GMII Monitor`
400			`// --------------------`
401			`ethmonitor gmii_mon (.reset(reset),`
402			`// active high`
403			`.tx_clk(gmii_clk),`
404			`.txd(gmii_d),`
405			`.tx_dv(gmii_en),`
406			`.tx_er(gmii_er),`
407			`.tx_sop(tx_sop),`
408			`.tx_eop(tx_eop),`
409			`.dst(dst),`
410			`.src(src),`
411			`.prmble_len(prmble_len),`
412			`.pquant(pquant),`
413			`.vlan_ctl(vlan_ctl),`
414			`.len(len),`
415			`.frmtype(frmtype),`
416			`.payload(payload),`
417			`.payload_vld(payload_vld),`
418			`.is_vlan(is_vlan),`
419			`.is_stack_vlan(is_stack_vlan),`
420			`.is_pause(is_pause),`
421			`.crc_err(crc_err),`
422			`.prmbl_err(prmbl_err),`
423			`.len_err(len_err),`
424			`.payload_err(payload_err),`
425			`.frame_err(frame_err),`
426			`.pause_op_err(pause_op_err),`
427			`.pause_dst_err(pause_dst_err),`
428			`.mac_err(mac_err),`
429			`.end_err(end_err),`
430			`.jumbo_en(jumbo_en),`
431			`.data_only(data_only),`
432			`.frm_rcvd(frm_rcvd_mon));`
433			`// GMII Monitor`
434
435			`endmodule // module ethmonitor2`
436