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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_timing_adapter_fifo8.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/timing_adapter/altera_tse_timing_adapter_fifo8.v,v $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : SKNg
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : SIMULATION ONLY
//
// simple atlantic fifo FOR 8BIT IMPLEMENTATION
 
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
module loopback_adapter_fifo (
   output reg  [11: 0] fill_level ,  //OUTPUT : 'TIMING ADAPTER' FIFO FILL LEVEL
 
   // Interface: clock
   input              clk,           //INPUT  : CLK
   input              reset,         //INPUT  : Asynchronous ACTIVE LOW Reset
   // Interface: data_in
   output reg         in_ready,      //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'
   input              in_valid,      //INPUT  : 'MAC TO TIMING ADAPTER' DATA VALID
   input      [10: 0] in_data,       //INPUT  : 'MAC TO TIMING ADAPTER' DATA
   // Interface: data_out
   input              out_ready,     //INPUT  : 'APPLICATION' READYNESS TO ACCEPT DATA FROM 'TIMING ADAPTER'
   output reg         out_valid,     //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA VALID
   output reg [10: 0] out_data       //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA
);
 
   // ---------------------------------------------------------------------
   //| Internal Parameters
   // ---------------------------------------------------------------------
   parameter DEPTH = 2048;
   parameter DATA_WIDTH = 11;
   parameter ADDR_WIDTH = 11;
 
   // ---------------------------------------------------------------------
   //| Signals
   // ---------------------------------------------------------------------
   reg [ADDR_WIDTH-1:0] wr_addr;
   reg [ADDR_WIDTH-1:0] rd_addr;
   reg [ADDR_WIDTH-1:0] next_wr_addr;
   reg [ADDR_WIDTH-1:0] next_rd_addr;
   reg [ADDR_WIDTH-1:0] mem_rd_addr;
   reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
   reg          empty;
   reg          full;
   reg out_ready_vector;
   integer j;
   reg enable_reading;
 
   // ---------------------------------------------------------------------
   //| FIFO Status
   // ---------------------------------------------------------------------
   always @(out_ready or wr_addr or rd_addr or full)
   begin
//      out_valid = !empty;
      out_ready_vector = out_ready;
      in_ready  = !full;
      next_wr_addr = wr_addr + 1;
      next_rd_addr = rd_addr + 1;
        fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
        fill_level[ADDR_WIDTH] = 0;
 
        if (full)
           fill_level = DEPTH;
 
   end
 
   // ---------------------------------------------------------------------
   //| Manage Pointers
   // ---------------------------------------------------------------------
   always @ (posedge reset or posedge clk)
   begin
          if (reset)
           begin
                 enable_reading <= 1'b0;
       end
          else
           begin
                 if (empty)
                  begin
                        enable_reading <= 1'b0;
          end
         else
                  begin
          if (in_data[1] & in_valid)
           enable_reading <= 1'b1;
          end
       end
   end
 
 
   always @ (posedge reset or posedge clk)
   begin
      if (reset)
        begin
         wr_addr  <= 0;
         rd_addr  <= 0;
         empty    <= 1;
         rd_addr  <= 0;
         full     <= 0;
         out_valid<= 0;
        end
    else
      begin
         out_valid <= enable_reading;
 
         if (in_ready && in_valid)
          begin
            wr_addr <= next_wr_addr;
            empty   <= 0;
          if (next_wr_addr == rd_addr)
            full <= 1;
          end
 
         if (out_ready_vector && out_valid)
          begin
           rd_addr <= next_rd_addr;
           full    <= 0;
               if (next_rd_addr == wr_addr)
                begin
                 empty <= 1;
                 out_valid <= 0;
                end
          end
 
         if (out_ready_vector && out_valid && in_ready && in_valid)
          begin
           full  <= full;
           empty <= empty;
          end
      end
   end // always @ (posedge reset, posedge clk)
 
 
   always @ (rd_addr or out_ready or out_valid or next_rd_addr)
   begin
      mem_rd_addr = rd_addr;
      if (out_ready && out_valid)
      begin
        mem_rd_addr = next_rd_addr;
      end
   end
 
 
   // ---------------------------------------------------------------------
   //| Infer Memory
   // ---------------------------------------------------------------------
   always @ (posedge reset or posedge clk)
   begin
      if (reset)
           begin
 
                   for (j = 0; j < DEPTH; j=j+1)
                    begin
                     mem[j] <= 11'h0;
                        end
           end
      else
       begin
         if (in_ready && in_valid)
           mem[wr_addr] <= in_data;
       end
 
       out_data = mem[mem_rd_addr];
   end
 
endmodule // loopback_adapter_fifo
 
 

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: altera_tse_timing_adapter_fifo8.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/timing_adapter/altera_tse_timing_adapter_fifo8.v,v $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : SKNg`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : SIMULATION ONLY`
17			`//`
18			`// simple atlantic fifo FOR 8BIT IMPLEMENTATION`
19
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`module loopback_adapter_fifo (`
29			`output reg [11: 0] fill_level , //OUTPUT : 'TIMING ADAPTER' FIFO FILL LEVEL`
30
31			`// Interface: clock`
32			`input clk, //INPUT : CLK`
33			`input reset, //INPUT : Asynchronous ACTIVE LOW Reset`
34			`// Interface: data_in`
35			`output reg in_ready, //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'`
36			`input in_valid, //INPUT : 'MAC TO TIMING ADAPTER' DATA VALID`
37			`input [10: 0] in_data, //INPUT : 'MAC TO TIMING ADAPTER' DATA`
38			`// Interface: data_out`
39			`input out_ready, //INPUT : 'APPLICATION' READYNESS TO ACCEPT DATA FROM 'TIMING ADAPTER'`
40			`output reg out_valid, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA VALID`
41			`output reg [10: 0] out_data //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA`
42			`);`
43
44			`// ---------------------------------------------------------------------`
45			`//\| Internal Parameters`
46			`// ---------------------------------------------------------------------`
47			`parameter DEPTH = 2048;`
48			`parameter DATA_WIDTH = 11;`
49			`parameter ADDR_WIDTH = 11;`
50
51			`// ---------------------------------------------------------------------`
52			`//\| Signals`
53			`// ---------------------------------------------------------------------`
54			`reg [ADDR_WIDTH-1:0] wr_addr;`
55			`reg [ADDR_WIDTH-1:0] rd_addr;`
56			`reg [ADDR_WIDTH-1:0] next_wr_addr;`
57			`reg [ADDR_WIDTH-1:0] next_rd_addr;`
58			`reg [ADDR_WIDTH-1:0] mem_rd_addr;`
59			`reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];`
60			`reg empty;`
61			`reg full;`
62			`reg out_ready_vector;`
63			`integer j;`
64			`reg enable_reading;`
65
66			`// ---------------------------------------------------------------------`
67			`//\| FIFO Status`
68			`// ---------------------------------------------------------------------`
69			`always @(out_ready or wr_addr or rd_addr or full)`
70			`begin`
71			`// out_valid = !empty;`
72			`out_ready_vector = out_ready;`
73			`in_ready = !full;`
74			`next_wr_addr = wr_addr + 1;`
75			`next_rd_addr = rd_addr + 1;`
76			`fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;`
77			`fill_level[ADDR_WIDTH] = 0;`
78
79			`if (full)`
80			`fill_level = DEPTH;`
81
82			`end`
83
84			`// ---------------------------------------------------------------------`
85			`//\| Manage Pointers`
86			`// ---------------------------------------------------------------------`
87			`always @ (posedge reset or posedge clk)`
88			`begin`
89			`if (reset)`
90			`begin`
91			`enable_reading <= 1'b0;`
92			`end`
93			`else`
94			`begin`
95			`if (empty)`
96			`begin`
97			`enable_reading <= 1'b0;`
98			`end`
99			`else`
100			`begin`
101			`if (in_data[1] & in_valid)`
102			`enable_reading <= 1'b1;`
103			`end`
104			`end`
105			`end`
106
107
108			`always @ (posedge reset or posedge clk)`
109			`begin`
110			`if (reset)`
111			`begin`
112			`wr_addr <= 0;`
113			`rd_addr <= 0;`
114			`empty <= 1;`
115			`rd_addr <= 0;`
116			`full <= 0;`
117			`out_valid<= 0;`
118			`end`
119			`else`
120			`begin`
121			`out_valid <= enable_reading;`
122
123			`if (in_ready && in_valid)`
124			`begin`
125			`wr_addr <= next_wr_addr;`
126			`empty <= 0;`
127			`if (next_wr_addr == rd_addr)`
128			`full <= 1;`
129			`end`
130
131			`if (out_ready_vector && out_valid)`
132			`begin`
133			`rd_addr <= next_rd_addr;`
134			`full <= 0;`
135			`if (next_rd_addr == wr_addr)`
136			`begin`
137			`empty <= 1;`
138			`out_valid <= 0;`
139			`end`
140			`end`
141
142			`if (out_ready_vector && out_valid && in_ready && in_valid)`
143			`begin`
144			`full <= full;`
145			`empty <= empty;`
146			`end`
147			`end`
148			`end // always @ (posedge reset, posedge clk)`
149
150
151			`always @ (rd_addr or out_ready or out_valid or next_rd_addr)`
152			`begin`
153			`mem_rd_addr = rd_addr;`
154			`if (out_ready && out_valid)`
155			`begin`
156			`mem_rd_addr = next_rd_addr;`
157			`end`
158			`end`
159
160
161			`// ---------------------------------------------------------------------`
162			`//\| Infer Memory`
163			`// ---------------------------------------------------------------------`
164			`always @ (posedge reset or posedge clk)`
165			`begin`
166			`if (reset)`
167			`begin`
168
169			`for (j = 0; j < DEPTH; j=j+1)`
170			`begin`
171			`mem[j] <= 11'h0;`
172			`end`
173			`end`
174			`else`
175			`begin`
176			`if (in_ready && in_valid)`
177			`mem[wr_addr] <= in_data;`
178			`end`
179
180			`out_data = mem[mem_rd_addr];`
181			`end`
182
183			`endmodule // loopback_adapter_fifo`
184
185

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [loopback_adapter_fifo.v] - Blame information for rev 9