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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: $
// $Source: $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// MDIO Slave's Register Map
// Instantiated in top_mdio_slave (top_mdio_slave.v)
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps
//`include "common_header.verilog" 
 
module mdio_reg_sim (reset,
   clk,
   reg_addr,
   reg_write,
   reg_read,
   reg_dout,
   reg_din,
   conf_done);
input   reset;
input   clk; //  MDIO 2.5MHz Clock
input   [4:0] reg_addr; //  Address Register
input   reg_write; //  Write Register       
input   reg_read; //  Read Register         
output   [15:0] reg_dout; //  Data Bus OUT
input   [15:0] reg_din; //  Data Bus IN
output   conf_done; //  PHY Config Done
reg     [15:0] reg_dout;
//  Status
//  ------
reg     conf_done;
reg     [15:0] reg_0;
reg     [15:0] reg_1;
reg     [15:0] reg_2;
reg     [15:0] reg_3;
reg     [15:0] reg_4;
reg     [15:0] reg_5;
reg     [15:0] reg_6;
reg     [15:0] reg_7;
reg     [15:0] reg_8;
reg     [15:0] reg_9;
reg     [15:0] reg_10;
reg     [15:0] reg_11;
reg     [15:0] reg_12;
reg     [15:0] reg_13;
reg     [15:0] reg_14;
reg     [15:0] reg_15;
reg     [15:0] reg_16;
reg     [15:0] reg_17;
reg     [15:0] reg_18;
reg     [15:0] reg_19;
reg     [15:0] reg_20;
reg     [15:0] reg_21;
reg     [15:0] reg_22;
reg     [15:0] reg_23;
reg     [15:0] reg_24;
reg     [15:0] reg_25;
reg     [15:0] reg_26;
reg     [15:0] reg_27;
reg     [15:0] reg_28;
reg     [15:0] reg_29;
reg     [15:0] reg_30;
reg     [15:0] reg_31;
//  MDIO Registers
//  --------------
 
always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      reg_0 <= {16{1'b 0}};
      reg_1 <= {16{1'b 0}};
      reg_2 <= {16{1'b 0}};
      reg_3 <= {16{1'b 0}};
      reg_4 <= {16{1'b 0}};
      reg_5 <= {16{1'b 0}};
      reg_6 <= {16{1'b 0}};
      reg_7 <= {16{1'b 0}};
      reg_8 <= {16{1'b 0}};
      reg_9 <= {16{1'b 0}};
      reg_10 <= {16{1'b 0}};
      reg_11 <= {16{1'b 0}};
      reg_12 <= {16{1'b 0}};
      reg_13 <= {16{1'b 0}};
      reg_14 <= {16{1'b 0}};
      reg_15 <= {16{1'b 0}};
      reg_16 <= {16{1'b 0}};
      reg_17 <= {16{1'b 0}};
      reg_18 <= {16{1'b 0}};
      reg_19 <= {16{1'b 0}};
      reg_20 <= {16{1'b 0}};
      reg_21 <= {16{1'b 0}};
      reg_22 <= {16{1'b 0}};
      reg_23 <= {16{1'b 0}};
      reg_24 <= {16{1'b 0}};
      reg_25 <= {16{1'b 0}};
      reg_26 <= {16{1'b 0}};
      reg_27 <= {16{1'b 0}};
      reg_28 <= {16{1'b 0}};
      reg_29 <= {16{1'b 0}};
      reg_30 <= {16{1'b 0}};
      reg_31 <= {16{1'b 0}};
      conf_done <= 1'b 0;
      end
   else
      begin
      if (reg_write == 1'b 1)
         begin
         if (reg_addr == 5'b 00000)
            begin
            reg_0 <= reg_din;
            conf_done <= 1'b 1;
            end
         else if (reg_addr == 5'b 00001 )
            begin
            reg_1 <= reg_din;
            end
         else if (reg_addr == 5'b 00010 )
            begin
            reg_2 <= reg_din;
            end
         else if (reg_addr == 5'b 00011 )
            begin
            reg_3 <= reg_din;
            end
         else if (reg_addr == 5'b 00100 )
            begin
            reg_4 <= reg_din;
            end
         else if (reg_addr == 5'b 00101 )
            begin
            reg_5 <= reg_din;
            end
         else if (reg_addr == 5'b 00110 )
            begin
            reg_6 <= reg_din;
            end
         else if (reg_addr == 5'b 00111 )
            begin
            reg_7 <= reg_din;
            end
         else if (reg_addr == 5'b 01000 )
            begin
            reg_8 <= reg_din;
            end
         else if (reg_addr == 5'b 01001 )
            begin
            reg_9 <= reg_din;
            end
         else if (reg_addr == 5'b 01010 )
            begin
            reg_10 <= reg_din;
            end
         else if (reg_addr == 5'b 01011 )
            begin
            reg_11 <= reg_din;
            end
         else if (reg_addr == 5'b 01100 )
            begin
            reg_12 <= reg_din;
            end
         else if (reg_addr == 5'b 01101 )
            begin
            reg_13 <= reg_din;
            end
         else if (reg_addr == 5'b 01110 )
            begin
            reg_14 <= reg_din;
            end
         else if (reg_addr == 5'b 01111 )
            begin
            reg_15 <= reg_din;
            end
         else if (reg_addr == 5'b 10000 )
            begin
            reg_16 <= reg_din;
            end
         else if (reg_addr == 5'b 10001 )
            begin
            reg_17 <= reg_din;
            end
         else if (reg_addr == 5'b 10010 )
            begin
            reg_18 <= reg_din;
            end
         else if (reg_addr == 5'b 10011 )
            begin
            reg_19 <= reg_din;
            end
         else if (reg_addr == 5'b 10100 )
            begin
            reg_20 <= reg_din;
            end
         else if (reg_addr == 5'b 10101 )
            begin
            reg_21 <= reg_din;
            end
         else if (reg_addr == 5'b 10110 )
            begin
            reg_22 <= reg_din;
            end
         else if (reg_addr == 5'b 10111 )
            begin
            reg_23 <= reg_din;
            end
         else if (reg_addr == 5'b 11000 )
            begin
            reg_24 <= reg_din;
            end
         else if (reg_addr == 5'b 11001 )
            begin
            reg_25 <= reg_din;
            end
         else if (reg_addr == 5'b 11010 )
            begin
            reg_26 <= reg_din;
            end
         else if (reg_addr == 5'b 11011 )
            begin
            reg_27 <= reg_din;
            end
         else if (reg_addr == 5'b 11100 )
            begin
            reg_28 <= reg_din;
            end
         else if (reg_addr == 5'b 11101 )
            begin
            reg_29 <= reg_din;
            end
         else if (reg_addr == 5'b 11110 )
            begin
            reg_30 <= reg_din;
            end
         else if (reg_addr == 5'b 11111 )
            begin
            reg_31 <= reg_din;
            end
         end
      end
   end
//  Data MUX
//  --------
always @(reg_addr or reg_write)
   begin : process_2
   if (reg_addr == 5'b 00000)
      begin
      reg_dout <= reg_0;
      end
   else if (reg_addr == 5'b 00001 )
      begin
      reg_dout <= reg_1;
      end
   else if (reg_addr == 5'b 00010 )
      begin
      reg_dout <= reg_2;
      end
   else if (reg_addr == 5'b 00011 )
      begin
      reg_dout <= reg_3;
      end
   else if (reg_addr == 5'b 00100 )
      begin
      reg_dout <= reg_4;
      end
   else if (reg_addr == 5'b 00101 )
      begin
      reg_dout <= reg_5;
      end
   else if (reg_addr == 5'b 00110 )
      begin
      reg_dout <= reg_6;
      end
   else if (reg_addr == 5'b 00111 )
      begin
      reg_dout <= reg_7;
      end
   else if (reg_addr == 5'b 01000 )
      begin
      reg_dout <= reg_8;
      end
   else if (reg_addr == 5'b 01001 )
      begin
      reg_dout <= reg_9;
      end
   else if (reg_addr == 5'b 01010 )
      begin
      reg_dout <= reg_10;
      end
   else if (reg_addr == 5'b 01011 )
      begin
      reg_dout <= reg_11;
      end
   else if (reg_addr == 5'b 01100 )
      begin
      reg_dout <= reg_12;
      end
   else if (reg_addr == 5'b 01101 )
      begin
      reg_dout <= reg_13;
      end
   else if (reg_addr == 5'b 01110 )
      begin
      reg_dout <= reg_14;
      end
   else if (reg_addr == 5'b 01111 )
      begin
      reg_dout <= reg_15;
      end
   else if (reg_addr == 5'b 10000 )
      begin
      reg_dout <= reg_16;
      end
   else if (reg_addr == 5'b 10001 )
      begin
      reg_dout <= reg_17;
      end
   else if (reg_addr == 5'b 10010 )
      begin
      reg_dout <= reg_18;
      end
   else if (reg_addr == 5'b 10011 )
      begin
      reg_dout <= reg_19;
      end
   else if (reg_addr == 5'b 10100 )
      begin
      reg_dout <= reg_20;
      end
   else if (reg_addr == 5'b 10101 )
      begin
      reg_dout <= reg_21;
      end
   else if (reg_addr == 5'b 10110 )
      begin
      reg_dout <= reg_22;
      end
   else if (reg_addr == 5'b 10111 )
      begin
      reg_dout <= reg_23;
      end
   else if (reg_addr == 5'b 11000 )
      begin
      reg_dout <= reg_24;
      end
   else if (reg_addr == 5'b 11001 )
      begin
      reg_dout <= reg_25;
      end
   else if (reg_addr == 5'b 11010 )
      begin
      reg_dout <= reg_26;
      end
   else if (reg_addr == 5'b 11011 )
      begin
      reg_dout <= reg_27;
      end
   else if (reg_addr == 5'b 11100 )
      begin
      reg_dout <= reg_28;
      end
   else if (reg_addr == 5'b 11101 )
      begin
      reg_dout <= reg_29;
      end
   else if (reg_addr == 5'b 11110 )
      begin
      reg_dout <= reg_30;
      end
   else if (reg_addr == 5'b 11111 )
      begin
      reg_dout <= reg_31;
      end
   end
 
 
endmodule // module mdio_reg_sim
 

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [mdio_reg.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: $`
7			`// $Source: $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// MDIO Slave's Register Map`
19			`// Instantiated in top_mdio_slave (top_mdio_slave.v)`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps
29			//`include "common_header.verilog"
30
31			`module mdio_reg_sim (reset,`
32			`clk,`
33			`reg_addr,`
34			`reg_write,`
35			`reg_read,`
36			`reg_dout,`
37			`reg_din,`
38			`conf_done);`
39			`input reset;`
40			`input clk; // MDIO 2.5MHz Clock`
41			`input [4:0] reg_addr; // Address Register`
42			`input reg_write; // Write Register`
43			`input reg_read; // Read Register`
44			`output [15:0] reg_dout; // Data Bus OUT`
45			`input [15:0] reg_din; // Data Bus IN`
46			`output conf_done; // PHY Config Done`
47			`reg [15:0] reg_dout;`
48			`// Status`
49			`// ------`
50			`reg conf_done;`
51			`reg [15:0] reg_0;`
52			`reg [15:0] reg_1;`
53			`reg [15:0] reg_2;`
54			`reg [15:0] reg_3;`
55			`reg [15:0] reg_4;`
56			`reg [15:0] reg_5;`
57			`reg [15:0] reg_6;`
58			`reg [15:0] reg_7;`
59			`reg [15:0] reg_8;`
60			`reg [15:0] reg_9;`
61			`reg [15:0] reg_10;`
62			`reg [15:0] reg_11;`
63			`reg [15:0] reg_12;`
64			`reg [15:0] reg_13;`
65			`reg [15:0] reg_14;`
66			`reg [15:0] reg_15;`
67			`reg [15:0] reg_16;`
68			`reg [15:0] reg_17;`
69			`reg [15:0] reg_18;`
70			`reg [15:0] reg_19;`
71			`reg [15:0] reg_20;`
72			`reg [15:0] reg_21;`
73			`reg [15:0] reg_22;`
74			`reg [15:0] reg_23;`
75			`reg [15:0] reg_24;`
76			`reg [15:0] reg_25;`
77			`reg [15:0] reg_26;`
78			`reg [15:0] reg_27;`
79			`reg [15:0] reg_28;`
80			`reg [15:0] reg_29;`
81			`reg [15:0] reg_30;`
82			`reg [15:0] reg_31;`
83			`// MDIO Registers`
84			`// --------------`
85
86			`always @(posedge reset or posedge clk)`
87			`begin : process_1`
88			`if (reset == 1'b 1)`
89			`begin`
90			`reg_0 <= {16{1'b 0}};`
91			`reg_1 <= {16{1'b 0}};`
92			`reg_2 <= {16{1'b 0}};`
93			`reg_3 <= {16{1'b 0}};`
94			`reg_4 <= {16{1'b 0}};`
95			`reg_5 <= {16{1'b 0}};`
96			`reg_6 <= {16{1'b 0}};`
97			`reg_7 <= {16{1'b 0}};`
98			`reg_8 <= {16{1'b 0}};`
99			`reg_9 <= {16{1'b 0}};`
100			`reg_10 <= {16{1'b 0}};`
101			`reg_11 <= {16{1'b 0}};`
102			`reg_12 <= {16{1'b 0}};`
103			`reg_13 <= {16{1'b 0}};`
104			`reg_14 <= {16{1'b 0}};`
105			`reg_15 <= {16{1'b 0}};`
106			`reg_16 <= {16{1'b 0}};`
107			`reg_17 <= {16{1'b 0}};`
108			`reg_18 <= {16{1'b 0}};`
109			`reg_19 <= {16{1'b 0}};`
110			`reg_20 <= {16{1'b 0}};`
111			`reg_21 <= {16{1'b 0}};`
112			`reg_22 <= {16{1'b 0}};`
113			`reg_23 <= {16{1'b 0}};`
114			`reg_24 <= {16{1'b 0}};`
115			`reg_25 <= {16{1'b 0}};`
116			`reg_26 <= {16{1'b 0}};`
117			`reg_27 <= {16{1'b 0}};`
118			`reg_28 <= {16{1'b 0}};`
119			`reg_29 <= {16{1'b 0}};`
120			`reg_30 <= {16{1'b 0}};`
121			`reg_31 <= {16{1'b 0}};`
122			`conf_done <= 1'b 0;`
123			`end`
124			`else`
125			`begin`
126			`if (reg_write == 1'b 1)`
127			`begin`
128			`if (reg_addr == 5'b 00000)`
129			`begin`
130			`reg_0 <= reg_din;`
131			`conf_done <= 1'b 1;`
132			`end`
133			`else if (reg_addr == 5'b 00001 )`
134			`begin`
135			`reg_1 <= reg_din;`
136			`end`
137			`else if (reg_addr == 5'b 00010 )`
138			`begin`
139			`reg_2 <= reg_din;`
140			`end`
141			`else if (reg_addr == 5'b 00011 )`
142			`begin`
143			`reg_3 <= reg_din;`
144			`end`
145			`else if (reg_addr == 5'b 00100 )`
146			`begin`
147			`reg_4 <= reg_din;`
148			`end`
149			`else if (reg_addr == 5'b 00101 )`
150			`begin`
151			`reg_5 <= reg_din;`
152			`end`
153			`else if (reg_addr == 5'b 00110 )`
154			`begin`
155			`reg_6 <= reg_din;`
156			`end`
157			`else if (reg_addr == 5'b 00111 )`
158			`begin`
159			`reg_7 <= reg_din;`
160			`end`
161			`else if (reg_addr == 5'b 01000 )`
162			`begin`
163			`reg_8 <= reg_din;`
164			`end`
165			`else if (reg_addr == 5'b 01001 )`
166			`begin`
167			`reg_9 <= reg_din;`
168			`end`
169			`else if (reg_addr == 5'b 01010 )`
170			`begin`
171			`reg_10 <= reg_din;`
172			`end`
173			`else if (reg_addr == 5'b 01011 )`
174			`begin`
175			`reg_11 <= reg_din;`
176			`end`
177			`else if (reg_addr == 5'b 01100 )`
178			`begin`
179			`reg_12 <= reg_din;`
180			`end`
181			`else if (reg_addr == 5'b 01101 )`
182			`begin`
183			`reg_13 <= reg_din;`
184			`end`
185			`else if (reg_addr == 5'b 01110 )`
186			`begin`
187			`reg_14 <= reg_din;`
188			`end`
189			`else if (reg_addr == 5'b 01111 )`
190			`begin`
191			`reg_15 <= reg_din;`
192			`end`
193			`else if (reg_addr == 5'b 10000 )`
194			`begin`
195			`reg_16 <= reg_din;`
196			`end`
197			`else if (reg_addr == 5'b 10001 )`
198			`begin`
199			`reg_17 <= reg_din;`
200			`end`
201			`else if (reg_addr == 5'b 10010 )`
202			`begin`
203			`reg_18 <= reg_din;`
204			`end`
205			`else if (reg_addr == 5'b 10011 )`
206			`begin`
207			`reg_19 <= reg_din;`
208			`end`
209			`else if (reg_addr == 5'b 10100 )`
210			`begin`
211			`reg_20 <= reg_din;`
212			`end`
213			`else if (reg_addr == 5'b 10101 )`
214			`begin`
215			`reg_21 <= reg_din;`
216			`end`
217			`else if (reg_addr == 5'b 10110 )`
218			`begin`
219			`reg_22 <= reg_din;`
220			`end`
221			`else if (reg_addr == 5'b 10111 )`
222			`begin`
223			`reg_23 <= reg_din;`
224			`end`
225			`else if (reg_addr == 5'b 11000 )`
226			`begin`
227			`reg_24 <= reg_din;`
228			`end`
229			`else if (reg_addr == 5'b 11001 )`
230			`begin`
231			`reg_25 <= reg_din;`
232			`end`
233			`else if (reg_addr == 5'b 11010 )`
234			`begin`
235			`reg_26 <= reg_din;`
236			`end`
237			`else if (reg_addr == 5'b 11011 )`
238			`begin`
239			`reg_27 <= reg_din;`
240			`end`
241			`else if (reg_addr == 5'b 11100 )`
242			`begin`
243			`reg_28 <= reg_din;`
244			`end`
245			`else if (reg_addr == 5'b 11101 )`
246			`begin`
247			`reg_29 <= reg_din;`
248			`end`
249			`else if (reg_addr == 5'b 11110 )`
250			`begin`
251			`reg_30 <= reg_din;`
252			`end`
253			`else if (reg_addr == 5'b 11111 )`
254			`begin`
255			`reg_31 <= reg_din;`
256			`end`
257			`end`
258			`end`
259			`end`
260			`// Data MUX`
261			`// --------`
262			`always @(reg_addr or reg_write)`
263			`begin : process_2`
264			`if (reg_addr == 5'b 00000)`
265			`begin`
266			`reg_dout <= reg_0;`
267			`end`
268			`else if (reg_addr == 5'b 00001 )`
269			`begin`
270			`reg_dout <= reg_1;`
271			`end`
272			`else if (reg_addr == 5'b 00010 )`
273			`begin`
274			`reg_dout <= reg_2;`
275			`end`
276			`else if (reg_addr == 5'b 00011 )`
277			`begin`
278			`reg_dout <= reg_3;`
279			`end`
280			`else if (reg_addr == 5'b 00100 )`
281			`begin`
282			`reg_dout <= reg_4;`
283			`end`
284			`else if (reg_addr == 5'b 00101 )`
285			`begin`
286			`reg_dout <= reg_5;`
287			`end`
288			`else if (reg_addr == 5'b 00110 )`
289			`begin`
290			`reg_dout <= reg_6;`
291			`end`
292			`else if (reg_addr == 5'b 00111 )`
293			`begin`
294			`reg_dout <= reg_7;`
295			`end`
296			`else if (reg_addr == 5'b 01000 )`
297			`begin`
298			`reg_dout <= reg_8;`
299			`end`
300			`else if (reg_addr == 5'b 01001 )`
301			`begin`
302			`reg_dout <= reg_9;`
303			`end`
304			`else if (reg_addr == 5'b 01010 )`
305			`begin`
306			`reg_dout <= reg_10;`
307			`end`
308			`else if (reg_addr == 5'b 01011 )`
309			`begin`
310			`reg_dout <= reg_11;`
311			`end`
312			`else if (reg_addr == 5'b 01100 )`
313			`begin`
314			`reg_dout <= reg_12;`
315			`end`
316			`else if (reg_addr == 5'b 01101 )`
317			`begin`
318			`reg_dout <= reg_13;`
319			`end`
320			`else if (reg_addr == 5'b 01110 )`
321			`begin`
322			`reg_dout <= reg_14;`
323			`end`
324			`else if (reg_addr == 5'b 01111 )`
325			`begin`
326			`reg_dout <= reg_15;`
327			`end`
328			`else if (reg_addr == 5'b 10000 )`
329			`begin`
330			`reg_dout <= reg_16;`
331			`end`
332			`else if (reg_addr == 5'b 10001 )`
333			`begin`
334			`reg_dout <= reg_17;`
335			`end`
336			`else if (reg_addr == 5'b 10010 )`
337			`begin`
338			`reg_dout <= reg_18;`
339			`end`
340			`else if (reg_addr == 5'b 10011 )`
341			`begin`
342			`reg_dout <= reg_19;`
343			`end`
344			`else if (reg_addr == 5'b 10100 )`
345			`begin`
346			`reg_dout <= reg_20;`
347			`end`
348			`else if (reg_addr == 5'b 10101 )`
349			`begin`
350			`reg_dout <= reg_21;`
351			`end`
352			`else if (reg_addr == 5'b 10110 )`
353			`begin`
354			`reg_dout <= reg_22;`
355			`end`
356			`else if (reg_addr == 5'b 10111 )`
357			`begin`
358			`reg_dout <= reg_23;`
359			`end`
360			`else if (reg_addr == 5'b 11000 )`
361			`begin`
362			`reg_dout <= reg_24;`
363			`end`
364			`else if (reg_addr == 5'b 11001 )`
365			`begin`
366			`reg_dout <= reg_25;`
367			`end`
368			`else if (reg_addr == 5'b 11010 )`
369			`begin`
370			`reg_dout <= reg_26;`
371			`end`
372			`else if (reg_addr == 5'b 11011 )`
373			`begin`
374			`reg_dout <= reg_27;`
375			`end`
376			`else if (reg_addr == 5'b 11100 )`
377			`begin`
378			`reg_dout <= reg_28;`
379			`end`
380			`else if (reg_addr == 5'b 11101 )`
381			`begin`
382			`reg_dout <= reg_29;`
383			`end`
384			`else if (reg_addr == 5'b 11110 )`
385			`begin`
386			`reg_dout <= reg_30;`
387			`end`
388			`else if (reg_addr == 5'b 11111 )`
389			`begin`
390			`reg_dout <= reg_31;`
391			`end`
392			`end`
393
394
395			`endmodule // module mdio_reg_sim`
396