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jefflieu |
// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: $
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// $Source: $
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//
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// Check in by : $Author: max $
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// Author : SKNg/TTChong
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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// Description : (Simulation only)
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//
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// MDIO slave's register interface controller
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// Instantiated in top_mdio_slave (top_mdio_slave.v)
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//
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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`timescale 1 ns / 10 ps
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//`include "common_header.verilog"
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module mdio_slave (reset,
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mdc,
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mdio,
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dev_addr,
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reg_addr,
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reg_read,
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reg_write,
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reg_dout,
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reg_din);
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input reset; // asynch reset
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input mdc; // system clock
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inout mdio; // Data Bus
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input [4:0] dev_addr; // Device address
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output [4:0] reg_addr; // Address register
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output reg_read; // Read register
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output reg_write; // Write register
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output [15:0] reg_dout; // Data Bus OUT
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input [15:0] reg_din; // Data Bus IN
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wire VHDL2V_mdio;
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wire mdio;
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wire [4:0] reg_addr;
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wire reg_read;
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wire reg_write;
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wire [15:0] reg_dout;
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reg [4:0] phy_add; // Phy Address
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reg [4:0] reg_add; // Register Address
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reg [15:0] reg_out; // Register data out
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reg [15:0] reg_in; // Register data in
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reg en_phy_add; // Write phy Address
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reg en_reg_add; // Write register Address
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reg en_data_out; // Write register data out
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wire en_data_in; // Write register data in
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wire shift_data_in; // Send register data in
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wire phy_add_ok; // Phy Address correct
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reg [4:0] cnt_32; // Frame Bit counter
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wire run_cnt_32; // Run Frame Bit counter
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wire ok_32; // Preambule length reached
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wire ok_16; // Data length reached
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wire ok_10; // Reg address length reach
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wire ok_5; // Phy address length reach
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reg cd_oe; // Output Enable command
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wire mux_0; // Mux zero
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reg mdio_wait; // Wait state of State machine
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reg [16:0] mdio_run; // State machine core
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// =====================================================================
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// Data logic structure
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// =====================================================================
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always @(posedge mdc or posedge reset)
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begin : p_data
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if (reset == 1'b 1)
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begin
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phy_add <= {5{1'b 0}}; // Phy Address
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reg_add <= {5{1'b 0}}; // Register Address
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reg_out <= {16{1'b 0}}; // Register data out
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reg_in <= {16{1'b 0}}; // Register data in
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//
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cnt_32 <= {5{1'b 0}}; // Frame Bit counter
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//
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end
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else
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begin
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// ----------------------
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// Phy Address
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// ----------------------
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if (en_phy_add == 1'b 1)
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begin
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phy_add[4:0] <= {phy_add[3:0], mdio};
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end
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else
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begin
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phy_add <= phy_add;
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end
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// ----------------------
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// -----------------------
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// Register Address
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// -----------------------
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if (en_reg_add == 1'b 1)
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begin
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reg_add[4:0] <= {reg_add[3:0], mdio};
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end
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else
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begin
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reg_add <= reg_add;
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end
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// -----------------------
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// -----------------------
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// Register data out
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// -----------------------
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if (en_data_out == 1'b 1)
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begin
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reg_out[15:0] <= {reg_out[14:0], mdio};
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end
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else
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begin
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reg_out <= reg_out;
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end
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// -----------------------
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// -----------------------------------------
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// Register data in
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// -----------------------------------------
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if (en_data_in == 1'b 1)
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begin
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reg_in[15:0] <= reg_din;
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end
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else if (shift_data_in == 1'b 1 )
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begin
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reg_in[15:1] <= reg_in[14:0];
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end
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else
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begin
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reg_in <= reg_in;
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end
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//
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// ------------------------------------------
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// --------------------
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// Frame Bit counter
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// -------------------
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if (run_cnt_32 == 1'b 1)
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begin
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cnt_32 <= cnt_32 + 1'b 1;
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end
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else
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begin
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cnt_32 <= 5'b 00000;
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end
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// -------------------
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end
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end
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//
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// --------------------------
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// Phy Address correct
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// --------------------------
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assign phy_add_ok = phy_add == dev_addr ? 1'b 1 :
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1'b 0;
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//
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// ---------------------------
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// Preambule length reached
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// ---------------------------
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assign ok_32 = cnt_32 == 5'b 11110 ? 1'b 1 :
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1'b 0;
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//
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// --------------------------
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// Data length reached
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// --------------------------
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assign ok_16 = cnt_32 == 5'b 01111 ? 1'b 1 :
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1'b 0;
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//
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// --------------------------
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// Reg address length reach
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// --------------------------
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assign ok_10 = cnt_32 == 5'b 01010 ? 1'b 1 :
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1'b 0;
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//
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// --------------------------
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// Phy address length reach
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// --------------------------
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assign ok_5 = cnt_32 == 5'b 00101 ? 1'b 1 :
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1'b 0;
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//
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// ----------------------
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// -- Address register
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// ----------------------
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assign reg_addr = reg_add;
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//
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// ----------------------
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// Data Bus OUT
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// ----------------------
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assign reg_dout = reg_out;
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//
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// ----------------------
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// Mux zero
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// ----------------------
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assign mux_0 = mdio_run[8] == 1'b 1 ? 1'b 0 :
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reg_in[15];
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//
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// ----------------------
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// Data Bus
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// ----------------------
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assign #(5) mdio = cd_oe == 1'b 0 ? mux_0 :
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1'b Z;
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//
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// =====================================================================
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// =====================================================================
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// State machine body
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// =====================================================================
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always @(posedge mdc or posedge reset)
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begin : p_state
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if (reset == 1'b 1)
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begin
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mdio_wait <= 1'b 1; // Wait state of State machine
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mdio_run <= {17{1'b 0}}; // State machine core
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//
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cd_oe <= 1'b 1; // Output Enable command
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//
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en_phy_add <= 1'b 0; // Write phy Address
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en_reg_add <= 1'b 0; // Write register Address
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en_data_out <= 1'b 0; // Write register data out
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//
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//
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end
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else
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begin
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// --------------------------------------
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// wait for a frame
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// --------------------------------------
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if (mdio_wait == 1'b 1 & mdio == 1'b 0 |
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mdio_run[0] == 1'b 1 & mdio == 1'b 0 |
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mdio_run[2] == 1'b 1 & mdio == 1'b 0 |
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mdio_run[4] == 1'b 1 & mdio == 1'b 1 |
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mdio_run[6] == 1'b 1 & phy_add_ok == 1'b 0 |
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mdio_run[7] == 1'b 1 & mdio == 1'b 0 |
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mdio_run[9] == 1'b 1 & ok_16 == 1'b 1 |
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mdio_run[10] == 1'b 1 & mdio == 1'b 0 |
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mdio_run[12] == 1'b 1 & phy_add_ok == 1'b 0 |
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mdio_run[13] == 1'b 1 & mdio == 1'b 0 |
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mdio_run[14] == 1'b 1 & mdio == 1'b 1 |
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mdio_run[16] == 1'b 1 | mdio_run[0] == 1'b 0 &
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mdio_run[1] == 1'b 0 & mdio_run[2] == 1'b 0 &
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mdio_run[3] == 1'b 0 & mdio_run[4] == 1'b 0 &
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mdio_run[5] == 1'b 0 & mdio_run[6] == 1'b 0 &
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mdio_run[7] == 1'b 0 & mdio_run[8] == 1'b 0 &
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mdio_run[9] == 1'b 0 & mdio_run[10] == 1'b 0 &
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mdio_run[11] == 1'b 0 & mdio_run[12] == 1'b 0 &
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mdio_run[13] == 1'b 0 & mdio_run[14] == 1'b 0 &
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mdio_run[15] == 1'b 0 & mdio_run[16] == 1'b 0)
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begin
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mdio_wait <= 1'b 1;
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end
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else
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begin
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mdio_wait <= 1'b 0;
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end
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//
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// --------------------------------------------
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// Check preambule
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// --------------------------------------------
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if (mdio_wait == 1'b 1 & mdio == 1'b 1 |
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mdio_run[0] == 1'b 1 & mdio == 1'b 1 &
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ok_32 == 1'b 0)
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begin
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mdio_run[0] <= 1'b 1;
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end
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else
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begin
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mdio_run[0] <= 1'b 0;
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end
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//
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if (mdio_run[0] == 1'b 1 & mdio == 1'b 1 &
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ok_32 == 1'b 1 | mdio_run[1] == 1'b 1 &
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mdio == 1'b 1)
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begin
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mdio_run[1] <= 1'b 1;
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end
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else
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begin
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mdio_run[1] <= 1'b 0;
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end
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| 290 |
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// --------------------------------------------
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// Check ST
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// --------------------------------------------
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if (mdio_run[1] == 1'b 1 & mdio == 1'b 0)
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begin
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mdio_run[2] <= 1'b 1;
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end
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| 297 |
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else
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| 298 |
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begin
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| 299 |
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mdio_run[2] <= 1'b 0;
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end
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| 301 |
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//
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| 302 |
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if (mdio_run[2] == 1'b 1 & mdio == 1'b 1)
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begin
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| 304 |
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mdio_run[3] <= 1'b 1;
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| 305 |
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end
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| 306 |
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else
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| 307 |
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begin
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| 308 |
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mdio_run[3] <= 1'b 0;
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| 309 |
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end
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| 310 |
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// --------------------------------------------
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| 311 |
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// Check OP
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| 312 |
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// --------------------------------------------
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| 313 |
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if (mdio_run[3] == 1'b 1 & mdio == 1'b 1)
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| 314 |
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begin
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| 315 |
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mdio_run[4] <= 1'b 1;
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| 316 |
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end
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| 317 |
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else
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| 318 |
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begin
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| 319 |
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mdio_run[4] <= 1'b 0;
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| 320 |
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end
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| 321 |
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// --------------------------------------------
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| 322 |
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// Read OP
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| 323 |
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// --------------------------------------------
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| 324 |
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if (mdio_run[4] == 1'b 1 & mdio == 1'b 0 |
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| 325 |
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mdio_run[5] == 1'b 1 & ok_5 == 1'b 0)
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| 326 |
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begin
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mdio_run[5] <= 1'b 1;
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| 328 |
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end
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| 329 |
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else
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| 330 |
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begin
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| 331 |
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mdio_run[5] <= 1'b 0;
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| 332 |
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end
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| 333 |
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//
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| 334 |
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if (mdio_run[5] == 1'b 1 & ok_5 == 1'b 1 |
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mdio_run[6] == 1'b 1 & ok_10 == 1'b 0 &
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| 336 |
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phy_add_ok == 1'b 1)
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| 337 |
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begin
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| 338 |
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mdio_run[6] <= 1'b 1;
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| 339 |
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end
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| 340 |
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else
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| 341 |
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begin
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| 342 |
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mdio_run[6] <= 1'b 0;
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| 343 |
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end
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| 344 |
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//
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| 345 |
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if (mdio_run[6] == 1'b 1 & ok_10 == 1'b 1 &
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| 346 |
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phy_add_ok == 1'b 1)
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| 347 |
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begin
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| 348 |
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mdio_run[7] <= 1'b 1;
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| 349 |
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end
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| 350 |
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else
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| 351 |
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begin
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| 352 |
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mdio_run[7] <= 1'b 0;
|
| 353 |
|
|
end
|
| 354 |
|
|
//
|
| 355 |
|
|
if (mdio_run[7] == 1'b 1 & mdio != 1'b 0)
|
| 356 |
|
|
begin
|
| 357 |
|
|
mdio_run[8] <= 1'b 1;
|
| 358 |
|
|
end
|
| 359 |
|
|
else
|
| 360 |
|
|
begin
|
| 361 |
|
|
mdio_run[8] <= 1'b 0;
|
| 362 |
|
|
end
|
| 363 |
|
|
//
|
| 364 |
|
|
if (mdio_run[8] == 1'b 1 | mdio_run[9] == 1'b 1 &
|
| 365 |
|
|
ok_16 == 1'b 0)
|
| 366 |
|
|
begin
|
| 367 |
|
|
mdio_run[9] <= 1'b 1;
|
| 368 |
|
|
end
|
| 369 |
|
|
else
|
| 370 |
|
|
begin
|
| 371 |
|
|
mdio_run[9] <= 1'b 0;
|
| 372 |
|
|
end
|
| 373 |
|
|
//
|
| 374 |
|
|
// --------------------------------------------
|
| 375 |
|
|
// Write OP
|
| 376 |
|
|
// --------------------------------------------
|
| 377 |
|
|
if (mdio_run[3] == 1'b 1 & mdio == 1'b 0)
|
| 378 |
|
|
begin
|
| 379 |
|
|
mdio_run[10] <= 1'b 1;
|
| 380 |
|
|
end
|
| 381 |
|
|
else
|
| 382 |
|
|
begin
|
| 383 |
|
|
mdio_run[10] <= 1'b 0;
|
| 384 |
|
|
end
|
| 385 |
|
|
//
|
| 386 |
|
|
if (mdio_run[10] == 1'b 1 & mdio == 1'b 1 |
|
| 387 |
|
|
mdio_run[11] == 1'b 1 & ok_5 == 1'b 0)
|
| 388 |
|
|
begin
|
| 389 |
|
|
mdio_run[11] <= 1'b 1;
|
| 390 |
|
|
end
|
| 391 |
|
|
else
|
| 392 |
|
|
begin
|
| 393 |
|
|
mdio_run[11] <= 1'b 0;
|
| 394 |
|
|
end
|
| 395 |
|
|
//
|
| 396 |
|
|
if (mdio_run[11] == 1'b 1 & ok_5 == 1'b 1 |
|
| 397 |
|
|
mdio_run[12] == 1'b 1 & ok_10 == 1'b 0 &
|
| 398 |
|
|
phy_add_ok == 1'b 1)
|
| 399 |
|
|
begin
|
| 400 |
|
|
mdio_run[12] <= 1'b 1;
|
| 401 |
|
|
end
|
| 402 |
|
|
else
|
| 403 |
|
|
begin
|
| 404 |
|
|
mdio_run[12] <= 1'b 0;
|
| 405 |
|
|
end
|
| 406 |
|
|
//
|
| 407 |
|
|
if (mdio_run[12] == 1'b 1 & ok_10 == 1'b 1 &
|
| 408 |
|
|
phy_add_ok == 1'b 1)
|
| 409 |
|
|
begin
|
| 410 |
|
|
mdio_run[13] <= 1'b 1;
|
| 411 |
|
|
end
|
| 412 |
|
|
else
|
| 413 |
|
|
begin
|
| 414 |
|
|
mdio_run[13] <= 1'b 0;
|
| 415 |
|
|
end
|
| 416 |
|
|
//
|
| 417 |
|
|
if (mdio_run[13] == 1'b 1 & mdio == 1'b 1)
|
| 418 |
|
|
begin
|
| 419 |
|
|
mdio_run[14] <= 1'b 1;
|
| 420 |
|
|
end
|
| 421 |
|
|
else
|
| 422 |
|
|
begin
|
| 423 |
|
|
mdio_run[14] <= 1'b 0;
|
| 424 |
|
|
end
|
| 425 |
|
|
//
|
| 426 |
|
|
if (mdio_run[14] == 1'b 1 & mdio == 1'b 0 |
|
| 427 |
|
|
mdio_run[15] == 1'b 1 & ok_16 == 1'b 0)
|
| 428 |
|
|
begin
|
| 429 |
|
|
mdio_run[15] <= 1'b 1;
|
| 430 |
|
|
end
|
| 431 |
|
|
else
|
| 432 |
|
|
begin
|
| 433 |
|
|
mdio_run[15] <= 1'b 0;
|
| 434 |
|
|
end
|
| 435 |
|
|
//
|
| 436 |
|
|
if (mdio_run[15] == 1'b 1 & ok_16 == 1'b 1)
|
| 437 |
|
|
begin
|
| 438 |
|
|
mdio_run[16] <= 1'b 1;
|
| 439 |
|
|
end
|
| 440 |
|
|
else
|
| 441 |
|
|
begin
|
| 442 |
|
|
mdio_run[16] <= 1'b 0;
|
| 443 |
|
|
end
|
| 444 |
|
|
//
|
| 445 |
|
|
// ----------------------------
|
| 446 |
|
|
// --------------------
|
| 447 |
|
|
// Write phy Address
|
| 448 |
|
|
// --------------------
|
| 449 |
|
|
if (mdio_run[4] == 1'b 1 & mdio == 1'b 0 |
|
| 450 |
|
|
mdio_run[5] == 1'b 1 & ok_5 == 1'b 0 |
|
| 451 |
|
|
mdio_run[10] == 1'b 1 & mdio == 1'b 1 |
|
| 452 |
|
|
mdio_run[11] == 1'b 1 & ok_5 == 1'b 0)
|
| 453 |
|
|
begin
|
| 454 |
|
|
en_phy_add <= 1'b 1;
|
| 455 |
|
|
end
|
| 456 |
|
|
else
|
| 457 |
|
|
begin
|
| 458 |
|
|
en_phy_add <= 1'b 0;
|
| 459 |
|
|
end
|
| 460 |
|
|
//
|
| 461 |
|
|
// -------------------
|
| 462 |
|
|
// --------------------------
|
| 463 |
|
|
// Write register Address
|
| 464 |
|
|
// --------------------------
|
| 465 |
|
|
if (mdio_run[5] == 1'b 1 & ok_5 == 1'b 1 |
|
| 466 |
|
|
mdio_run[6] == 1'b 1 & ok_10 == 1'b 0 |
|
| 467 |
|
|
mdio_run[11] == 1'b 1 & ok_5 == 1'b 1 |
|
| 468 |
|
|
mdio_run[12] == 1'b 1 & ok_10 == 1'b 0)
|
| 469 |
|
|
begin
|
| 470 |
|
|
en_reg_add <= 1'b 1;
|
| 471 |
|
|
end
|
| 472 |
|
|
else
|
| 473 |
|
|
begin
|
| 474 |
|
|
en_reg_add <= 1'b 0;
|
| 475 |
|
|
end
|
| 476 |
|
|
// ---------------------------
|
| 477 |
|
|
// --------------------------
|
| 478 |
|
|
// Write register data out
|
| 479 |
|
|
// --------------------------
|
| 480 |
|
|
if (mdio_run[14] == 1'b 1 & mdio == 1'b 0 |
|
| 481 |
|
|
mdio_run[15] == 1'b 1 & ok_16 == 1'b 0)
|
| 482 |
|
|
begin
|
| 483 |
|
|
en_data_out <= 1'b 1;
|
| 484 |
|
|
end
|
| 485 |
|
|
else
|
| 486 |
|
|
begin
|
| 487 |
|
|
en_data_out <= 1'b 0;
|
| 488 |
|
|
end
|
| 489 |
|
|
// ---------------------------
|
| 490 |
|
|
// --------------------------
|
| 491 |
|
|
// Output Enable command
|
| 492 |
|
|
// --------------------------
|
| 493 |
|
|
if (mdio_run[7] == 1'b 1 & mdio != 1'b 0 |
|
| 494 |
|
|
mdio_run[8] == 1'b 1 | mdio_run[9] == 1'b 1 &
|
| 495 |
|
|
ok_16 == 1'b 0)
|
| 496 |
|
|
begin
|
| 497 |
|
|
cd_oe <= 1'b 0;
|
| 498 |
|
|
end
|
| 499 |
|
|
else
|
| 500 |
|
|
begin
|
| 501 |
|
|
cd_oe <= 1'b 1;
|
| 502 |
|
|
end
|
| 503 |
|
|
// ---------------------------
|
| 504 |
|
|
end
|
| 505 |
|
|
end
|
| 506 |
|
|
//
|
| 507 |
|
|
// -------------------------
|
| 508 |
|
|
// Write register data in
|
| 509 |
|
|
// -------------------------
|
| 510 |
|
|
assign en_data_in = mdio_run[8];
|
| 511 |
|
|
//
|
| 512 |
|
|
// -------------------------
|
| 513 |
|
|
// Send register data in
|
| 514 |
|
|
// -------------------------
|
| 515 |
|
|
assign shift_data_in = mdio_run[9];
|
| 516 |
|
|
//
|
| 517 |
|
|
// -------------------------
|
| 518 |
|
|
// Read register
|
| 519 |
|
|
// -------------------------
|
| 520 |
|
|
assign reg_read = mdio_run[7] == 1'b 1 & mdio != 1'b 0 |
|
| 521 |
|
|
mdio_run[8] == 1'b 1 ? 1'b 1 :
|
| 522 |
|
|
1'b 0;
|
| 523 |
|
|
//
|
| 524 |
|
|
// -------------------------
|
| 525 |
|
|
// Write register
|
| 526 |
|
|
// -------------------------
|
| 527 |
|
|
assign reg_write = mdio_run[16];
|
| 528 |
|
|
//
|
| 529 |
|
|
// --------------------------------
|
| 530 |
|
|
// Run Frame Bit counter
|
| 531 |
|
|
// ---------------------------------
|
| 532 |
|
|
assign run_cnt_32 = mdio_wait == 1'b 1 & mdio == 1'b 1 |
|
| 533 |
|
|
mdio_run[0] == 1'b 1 & mdio == 1'b 1 &
|
| 534 |
|
|
ok_32 == 1'b 0 | mdio_run[4] == 1'b 1 &
|
| 535 |
|
|
mdio == 1'b 0 | mdio_run[5] == 1'b 1 &
|
| 536 |
|
|
ok_5 == 1'b 0 | mdio_run[5] == 1'b 1 &
|
| 537 |
|
|
ok_5 == 1'b 1 | mdio_run[6] == 1'b 1 &
|
| 538 |
|
|
ok_10 == 1'b 0 | mdio_run[9] == 1'b 1 |
|
| 539 |
|
|
mdio_run[10] == 1'b 1 & mdio == 1'b 1 |
|
| 540 |
|
|
mdio_run[11] == 1'b 1 & ok_5 == 1'b 0 |
|
| 541 |
|
|
mdio_run[11] == 1'b 1 & ok_5 == 1'b 1 |
|
| 542 |
|
|
mdio_run[12] == 1'b 1 & ok_10 == 1'b 0 |
|
| 543 |
|
|
mdio_run[15] == 1'b 1 & ok_16 == 1'b 0 ? 1'b 1 :
|
| 544 |
|
|
1'b 0;
|
| 545 |
|
|
// ---------------------------------
|
| 546 |
|
|
//
|
| 547 |
|
|
// =====================================================================
|
| 548 |
|
|
|
| 549 |
|
|
endmodule // module mdio_slave
|
| 550 |
|
|
|
