URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [top_ethgen32.v] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log


// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: top_ethgen32.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen32.v,v $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// Ethernet Traffic Generator for 32 bit MAC Atlantic client interface
// Instantiates VERILOG module: ethgenerator32 (ethgen32.v)
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps  // timescale for following modules
 
module top_ethgenerator32 (
 
   reset,
   clk,
   enable,
   dout,
   dval,
   derror,
   sop,
   eop,
   tmod,
   mac_reverse,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   cntstart,
   cntstep,
   ipg_len,
   payload_err,
   prmbl_err,
   crc_err,
   vlan_en,
   stack_vlan,
   pause_gen,
   pad_en,
   phy_err,
   end_err,
   data_only,
   start,
   done);
parameter thold = 1.0 ;
parameter ENABLE_SHIFT16 = 1'b 0;
parameter BIG_ENDIAN = 1'b1;
parameter ZERO_LATENCY = 0;
 
input   reset; //  active high
input   clk;
input   enable;
output   [31:0] dout;
output   dval;
output   derror;
output   sop; //  pulse with first word
output   eop; //  pulse with last word (tmod valid)
output   [1:0] tmod; //  last word modulo
input   mac_reverse; //  1: dst/src are sent MSB first (non-standard)
input   [47:0] dst; //  destination address
input   [47:0] src; //  source address
input   [3:0] prmble_len; //  length of preamble
input   [15:0] pquant; //  Pause Quanta value
input   [15:0] vlan_ctl; //  VLAN control info
input   [15:0] len; //  Length of payload
input   [15:0] frmtype; //  if non-null: type field instead length
input   [7:0] cntstart; //  payload data counter start (first byte of payload)
input   [7:0] cntstep; //  payload counter step (2nd byte in paylaod)
input   [15:0] ipg_len;
input   payload_err; //  generate payload pattern error (last payload byte is wrong)
input   prmbl_err; //  Send corrupt SFD in otherwise correct preamble
input   crc_err;
input   vlan_en;
input   stack_vlan;
input   pause_gen;
input   pad_en;
input   phy_err; //  Generate the well known ERROR control character
input   end_err; //  Send corrupt TERMINATE character (wrong code)
input   data_only; //  if set omits preamble, padding, CRC
input   start;
output   done;
wire     [31:0] dout;
reg     [31:0] dout_reg;
wire     dval;
reg     dval_reg;
wire     derror;
reg     derror_reg;
wire    sop;
wire    eop;
//  Frame Contents definitions
wire     [1:0] tmod;
reg     [1:0] tmod_reg;
wire     done;
reg     done_reg;
//  internal GMII from generator
wire    [7:0] rxd;
wire    rx_dv;
wire    rx_er;
wire    sop_gen;
wire    eop_gen;
reg     start_gen;
wire    done_gen;
//  captured signals from generator (lasting 1 word clock cycle)
wire     enable_int;
reg     enable_reg;
reg     sop_int; //  captured sop_gen
wire    sop_int_d; //  captured sop_gen
reg     eop_int; //  captured eop_gen
wire    eop_i; //  captured eop_gen
reg     rx_er_int; //  captured rx_er
//  external signals
reg     sop_ex;
reg     eop_ex;
//  captured command signals 
reg     [15:0] ipg_len_i;
//  internal
reg     [31:0] data32;
wire    [2:0] clkcnt;
reg     [1:0] bytecnt_eop; //  captured count for last word
integer count;
 
//assign output
reg     [31:0] dout_temp;
reg     dval_temp;
reg     derror_temp;
reg     sop_temp;
reg     eop_temp;
reg     [1:0] tmod_temp;
reg     done_temp;
 
 
// TYPE stm_typ:
parameter stm_typ_s_idle = 0;
parameter stm_typ_s_data = 1;
parameter stm_typ_s_ipg = 2;
parameter stm_typ_s_ipg0 = 3;
parameter stm_typ_s_wait = 4;
 
reg     [2:0] state;
reg     clk_d;
reg     fast_clk;
reg     fast_clk_gate;
reg     [1:0] bytecnt;
reg     tx_clk;
 
 
//  ---------------------------------------
//  Generate internal fast clock synchronized to external input clock
//  ---------------------------------------
 
always
   begin : process_1
   fast_clk <= #(0.1) 1'b 0;
   #( 0.4 );
   fast_clk <= #(0.1) 1'b 1;
   #( 0.4 );
   end
 
always @(negedge fast_clk or posedge reset)
   begin : process_2
   if (reset == 1'b 1)
      begin
      fast_clk_gate <= 1'b 0;
      clk_d <= 1'b 0;
      end
   else
      begin
//  work on neg edge
      clk_d <= clk;
      if ((rx_dv == 1'b 0 | done_gen == 1'b 1) &
    (enable_int == 1'b 1 | start_gen == 1'b 1))
         begin
//  generator not running, enable it permanently
         fast_clk_gate <= 1'b 1;
         end
      else if (clk_d == 1'b 0 & clk == 1'b 1 &
    state != stm_typ_s_wait & (enable_int == 1'b 1 |
    state == stm_typ_s_ipg0) )
         begin
//  wait for rising edge
         fast_clk_gate <= 1'b 1;
         end
      else if (bytecnt < 3 )
         begin
//  after 4 octets have been processed, wait for next clk rising edge
         fast_clk_gate <= 1'b 1;
         end
      else
         begin
         fast_clk_gate <= 1'b 0;
         end
      end
   end
//  DDR process to generate gated clock
always @(fast_clk or reset)
   begin : process_3
   if (reset == 1'b 1)
      begin
      tx_clk <= 1'b 0;
      end
   else if ( fast_clk == 1'b 1 )
      begin
      if (fast_clk_gate == 1'b 1)
         begin
         tx_clk <= 1'b 1;
         end
      end
   else if ( fast_clk == 1'b 0 )
      begin
      tx_clk <= 1'b 0;
      end
   end
// tx_clk <= fast_clk and fast_clk_gate;        
//  capture generator signals with word clock domain handshake
//  ----------------------------------------------------------
always @(posedge tx_clk or posedge reset)
   begin : process_4
   if (reset == 1'b 1)
      begin
      eop_int <= 1'b 0;
      sop_int <= 1'b 0;
      rx_er_int <= 1'b 0;
      end
   else
      begin
      if (sop_gen == 1'b 1)
         begin
         sop_int <= 1'b 1;
         end
      else if (sop_ex == 1'b 1 )
         begin
         sop_int <= 1'b 0;
         end
      if (eop_gen == 1'b 1)
         begin
         eop_int <= 1'b 1;
         end
      else if (eop_ex == 1'b 1 )
         begin
         eop_int <= 1'b 0;
         end
      if (rx_er == 1'b 1)
         begin
         rx_er_int <= 1'b 1;
         end
      else if (eop_ex == 1'b 1 )
         begin
         rx_er_int <= 1'b 0;
         end
      end
   end
//  word clock, external signal generation
//  --------------------------------------
//assign #(thold) sop = sop_ex; 
//assign #(thold) eop = eop_ex; 
always @(posedge clk or posedge reset)
   begin : process_5
   if (reset == 1'b 1)
      begin
//      enable_int <= 1'b 0;  
      eop_ex <= 1'b 0;
      sop_ex <= 1'b 0;
      dval_reg <= 1'b 0;
      dout_reg <= {32{1'b 0}};
      tmod_reg <= {2{1'b 0}};
      derror_reg <= 1'b 0;
      start_gen <= 1'b 0;
      ipg_len_i <= 0;
      done_reg <= 1'b 0;
      end
   else
      begin
      eop_ex <= eop_int;
      sop_ex <= sop_int;
      dout_reg <= #(thold) data32;
      derror_reg <= #(thold) rx_er_int;
//      enable_int <= enable; 
      if (done_gen == 1'b 1 & enable_int == 1'b 1 &
    (state == stm_typ_s_idle | state == stm_typ_s_ipg0 |
    state == stm_typ_s_data & eop_int == 1'b 1 &
    ipg_len_i < 4 & start == 1'b 1))
         begin
//  nextstate=S_IPG0
         start_gen <= start;
         end
      else
         begin
         start_gen <= 1'b 0;
         end
      if ((state == stm_typ_s_data | state == stm_typ_s_ipg0) &
    enable_int == 1'b 1 | start_gen == 1'b 1)
         begin
         dval_reg <= #(thold) 1'b 1;
         end
      else
         begin
         dval_reg <= #(thold) 1'b 0;
         end
//  store input variables that could change until end of frame
      if (sop_int == 1'b 1)
         begin
         ipg_len_i <= ipg_len;
         end
//  output last word modulo during eop
      if (eop_int == 1'b 1)
         begin
         tmod_reg <= #(thold) bytecnt_eop;
         end
      else if (eop_ex == 1'b 0 )
         begin
         tmod_reg <= #(thold) {2{1'b 0}};
         end
      done_reg <= done_gen;
      end
   end
//  ------------------------
//  capture GMII data bytes
//  ------------------------
always @(posedge tx_clk or posedge reset)
   begin : process_6
   if (reset == 1'b 1)
      begin
      data32 <= {32{1'b 0}};
      bytecnt_eop <= 0;
      bytecnt <= 0;
      end
   else
      begin
      if (eop_gen == 1'b 1)
         begin
         bytecnt_eop <= (bytecnt + 2'b 10) % 4; //  remember where the last byte was
         end
      if (sop_gen == 1'b 1 & rx_dv == 1'b 1)
         begin
//  first byte
         data32 <= {rxd[7:0], 24'h 000000};
         bytecnt <= 0;
         end
      else if (rx_dv == 1'b 1 )
         begin
//  during frame
         data32[31:0] <= {rxd[7:0], data32[31:8]};
         bytecnt <= (bytecnt + 1'b 1) % 4;
         end
      else if (rx_dv == 1'b 0 & bytecnt < 3 &
    eop_int == 1'b 1 )
         begin
//  shift last bytes to LSBs as necessary
         data32[31:0] <= {8'h 00, data32[31:8]};
         bytecnt <= (bytecnt + 1'b 1) % 4;
         end
      else if (rx_dv == 1'b 0 & eop_int == 1'b 0 )
         begin
//  stopped and after eop => reset
         bytecnt <= 0;
         end
      end
   end
 
//  ------------------------
//  state machine
//  ------------------------
always @(posedge clk or posedge reset)
   begin : process_7
   if (reset == 1'b 1)
      begin
      state <= stm_typ_s_idle;
      count <= 8;
      end
   else
      begin
      if (state == stm_typ_s_ipg)
         begin
         count <= count + 3'b 100;
         end
      else
         begin
         count <= 8;
         end
      case (state)
      stm_typ_s_idle:
         begin
         if (done_gen == 1'b 0) //  has the generator been triggered ?
            begin
            state <= stm_typ_s_data;
            end
         else
            begin
            state <= stm_typ_s_idle;
            end
         end
      stm_typ_s_data:
         begin
         if (eop_int == 1'b 0 & enable_int == 1'b 1)
            begin
            state <= stm_typ_s_data;
            end
         else if (eop_int == 1'b 0 & enable_int == 1'b 0 )
            begin
            state <= stm_typ_s_wait;
            end
         else if (eop_int == 1'b 1 )
            begin
            if (ipg_len_i < 4 & start == 1'b 1)
               begin
               state <= stm_typ_s_ipg0; //  no IPG
               end
            else if (ipg_len_i < 8 )
               begin
               state <= stm_typ_s_idle;
               end
            else
               begin
               state <= stm_typ_s_ipg;
               end
            end
         else
            begin
            state <= stm_typ_s_data;
            end
         end
      stm_typ_s_ipg:
         begin
         if (count < ipg_len_i)
            begin
            state <= stm_typ_s_ipg;
            end
         else
            begin
            state <= stm_typ_s_idle;
            end
         end
      stm_typ_s_ipg0:
         begin
         state <= stm_typ_s_data;
         end
      stm_typ_s_wait:
         begin
         if (enable_int == 1'b 1)
            begin
            state <= stm_typ_s_data;
            end
         else
            begin
            state <= stm_typ_s_wait;
            end
         end
      default:
         begin
         state <= stm_typ_s_idle;
         end
      endcase
      end
   end
 
 
// endian adapter from Little endian to Big endian
 
// output   [31:0] dout; 
// output   dval; 
// output   derror; 
// output   sop; //  pulse with first word
// output   eop; //  pulse with last word (tmod valid)
// output   [1:0] tmod; //  last word modulo
 
always @(posedge clk or posedge reset)
 begin
   if (reset == 1'b 1)
      begin
          dout_temp  <= {32{1'b 0}};
          dval_temp  <= {{1'b 0}};
          derror_temp<= {{1'b 0}};
          sop_temp   <= {{1'b 0}};
          eop_temp   <= {{1'b 0}};
          tmod_temp  <= {2{1'b 0}};
          done_temp  <= 1'b 0;
      end
   else
    begin
        if (BIG_ENDIAN ==1'b1)
         begin
             dout_temp  <= #(thold) {dout_reg[7:0],dout_reg[15:8],dout_reg[23:16],dout_reg[31:24]};
             dval_temp  <= #(thold) dval_reg;
             derror_temp<= #(thold) derror_reg;
             sop_temp   <= #(thold) sop_ex;
             eop_temp   <= #(thold) eop_ex;
             done_temp  <= #(thold) done_reg;
 
             case (tmod_reg)
               2'b00:  tmod_temp <= 2'b00;
               2'b01:  tmod_temp <= 2'b11;
               2'b10:  tmod_temp <= 2'b10;
               2'b11:  tmod_temp <= 2'b01;
               default:tmod_temp <= {{1'b 0}};
             endcase
 
         end
        else
         begin
             dout_temp     <= #(thold) dout_reg;
             dval_temp     <= #(thold) dval_reg;
             derror_temp   <= #(thold) derror_reg;
             sop_temp      <= #(thold) sop_ex;
             eop_temp      <= #(thold) eop_ex;
             tmod_temp     <= #(thold) tmod_reg;
             done_temp     <= #(thold) done_reg;
         end
    end
 end
 
generate if (ZERO_LATENCY == 1)
    begin
    timing_adapter_32 tb_adapter (
 
          // Interface: clk
          .clk(clk),                                //input
          .reset(reset),                         //input
          // Interface: in 
          .in_ready(enable_int),                    //output
          .in_valid(dval_temp),                     //input
          .in_data(dout_temp),                      //input
          .in_startofpacket(sop_temp),              //input
          .in_endofpacket(eop_temp),                //input
          .in_empty(tmod_temp),                     //input
          .in_error({derror_temp}),                 //input
          // Interface: out
          .out_ready(enable),                       //input
          .out_valid(dval),                         //output
          .out_data(dout),                          //output
          .out_startofpacket(sop),                  //output
          .out_endofpacket(eop),                    //output
          .out_empty(tmod),                         //output
          .out_error({derror})                      //output
    );
 
    assign done = done_temp;
    end
else
    begin
     always @(posedge clk or posedge reset)
       begin
         if (reset == 1'b 1)
           enable_reg <= 1'b 0;
         else
           enable_reg <= enable;
        end
         assign enable_int = enable_reg;
     assign dout     = dout_temp;
     assign dval     = dval_temp;
     assign derror   = derror_temp;
     assign sop      = sop_temp;
     assign eop      = eop_temp;
     assign tmod     = tmod_temp;
     assign done     = done_temp;
    end
endgenerate
 
//  Generator
//  ---------
ethgenerator32  gen1g (
          .reset(reset),
          .rx_clk(tx_clk),
          .rxd(rxd),
          .rx_dv(rx_dv),
          .rx_er(rx_er),
          .sop(sop_gen),
          .eop(eop_gen),
          .mac_reverse(mac_reverse),
          .dst(dst),
          .src(src),
          .prmble_len(prmble_len),
          .pquant(pquant),
          .vlan_ctl(vlan_ctl),
          .len(len),
          .frmtype(frmtype),
          .cntstart(cntstart),
          .cntstep(cntstep),
          .ipg_len(16'h 4),
          .payload_err(payload_err),
          .prmbl_err(prmbl_err),
          .crc_err(crc_err),
          .vlan_en(vlan_en),
          .stack_vlan(stack_vlan),
          .pause_gen(pause_gen),
          .pad_en(pad_en),
          .phy_err(phy_err),
          .end_err(end_err),
          .data_only(data_only),
          .start(start_gen),
          .done(done_gen));
 
defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;
defparam gen1g.thold         = 0.1;
 
endmodule // module ethgenerator32
 

Browse

Tools

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [top_ethgen32.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: top_ethgen32.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen32.v,v $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// Ethernet Traffic Generator for 32 bit MAC Atlantic client interface`
19			`// Instantiates VERILOG module: ethgenerator32 (ethgen32.v)`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps // timescale for following modules
29
30			`module top_ethgenerator32 (`
31
32			`reset,`
33			`clk,`
34			`enable,`
35			`dout,`
36			`dval,`
37			`derror,`
38			`sop,`
39			`eop,`
40			`tmod,`
41			`mac_reverse,`
42			`dst,`
43			`src,`
44			`prmble_len,`
45			`pquant,`
46			`vlan_ctl,`
47			`len,`
48			`frmtype,`
49			`cntstart,`
50			`cntstep,`
51			`ipg_len,`
52			`payload_err,`
53			`prmbl_err,`
54			`crc_err,`
55			`vlan_en,`
56			`stack_vlan,`
57			`pause_gen,`
58			`pad_en,`
59			`phy_err,`
60			`end_err,`
61			`data_only,`
62			`start,`
63			`done);`
64			`parameter thold = 1.0 ;`
65			`parameter ENABLE_SHIFT16 = 1'b 0;`
66			`parameter BIG_ENDIAN = 1'b1;`
67			`parameter ZERO_LATENCY = 0;`
68
69			`input reset; // active high`
70			`input clk;`
71			`input enable;`
72			`output [31:0] dout;`
73			`output dval;`
74			`output derror;`
75			`output sop; // pulse with first word`
76			`output eop; // pulse with last word (tmod valid)`
77			`output [1:0] tmod; // last word modulo`
78			`input mac_reverse; // 1: dst/src are sent MSB first (non-standard)`
79			`input [47:0] dst; // destination address`
80			`input [47:0] src; // source address`
81			`input [3:0] prmble_len; // length of preamble`
82			`input [15:0] pquant; // Pause Quanta value`
83			`input [15:0] vlan_ctl; // VLAN control info`
84			`input [15:0] len; // Length of payload`
85			`input [15:0] frmtype; // if non-null: type field instead length`
86			`input [7:0] cntstart; // payload data counter start (first byte of payload)`
87			`input [7:0] cntstep; // payload counter step (2nd byte in paylaod)`
88			`input [15:0] ipg_len;`
89			`input payload_err; // generate payload pattern error (last payload byte is wrong)`
90			`input prmbl_err; // Send corrupt SFD in otherwise correct preamble`
91			`input crc_err;`
92			`input vlan_en;`
93			`input stack_vlan;`
94			`input pause_gen;`
95			`input pad_en;`
96			`input phy_err; // Generate the well known ERROR control character`
97			`input end_err; // Send corrupt TERMINATE character (wrong code)`
98			`input data_only; // if set omits preamble, padding, CRC`
99			`input start;`
100			`output done;`
101			`wire [31:0] dout;`
102			`reg [31:0] dout_reg;`
103			`wire dval;`
104			`reg dval_reg;`
105			`wire derror;`
106			`reg derror_reg;`
107			`wire sop;`
108			`wire eop;`
109			`// Frame Contents definitions`
110			`wire [1:0] tmod;`
111			`reg [1:0] tmod_reg;`
112			`wire done;`
113			`reg done_reg;`
114			`// internal GMII from generator`
115			`wire [7:0] rxd;`
116			`wire rx_dv;`
117			`wire rx_er;`
118			`wire sop_gen;`
119			`wire eop_gen;`
120			`reg start_gen;`
121			`wire done_gen;`
122			`// captured signals from generator (lasting 1 word clock cycle)`
123			`wire enable_int;`
124			`reg enable_reg;`
125			`reg sop_int; // captured sop_gen`
126			`wire sop_int_d; // captured sop_gen`
127			`reg eop_int; // captured eop_gen`
128			`wire eop_i; // captured eop_gen`
129			`reg rx_er_int; // captured rx_er`
130			`// external signals`
131			`reg sop_ex;`
132			`reg eop_ex;`
133			`// captured command signals`
134			`reg [15:0] ipg_len_i;`
135			`// internal`
136			`reg [31:0] data32;`
137			`wire [2:0] clkcnt;`
138			`reg [1:0] bytecnt_eop; // captured count for last word`
139			`integer count;`
140
141			`//assign output`
142			`reg [31:0] dout_temp;`
143			`reg dval_temp;`
144			`reg derror_temp;`
145			`reg sop_temp;`
146			`reg eop_temp;`
147			`reg [1:0] tmod_temp;`
148			`reg done_temp;`
149
150
151			`// TYPE stm_typ:`
152			`parameter stm_typ_s_idle = 0;`
153			`parameter stm_typ_s_data = 1;`
154			`parameter stm_typ_s_ipg = 2;`
155			`parameter stm_typ_s_ipg0 = 3;`
156			`parameter stm_typ_s_wait = 4;`
157
158			`reg [2:0] state;`
159			`reg clk_d;`
160			`reg fast_clk;`
161			`reg fast_clk_gate;`
162			`reg [1:0] bytecnt;`
163			`reg tx_clk;`
164
165
166			`// ---------------------------------------`
167			`// Generate internal fast clock synchronized to external input clock`
168			`// ---------------------------------------`
169
170			`always`
171			`begin : process_1`
172			`fast_clk <= #(0.1) 1'b 0;`
173			`#( 0.4 );`
174			`fast_clk <= #(0.1) 1'b 1;`
175			`#( 0.4 );`
176			`end`
177
178			`always @(negedge fast_clk or posedge reset)`
179			`begin : process_2`
180			`if (reset == 1'b 1)`
181			`begin`
182			`fast_clk_gate <= 1'b 0;`
183			`clk_d <= 1'b 0;`
184			`end`
185			`else`
186			`begin`
187			`// work on neg edge`
188			`clk_d <= clk;`
189			`if ((rx_dv == 1'b 0 \| done_gen == 1'b 1) &`
190			`(enable_int == 1'b 1 \| start_gen == 1'b 1))`
191			`begin`
192			`// generator not running, enable it permanently`
193			`fast_clk_gate <= 1'b 1;`
194			`end`
195			`else if (clk_d == 1'b 0 & clk == 1'b 1 &`
196			`state != stm_typ_s_wait & (enable_int == 1'b 1 \|`
197			`state == stm_typ_s_ipg0) )`
198			`begin`
199			`// wait for rising edge`
200			`fast_clk_gate <= 1'b 1;`
201			`end`
202			`else if (bytecnt < 3 )`
203			`begin`
204			`// after 4 octets have been processed, wait for next clk rising edge`
205			`fast_clk_gate <= 1'b 1;`
206			`end`
207			`else`
208			`begin`
209			`fast_clk_gate <= 1'b 0;`
210			`end`
211			`end`
212			`end`
213			`// DDR process to generate gated clock`
214			`always @(fast_clk or reset)`
215			`begin : process_3`
216			`if (reset == 1'b 1)`
217			`begin`
218			`tx_clk <= 1'b 0;`
219			`end`
220			`else if ( fast_clk == 1'b 1 )`
221			`begin`
222			`if (fast_clk_gate == 1'b 1)`
223			`begin`
224			`tx_clk <= 1'b 1;`
225			`end`
226			`end`
227			`else if ( fast_clk == 1'b 0 )`
228			`begin`
229			`tx_clk <= 1'b 0;`
230			`end`
231			`end`
232			`// tx_clk <= fast_clk and fast_clk_gate;`
233			`// capture generator signals with word clock domain handshake`
234			`// ----------------------------------------------------------`
235			`always @(posedge tx_clk or posedge reset)`
236			`begin : process_4`
237			`if (reset == 1'b 1)`
238			`begin`
239			`eop_int <= 1'b 0;`
240			`sop_int <= 1'b 0;`
241			`rx_er_int <= 1'b 0;`
242			`end`
243			`else`
244			`begin`
245			`if (sop_gen == 1'b 1)`
246			`begin`
247			`sop_int <= 1'b 1;`
248			`end`
249			`else if (sop_ex == 1'b 1 )`
250			`begin`
251			`sop_int <= 1'b 0;`
252			`end`
253			`if (eop_gen == 1'b 1)`
254			`begin`
255			`eop_int <= 1'b 1;`
256			`end`
257			`else if (eop_ex == 1'b 1 )`
258			`begin`
259			`eop_int <= 1'b 0;`
260			`end`
261			`if (rx_er == 1'b 1)`
262			`begin`
263			`rx_er_int <= 1'b 1;`
264			`end`
265			`else if (eop_ex == 1'b 1 )`
266			`begin`
267			`rx_er_int <= 1'b 0;`
268			`end`
269			`end`
270			`end`
271			`// word clock, external signal generation`
272			`// --------------------------------------`
273			`//assign #(thold) sop = sop_ex;`
274			`//assign #(thold) eop = eop_ex;`
275			`always @(posedge clk or posedge reset)`
276			`begin : process_5`
277			`if (reset == 1'b 1)`
278			`begin`
279			`// enable_int <= 1'b 0;`
280			`eop_ex <= 1'b 0;`
281			`sop_ex <= 1'b 0;`
282			`dval_reg <= 1'b 0;`
283			`dout_reg <= {32{1'b 0}};`
284			`tmod_reg <= {2{1'b 0}};`
285			`derror_reg <= 1'b 0;`
286			`start_gen <= 1'b 0;`
287			`ipg_len_i <= 0;`
288			`done_reg <= 1'b 0;`
289			`end`
290			`else`
291			`begin`
292			`eop_ex <= eop_int;`
293			`sop_ex <= sop_int;`
294			`dout_reg <= #(thold) data32;`
295			`derror_reg <= #(thold) rx_er_int;`
296			`// enable_int <= enable;`
297			`if (done_gen == 1'b 1 & enable_int == 1'b 1 &`
298			`(state == stm_typ_s_idle \| state == stm_typ_s_ipg0 \|`
299			`state == stm_typ_s_data & eop_int == 1'b 1 &`
300			`ipg_len_i < 4 & start == 1'b 1))`
301			`begin`
302			`// nextstate=S_IPG0`
303			`start_gen <= start;`
304			`end`
305			`else`
306			`begin`
307			`start_gen <= 1'b 0;`
308			`end`
309			`if ((state == stm_typ_s_data \| state == stm_typ_s_ipg0) &`
310			`enable_int == 1'b 1 \| start_gen == 1'b 1)`
311			`begin`
312			`dval_reg <= #(thold) 1'b 1;`
313			`end`
314			`else`
315			`begin`
316			`dval_reg <= #(thold) 1'b 0;`
317			`end`
318			`// store input variables that could change until end of frame`
319			`if (sop_int == 1'b 1)`
320			`begin`
321			`ipg_len_i <= ipg_len;`
322			`end`
323			`// output last word modulo during eop`
324			`if (eop_int == 1'b 1)`
325			`begin`
326			`tmod_reg <= #(thold) bytecnt_eop;`
327			`end`
328			`else if (eop_ex == 1'b 0 )`
329			`begin`
330			`tmod_reg <= #(thold) {2{1'b 0}};`
331			`end`
332			`done_reg <= done_gen;`
333			`end`
334			`end`
335			`// ------------------------`
336			`// capture GMII data bytes`
337			`// ------------------------`
338			`always @(posedge tx_clk or posedge reset)`
339			`begin : process_6`
340			`if (reset == 1'b 1)`
341			`begin`
342			`data32 <= {32{1'b 0}};`
343			`bytecnt_eop <= 0;`
344			`bytecnt <= 0;`
345			`end`
346			`else`
347			`begin`
348			`if (eop_gen == 1'b 1)`
349			`begin`
350			`bytecnt_eop <= (bytecnt + 2'b 10) % 4; // remember where the last byte was`
351			`end`
352			`if (sop_gen == 1'b 1 & rx_dv == 1'b 1)`
353			`begin`
354			`// first byte`
355			`data32 <= {rxd[7:0], 24'h 000000};`
356			`bytecnt <= 0;`
357			`end`
358			`else if (rx_dv == 1'b 1 )`
359			`begin`
360			`// during frame`
361			`data32[31:0] <= {rxd[7:0], data32[31:8]};`
362			`bytecnt <= (bytecnt + 1'b 1) % 4;`
363			`end`
364			`else if (rx_dv == 1'b 0 & bytecnt < 3 &`
365			`eop_int == 1'b 1 )`
366			`begin`
367			`// shift last bytes to LSBs as necessary`
368			`data32[31:0] <= {8'h 00, data32[31:8]};`
369			`bytecnt <= (bytecnt + 1'b 1) % 4;`
370			`end`
371			`else if (rx_dv == 1'b 0 & eop_int == 1'b 0 )`
372			`begin`
373			`// stopped and after eop => reset`
374			`bytecnt <= 0;`
375			`end`
376			`end`
377			`end`
378
379			`// ------------------------`
380			`// state machine`
381			`// ------------------------`
382			`always @(posedge clk or posedge reset)`
383			`begin : process_7`
384			`if (reset == 1'b 1)`
385			`begin`
386			`state <= stm_typ_s_idle;`
387			`count <= 8;`
388			`end`
389			`else`
390			`begin`
391			`if (state == stm_typ_s_ipg)`
392			`begin`
393			`count <= count + 3'b 100;`
394			`end`
395			`else`
396			`begin`
397			`count <= 8;`
398			`end`
399			`case (state)`
400			`stm_typ_s_idle:`
401			`begin`
402			`if (done_gen == 1'b 0) // has the generator been triggered ?`
403			`begin`
404			`state <= stm_typ_s_data;`
405			`end`
406			`else`
407			`begin`
408			`state <= stm_typ_s_idle;`
409			`end`
410			`end`
411			`stm_typ_s_data:`
412			`begin`
413			`if (eop_int == 1'b 0 & enable_int == 1'b 1)`
414			`begin`
415			`state <= stm_typ_s_data;`
416			`end`
417			`else if (eop_int == 1'b 0 & enable_int == 1'b 0 )`
418			`begin`
419			`state <= stm_typ_s_wait;`
420			`end`
421			`else if (eop_int == 1'b 1 )`
422			`begin`
423			`if (ipg_len_i < 4 & start == 1'b 1)`
424			`begin`
425			`state <= stm_typ_s_ipg0; // no IPG`
426			`end`
427			`else if (ipg_len_i < 8 )`
428			`begin`
429			`state <= stm_typ_s_idle;`
430			`end`
431			`else`
432			`begin`
433			`state <= stm_typ_s_ipg;`
434			`end`
435			`end`
436			`else`
437			`begin`
438			`state <= stm_typ_s_data;`
439			`end`
440			`end`
441			`stm_typ_s_ipg:`
442			`begin`
443			`if (count < ipg_len_i)`
444			`begin`
445			`state <= stm_typ_s_ipg;`
446			`end`
447			`else`
448			`begin`
449			`state <= stm_typ_s_idle;`
450			`end`
451			`end`
452			`stm_typ_s_ipg0:`
453			`begin`
454			`state <= stm_typ_s_data;`
455			`end`
456			`stm_typ_s_wait:`
457			`begin`
458			`if (enable_int == 1'b 1)`
459			`begin`
460			`state <= stm_typ_s_data;`
461			`end`
462			`else`
463			`begin`
464			`state <= stm_typ_s_wait;`
465			`end`
466			`end`
467			`default:`
468			`begin`
469			`state <= stm_typ_s_idle;`
470			`end`
471			`endcase`
472			`end`
473			`end`
474
475
476			`// endian adapter from Little endian to Big endian`
477
478			`// output [31:0] dout;`
479			`// output dval;`
480			`// output derror;`
481			`// output sop; // pulse with first word`
482			`// output eop; // pulse with last word (tmod valid)`
483			`// output [1:0] tmod; // last word modulo`
484
485			`always @(posedge clk or posedge reset)`
486			`begin`
487			`if (reset == 1'b 1)`
488			`begin`
489			`dout_temp <= {32{1'b 0}};`
490			`dval_temp <= {{1'b 0}};`
491			`derror_temp<= {{1'b 0}};`
492			`sop_temp <= {{1'b 0}};`
493			`eop_temp <= {{1'b 0}};`
494			`tmod_temp <= {2{1'b 0}};`
495			`done_temp <= 1'b 0;`
496			`end`
497			`else`
498			`begin`
499			`if (BIG_ENDIAN ==1'b1)`
500			`begin`
501			`dout_temp <= #(thold) {dout_reg[7:0],dout_reg[15:8],dout_reg[23:16],dout_reg[31:24]};`
502			`dval_temp <= #(thold) dval_reg;`
503			`derror_temp<= #(thold) derror_reg;`
504			`sop_temp <= #(thold) sop_ex;`
505			`eop_temp <= #(thold) eop_ex;`
506			`done_temp <= #(thold) done_reg;`
507
508			`case (tmod_reg)`
509			`2'b00: tmod_temp <= 2'b00;`
510			`2'b01: tmod_temp <= 2'b11;`
511			`2'b10: tmod_temp <= 2'b10;`
512			`2'b11: tmod_temp <= 2'b01;`
513			`default:tmod_temp <= {{1'b 0}};`
514			`endcase`
515
516			`end`
517			`else`
518			`begin`
519			`dout_temp <= #(thold) dout_reg;`
520			`dval_temp <= #(thold) dval_reg;`
521			`derror_temp <= #(thold) derror_reg;`
522			`sop_temp <= #(thold) sop_ex;`
523			`eop_temp <= #(thold) eop_ex;`
524			`tmod_temp <= #(thold) tmod_reg;`
525			`done_temp <= #(thold) done_reg;`
526			`end`
527			`end`
528			`end`
529
530			`generate if (ZERO_LATENCY == 1)`
531			`begin`
532			`timing_adapter_32 tb_adapter (`
533
534			`// Interface: clk`
535			`.clk(clk), //input`
536			`.reset(reset), //input`
537			`// Interface: in`
538			`.in_ready(enable_int), //output`
539			`.in_valid(dval_temp), //input`
540			`.in_data(dout_temp), //input`
541			`.in_startofpacket(sop_temp), //input`
542			`.in_endofpacket(eop_temp), //input`
543			`.in_empty(tmod_temp), //input`
544			`.in_error({derror_temp}), //input`
545			`// Interface: out`
546			`.out_ready(enable), //input`
547			`.out_valid(dval), //output`
548			`.out_data(dout), //output`
549			`.out_startofpacket(sop), //output`
550			`.out_endofpacket(eop), //output`
551			`.out_empty(tmod), //output`
552			`.out_error({derror}) //output`
553			`);`
554
555			`assign done = done_temp;`
556			`end`
557			`else`
558			`begin`
559			`always @(posedge clk or posedge reset)`
560			`begin`
561			`if (reset == 1'b 1)`
562			`enable_reg <= 1'b 0;`
563			`else`
564			`enable_reg <= enable;`
565			`end`
566			`assign enable_int = enable_reg;`
567			`assign dout = dout_temp;`
568			`assign dval = dval_temp;`
569			`assign derror = derror_temp;`
570			`assign sop = sop_temp;`
571			`assign eop = eop_temp;`
572			`assign tmod = tmod_temp;`
573			`assign done = done_temp;`
574			`end`
575			`endgenerate`
576
577			`// Generator`
578			`// ---------`
579			`ethgenerator32 gen1g (`
580			`.reset(reset),`
581			`.rx_clk(tx_clk),`
582			`.rxd(rxd),`
583			`.rx_dv(rx_dv),`
584			`.rx_er(rx_er),`
585			`.sop(sop_gen),`
586			`.eop(eop_gen),`
587			`.mac_reverse(mac_reverse),`
588			`.dst(dst),`
589			`.src(src),`
590			`.prmble_len(prmble_len),`
591			`.pquant(pquant),`
592			`.vlan_ctl(vlan_ctl),`
593			`.len(len),`
594			`.frmtype(frmtype),`
595			`.cntstart(cntstart),`
596			`.cntstep(cntstep),`
597			`.ipg_len(16'h 4),`
598			`.payload_err(payload_err),`
599			`.prmbl_err(prmbl_err),`
600			`.crc_err(crc_err),`
601			`.vlan_en(vlan_en),`
602			`.stack_vlan(stack_vlan),`
603			`.pause_gen(pause_gen),`
604			`.pad_en(pad_en),`
605			`.phy_err(phy_err),`
606			`.end_err(end_err),`
607			`.data_only(data_only),`
608			`.start(start_gen),`
609			`.done(done_gen));`
610
611			`defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;`
612			`defparam gen1g.thold = 0.1;`
613
614			`endmodule // module ethgenerator32`
615