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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: top_ethgen32.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen8.v,v $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description : (Simulation only)
//
// Ethernet Traffic Generator for 8 bit fifoless MAC Atlantic client interface
// Instantiates VERILOG module: ethgenerator (ethgen.v)
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps  // timescale for following modules
 
module top_ethgenerator_8 (
 
   reset,
   clk,
   enable,
   dout,
   dval,
   derror,
   sop,
   eop,
   mac_reverse,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   cntstart,
   cntstep,
   ipg_len,
   payload_err,
   prmbl_err,
   crc_err,
   vlan_en,
   stack_vlan,
   pause_gen,
   pad_en,
   phy_err,
   end_err,
   data_only,
   start,
   done);
 
parameter thold = 1.0 ;
parameter ZERO_LATENCY = 0;
parameter ENABLE_SHIFT16 = 1'b 0;
 
 
input   reset; //  active high
input   clk;
input   enable;
output   [7:0] dout;
output   dval;
output   derror;
output   sop; //  pulse with first word
output   eop; //  pulse with last word (tmod valid)
input   mac_reverse; //  1: dst/src are sent MSB first (non-standard)
input   [47:0] dst; //  destination address
input   [47:0] src; //  source address
input   [3:0] prmble_len; //  length of preamble
input   [15:0] pquant; //  Pause Quanta value
input   [15:0] vlan_ctl; //  VLAN control info
input   [15:0] len; //  Length of payload
input   [15:0] frmtype; //  if non-null: type field instead length
input   [7:0] cntstart; //  payload data counter start (first byte of payload)
input   [7:0] cntstep; //  payload counter step (2nd byte in paylaod)
input   [15:0] ipg_len;
input   payload_err; //  generate payload pattern error (last payload byte is wrong)
input   prmbl_err; //  Send corrupt SFD in otherwise correct preamble
input   crc_err;
input   vlan_en;
input   stack_vlan;
input   pause_gen;
input   pad_en;
input   phy_err; //  Generate the well known ERROR control character
input   end_err; //  Send corrupt TERMINATE character (wrong code)
input   data_only; //  if set omits preamble, padding, CRC
input   start;
output   done;
wire     [7:0] dout;
reg     [7:0] dout_reg;
wire     dval;
reg     dval_reg;
wire     derror;
reg     derror_reg;
wire    sop;
wire    eop;
//  Frame Contents definitions
wire     done;
reg     done_reg;
//  internal GMII from generator
wire    [7:0] rxd;
wire    rx_dv;
wire    rx_er;
wire    sop_gen;
wire    eop_gen;
reg     start_gen;
wire    done_gen;
//  captured signals from generator (lasting 1 word clock cycle)
wire     enable_int;
reg     enable_reg;
reg     sop_int; //  captured sop_gen
wire    sop_int_d; //  captured sop_gen
reg     eop_int; //  captured eop_gen
wire    eop_i; //  captured eop_gen
reg     rx_er_int; //  captured rx_er
//  external signals
reg     sop_ex;
reg     eop_ex;
//  captured command signals 
reg     [15:0] ipg_len_i;
//  internal
reg     [7:0] data8;
wire    [2:0] clkcnt;
reg     [1:0] bytecnt_eop; //  captured count for last word
integer count;
 
//assign output
reg     [7:0] dout_temp;
reg     dval_temp;
reg     derror_temp;
reg     sop_temp;
reg     eop_temp;
reg     done_temp;
 
reg     [7:0] dout_before_delay;
reg     dval_before_delay;
reg     derror_before_delay;
reg     sop_before_delay;
reg     eop_before_delay;
reg     done_before_delay;
 
 
// TYPE stm_typ:
parameter stm_typ_s_idle = 0;
parameter stm_typ_s_data = 1;
parameter stm_typ_s_ipg = 2;
parameter stm_typ_s_ipg0 = 3;
parameter stm_typ_s_wait = 4;
 
reg     [2:0] state;
reg     clk_d;
reg     fast_clk;
reg     fast_clk_gate;
reg     [1:0] bytecnt;
reg     tx_clk;
 
 
//  ---------------------------------------
//  Generate internal fast clock synchronized to external input clock
//  ---------------------------------------
 
always
   begin : process_1
   fast_clk <= #(0.1) 1'b 0;
   #( 0.4 );
   fast_clk <= #(0.1) 1'b 1;
   #( 0.4 );
   end
 
always @(negedge fast_clk or posedge reset)
   begin : process_2
   if (reset == 1'b 1)
      begin
      fast_clk_gate <= 1'b 0;
      clk_d <= 1'b 0;
      end
   else
      begin
//  work on neg edge
      clk_d <= clk;
      if ((rx_dv == 1'b 0 | done_gen == 1'b 1) &
    (enable_int == 1'b 1 | start_gen == 1'b 1))
         begin
//  generator not running, enable it permanently
         fast_clk_gate <= 1'b 1;
         end
      else if (clk_d == 1'b 0 & clk == 1'b 1 &
    state != stm_typ_s_wait & (enable_int == 1'b 1 |
    state == stm_typ_s_ipg0) )
         begin
//  wait for rising edge
         fast_clk_gate <= 1'b 1;
         end
      else
         begin
         fast_clk_gate <= 1'b 0;
         end
      end
   end
//  DDR process to generate gated clock
always @(fast_clk or reset)
   begin : process_3
   if (reset == 1'b 1)
      begin
      tx_clk <= 1'b 0;
      end
   else if ( fast_clk == 1'b 1 )
      begin
      if (fast_clk_gate == 1'b 1)
         begin
         tx_clk <= 1'b 1;
         end
      end
   else if ( fast_clk == 1'b 0 )
      begin
      tx_clk <= 1'b 0;
      end
   end
 
 
 
// tx_clk <= fast_clk and fast_clk_gate;        
//  capture generator signals with word clock domain handshake
//  ----------------------------------------------------------
always @(posedge tx_clk or posedge reset)
   begin : process_4
   if (reset == 1'b 1)
      begin
      eop_int <= 1'b 0;
      sop_int <= 1'b 0;
      rx_er_int <= 1'b 0;
      end
   else
      begin
      if (sop_gen == 1'b 1)
         begin
         sop_int <= 1'b 1;
         end
      else if (sop_ex == 1'b 1 )
         begin
         sop_int <= 1'b 0;
         end
      if (eop_gen == 1'b 1)
         begin
         eop_int <= 1'b 1;
         end
      else if (eop_ex == 1'b 1 )
         begin
         eop_int <= 1'b 0;
         end
      if (rx_er == 1'b 1)
         begin
         rx_er_int <= 1'b 1;
         end
      else if (eop_ex == 1'b 1 )
         begin
         rx_er_int <= 1'b 0;
         end
      end
   end
//  word clock, external signal generation
//  --------------------------------------
//assign #(thold) sop = sop_ex; 
//assign #(thold) eop = eop_ex; 
always @(posedge clk or posedge reset)
   begin : process_5
   if (reset == 1'b 1)
      begin
//      enable_int <= 1'b 0;  
      eop_ex <= 1'b 0;
      sop_ex <= 1'b 0;
      dval_reg <= 1'b 0;
      dout_reg <= {8{1'b 0}};
      derror_reg <= 1'b 0;
      start_gen <= 1'b 0;
      ipg_len_i <= 0;
      done_reg <= 1'b 0;
      end
   else
      begin
      eop_ex <= eop_int;
      sop_ex <= sop_int;
      dout_reg <= #(thold) data8;
      derror_reg <= #(thold) rx_er_int;
//      enable_int <= enable; 
      if (done_gen == 1'b 1 & enable_int == 1'b 1 &
    (state == stm_typ_s_idle | state == stm_typ_s_ipg0 |
    state == stm_typ_s_data & eop_int == 1'b 1 &
    ipg_len_i < 4 & start == 1'b 1))
         begin
//  nextstate=S_IPG0
         start_gen <= start;
         end
      else
         begin
         start_gen <= 1'b 0;
         end
      if ((state == stm_typ_s_data | state == stm_typ_s_ipg0) &
    enable_int == 1'b 1 )//| start_gen == 1'b 1)
         begin
         dval_reg <= #(thold) 1'b 1;
         end
      else
         begin
         dval_reg <= #(thold) 1'b 0;
         end
//  store input variables that could change until end of frame
      if (sop_int == 1'b 1)
         begin
         ipg_len_i <= ipg_len;
         end
//  output last word modulo during eop
//      if (eop_int == 1'b 1)
//         begin
//         tmod_reg <= #(thold) bytecnt_eop;  
//         end
//      else if (eop_ex == 1'b 0 )
//         begin
//         tmod_reg <= #(thold) {2{1'b 0}};   
//         end
      done_reg <= done_gen;
      end
   end
//  ------------------------
//  capture GMII data bytes
//  ------------------------
always @(posedge tx_clk or posedge reset)
   begin : process_6
   if (reset == 1'b 1)
      begin
      data8 <= {8{1'b 0}};
      end
   else
      begin
      if (sop_gen == 1'b 1 & rx_dv == 1'b 1)
         begin
//  first byte
         data8 <= {rxd[7:0]};
         end
      else if (rx_dv == 1'b 1 )
         begin
//  during frame
         data8 <= {rxd[7:0]};
         end
      end
    end
 
//  ------------------------
//  state machine
//  ------------------------
always @(posedge clk or posedge reset)
   begin : process_7
   if (reset == 1'b 1)
      begin
      state <= stm_typ_s_idle;
      count <= 8;
      end
   else
      begin
      if (state == stm_typ_s_ipg)
         begin
         count <= count + 3'b 100;
         end
      else
         begin
         count <= 8;
         end
      case (state)
      stm_typ_s_idle:
         begin
         if (done_gen == 1'b 0) //  has the generator been triggered ?
            begin
            state <= stm_typ_s_data;
            end
         else
            begin
            state <= stm_typ_s_idle;
            end
         end
      stm_typ_s_data:
         begin
         if (eop_int == 1'b 0 & enable_int == 1'b 1)
            begin
            state <= stm_typ_s_data;
            end
         else if (eop_int == 1'b 0 & enable_int == 1'b 0 )
            begin
            state <= stm_typ_s_wait;
            end
         else if (eop_int == 1'b 1 )
            begin
            if (ipg_len_i < 4 & start == 1'b 1)
               begin
               state <= stm_typ_s_ipg0; //  no IPG
               end
            else if (ipg_len_i < 8 )
               begin
               state <= stm_typ_s_idle;
               end
            else
               begin
               state <= stm_typ_s_ipg;
               end
            end
         else
            begin
            state <= stm_typ_s_data;
            end
         end
      stm_typ_s_ipg:
         begin
         if (count < ipg_len_i)
            begin
            state <= stm_typ_s_ipg;
            end
         else
            begin
            state <= stm_typ_s_idle;
            end
         end
      stm_typ_s_ipg0:
         begin
         state <= stm_typ_s_data;
         end
      stm_typ_s_wait:
         begin
         if (enable_int == 1'b 1)
            begin
            state <= stm_typ_s_data;
            end
         else
            begin
            state <= stm_typ_s_wait;
            end
         end
      default:
         begin
         state <= stm_typ_s_idle;
         end
      endcase
      end
   end
 
 
 
always @(posedge clk or posedge reset)
 begin
   if (reset == 1'b 1)
      begin
          dout_temp  <= {8{1'b 0}};
          dval_temp  <= {{1'b 0}};
          derror_temp<= {{1'b 0}};
          sop_temp   <= {{1'b 0}};
          eop_temp   <= {{1'b 0}};
          done_temp  <= 1'b 0;
 
 
      end
   else
    begin
             dout_temp     <= #(thold) dout_reg;
             dval_temp     <= #(thold) dval_reg;
             derror_temp   <= #(thold) derror_reg;
             sop_temp      <= #(thold) sop_ex;
             eop_temp      <= #(thold) eop_ex;
             done_temp     <= #(thold) done_reg;
    end
 end
 
generate if (ZERO_LATENCY == 1)
    begin
    timing_adapter_8 tb_adapter (
 
          // Interface: clk
          .clk(clk),                             //input
          .reset(reset),                            //input
          // Interface: in 
          .in_ready(enable_int),                    //output
          .in_valid(dval_temp),                     //input
          .in_data(dout_temp),                      //input
          .in_startofpacket(sop_temp),              //input
          .in_endofpacket(eop_temp),                //input
          .in_error({derror_temp}),                 //input
          // Interface: out
          .out_ready(enable),                       //input
          .out_valid(dval),                        //output
          .out_data(dout),                           //output
          .out_startofpacket(sop),                  //output
          .out_endofpacket(eop),                    //output
          .out_error({derror})                       //output
 
    );
 
    assign done = done_temp;
    end
else
    begin
     always @(posedge clk or posedge reset)
       begin
         if (reset == 1'b 1)
           enable_reg <= 1'b 0;
         else
           enable_reg <= enable;
        end
         assign enable_int = enable_reg;
     assign dout     =  dout_temp;
     assign dval     =  dval_temp;
     assign derror   =  derror_temp;
     assign sop      =  sop_temp;
     assign eop      =  eop_temp;
     assign done     =  done_temp;
    end
endgenerate
 
 
//  Generator
//  ---------
ethgenerator  gen1g (
          .reset(reset),
          .rx_clk(tx_clk),
          .enable(1'b1),
          .rxd(rxd),
          .rx_dv(rx_dv),
          .rx_er(rx_er),
          .sop(sop_gen),
          .eop(eop_gen),
          .mac_reverse(mac_reverse),
          .dst(dst),
          .src(src),
          .prmble_len(prmble_len),
          .pquant(pquant),
          .vlan_ctl(vlan_ctl),
          .len(len),
          .frmtype(frmtype),
          .cntstart(cntstart),
          .cntstep(cntstep),
          .ipg_len(16'h 4),
          .payload_err(payload_err),
          .prmbl_err(prmbl_err),
          .crc_err(crc_err),
          .vlan_en(vlan_en),
          .stack_vlan(stack_vlan),
          .pause_gen(pause_gen),
          .pad_en(pad_en),
          .phy_err(phy_err),
          .end_err(end_err),
          .data_only(data_only),
                  .runt_gen(1'b0) ,
          .long_pause(1'b0),
          .carrier_sense(1'b0),
          .false_carrier(1'b0),
          .carrier_extend(1'b0),
          .carrier_extend_error(1'b0),
          .start(start_gen),
          .done(done_gen));
 
defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;
defparam gen1g.thold         = 0.1;
 
 
endmodule // module top_ethgenerator_8
 

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [top_ethgen8.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: top_ethgen32.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen8.v,v $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// Ethernet Traffic Generator for 8 bit fifoless MAC Atlantic client interface`
19			`// Instantiates VERILOG module: ethgenerator (ethgen.v)`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps // timescale for following modules
29
30			`module top_ethgenerator_8 (`
31
32			`reset,`
33			`clk,`
34			`enable,`
35			`dout,`
36			`dval,`
37			`derror,`
38			`sop,`
39			`eop,`
40			`mac_reverse,`
41			`dst,`
42			`src,`
43			`prmble_len,`
44			`pquant,`
45			`vlan_ctl,`
46			`len,`
47			`frmtype,`
48			`cntstart,`
49			`cntstep,`
50			`ipg_len,`
51			`payload_err,`
52			`prmbl_err,`
53			`crc_err,`
54			`vlan_en,`
55			`stack_vlan,`
56			`pause_gen,`
57			`pad_en,`
58			`phy_err,`
59			`end_err,`
60			`data_only,`
61			`start,`
62			`done);`
63
64			`parameter thold = 1.0 ;`
65			`parameter ZERO_LATENCY = 0;`
66			`parameter ENABLE_SHIFT16 = 1'b 0;`
67
68
69			`input reset; // active high`
70			`input clk;`
71			`input enable;`
72			`output [7:0] dout;`
73			`output dval;`
74			`output derror;`
75			`output sop; // pulse with first word`
76			`output eop; // pulse with last word (tmod valid)`
77			`input mac_reverse; // 1: dst/src are sent MSB first (non-standard)`
78			`input [47:0] dst; // destination address`
79			`input [47:0] src; // source address`
80			`input [3:0] prmble_len; // length of preamble`
81			`input [15:0] pquant; // Pause Quanta value`
82			`input [15:0] vlan_ctl; // VLAN control info`
83			`input [15:0] len; // Length of payload`
84			`input [15:0] frmtype; // if non-null: type field instead length`
85			`input [7:0] cntstart; // payload data counter start (first byte of payload)`
86			`input [7:0] cntstep; // payload counter step (2nd byte in paylaod)`
87			`input [15:0] ipg_len;`
88			`input payload_err; // generate payload pattern error (last payload byte is wrong)`
89			`input prmbl_err; // Send corrupt SFD in otherwise correct preamble`
90			`input crc_err;`
91			`input vlan_en;`
92			`input stack_vlan;`
93			`input pause_gen;`
94			`input pad_en;`
95			`input phy_err; // Generate the well known ERROR control character`
96			`input end_err; // Send corrupt TERMINATE character (wrong code)`
97			`input data_only; // if set omits preamble, padding, CRC`
98			`input start;`
99			`output done;`
100			`wire [7:0] dout;`
101			`reg [7:0] dout_reg;`
102			`wire dval;`
103			`reg dval_reg;`
104			`wire derror;`
105			`reg derror_reg;`
106			`wire sop;`
107			`wire eop;`
108			`// Frame Contents definitions`
109			`wire done;`
110			`reg done_reg;`
111			`// internal GMII from generator`
112			`wire [7:0] rxd;`
113			`wire rx_dv;`
114			`wire rx_er;`
115			`wire sop_gen;`
116			`wire eop_gen;`
117			`reg start_gen;`
118			`wire done_gen;`
119			`// captured signals from generator (lasting 1 word clock cycle)`
120			`wire enable_int;`
121			`reg enable_reg;`
122			`reg sop_int; // captured sop_gen`
123			`wire sop_int_d; // captured sop_gen`
124			`reg eop_int; // captured eop_gen`
125			`wire eop_i; // captured eop_gen`
126			`reg rx_er_int; // captured rx_er`
127			`// external signals`
128			`reg sop_ex;`
129			`reg eop_ex;`
130			`// captured command signals`
131			`reg [15:0] ipg_len_i;`
132			`// internal`
133			`reg [7:0] data8;`
134			`wire [2:0] clkcnt;`
135			`reg [1:0] bytecnt_eop; // captured count for last word`
136			`integer count;`
137
138			`//assign output`
139			`reg [7:0] dout_temp;`
140			`reg dval_temp;`
141			`reg derror_temp;`
142			`reg sop_temp;`
143			`reg eop_temp;`
144			`reg done_temp;`
145
146			`reg [7:0] dout_before_delay;`
147			`reg dval_before_delay;`
148			`reg derror_before_delay;`
149			`reg sop_before_delay;`
150			`reg eop_before_delay;`
151			`reg done_before_delay;`
152
153
154			`// TYPE stm_typ:`
155			`parameter stm_typ_s_idle = 0;`
156			`parameter stm_typ_s_data = 1;`
157			`parameter stm_typ_s_ipg = 2;`
158			`parameter stm_typ_s_ipg0 = 3;`
159			`parameter stm_typ_s_wait = 4;`
160
161			`reg [2:0] state;`
162			`reg clk_d;`
163			`reg fast_clk;`
164			`reg fast_clk_gate;`
165			`reg [1:0] bytecnt;`
166			`reg tx_clk;`
167
168
169			`// ---------------------------------------`
170			`// Generate internal fast clock synchronized to external input clock`
171			`// ---------------------------------------`
172
173			`always`
174			`begin : process_1`
175			`fast_clk <= #(0.1) 1'b 0;`
176			`#( 0.4 );`
177			`fast_clk <= #(0.1) 1'b 1;`
178			`#( 0.4 );`
179			`end`
180
181			`always @(negedge fast_clk or posedge reset)`
182			`begin : process_2`
183			`if (reset == 1'b 1)`
184			`begin`
185			`fast_clk_gate <= 1'b 0;`
186			`clk_d <= 1'b 0;`
187			`end`
188			`else`
189			`begin`
190			`// work on neg edge`
191			`clk_d <= clk;`
192			`if ((rx_dv == 1'b 0 \| done_gen == 1'b 1) &`
193			`(enable_int == 1'b 1 \| start_gen == 1'b 1))`
194			`begin`
195			`// generator not running, enable it permanently`
196			`fast_clk_gate <= 1'b 1;`
197			`end`
198			`else if (clk_d == 1'b 0 & clk == 1'b 1 &`
199			`state != stm_typ_s_wait & (enable_int == 1'b 1 \|`
200			`state == stm_typ_s_ipg0) )`
201			`begin`
202			`// wait for rising edge`
203			`fast_clk_gate <= 1'b 1;`
204			`end`
205			`else`
206			`begin`
207			`fast_clk_gate <= 1'b 0;`
208			`end`
209			`end`
210			`end`
211			`// DDR process to generate gated clock`
212			`always @(fast_clk or reset)`
213			`begin : process_3`
214			`if (reset == 1'b 1)`
215			`begin`
216			`tx_clk <= 1'b 0;`
217			`end`
218			`else if ( fast_clk == 1'b 1 )`
219			`begin`
220			`if (fast_clk_gate == 1'b 1)`
221			`begin`
222			`tx_clk <= 1'b 1;`
223			`end`
224			`end`
225			`else if ( fast_clk == 1'b 0 )`
226			`begin`
227			`tx_clk <= 1'b 0;`
228			`end`
229			`end`
230
231
232
233			`// tx_clk <= fast_clk and fast_clk_gate;`
234			`// capture generator signals with word clock domain handshake`
235			`// ----------------------------------------------------------`
236			`always @(posedge tx_clk or posedge reset)`
237			`begin : process_4`
238			`if (reset == 1'b 1)`
239			`begin`
240			`eop_int <= 1'b 0;`
241			`sop_int <= 1'b 0;`
242			`rx_er_int <= 1'b 0;`
243			`end`
244			`else`
245			`begin`
246			`if (sop_gen == 1'b 1)`
247			`begin`
248			`sop_int <= 1'b 1;`
249			`end`
250			`else if (sop_ex == 1'b 1 )`
251			`begin`
252			`sop_int <= 1'b 0;`
253			`end`
254			`if (eop_gen == 1'b 1)`
255			`begin`
256			`eop_int <= 1'b 1;`
257			`end`
258			`else if (eop_ex == 1'b 1 )`
259			`begin`
260			`eop_int <= 1'b 0;`
261			`end`
262			`if (rx_er == 1'b 1)`
263			`begin`
264			`rx_er_int <= 1'b 1;`
265			`end`
266			`else if (eop_ex == 1'b 1 )`
267			`begin`
268			`rx_er_int <= 1'b 0;`
269			`end`
270			`end`
271			`end`
272			`// word clock, external signal generation`
273			`// --------------------------------------`
274			`//assign #(thold) sop = sop_ex;`
275			`//assign #(thold) eop = eop_ex;`
276			`always @(posedge clk or posedge reset)`
277			`begin : process_5`
278			`if (reset == 1'b 1)`
279			`begin`
280			`// enable_int <= 1'b 0;`
281			`eop_ex <= 1'b 0;`
282			`sop_ex <= 1'b 0;`
283			`dval_reg <= 1'b 0;`
284			`dout_reg <= {8{1'b 0}};`
285			`derror_reg <= 1'b 0;`
286			`start_gen <= 1'b 0;`
287			`ipg_len_i <= 0;`
288			`done_reg <= 1'b 0;`
289			`end`
290			`else`
291			`begin`
292			`eop_ex <= eop_int;`
293			`sop_ex <= sop_int;`
294			`dout_reg <= #(thold) data8;`
295			`derror_reg <= #(thold) rx_er_int;`
296			`// enable_int <= enable;`
297			`if (done_gen == 1'b 1 & enable_int == 1'b 1 &`
298			`(state == stm_typ_s_idle \| state == stm_typ_s_ipg0 \|`
299			`state == stm_typ_s_data & eop_int == 1'b 1 &`
300			`ipg_len_i < 4 & start == 1'b 1))`
301			`begin`
302			`// nextstate=S_IPG0`
303			`start_gen <= start;`
304			`end`
305			`else`
306			`begin`
307			`start_gen <= 1'b 0;`
308			`end`
309			`if ((state == stm_typ_s_data \| state == stm_typ_s_ipg0) &`
310			`enable_int == 1'b 1 )//\| start_gen == 1'b 1)`
311			`begin`
312			`dval_reg <= #(thold) 1'b 1;`
313			`end`
314			`else`
315			`begin`
316			`dval_reg <= #(thold) 1'b 0;`
317			`end`
318			`// store input variables that could change until end of frame`
319			`if (sop_int == 1'b 1)`
320			`begin`
321			`ipg_len_i <= ipg_len;`
322			`end`
323			`// output last word modulo during eop`
324			`// if (eop_int == 1'b 1)`
325			`// begin`
326			`// tmod_reg <= #(thold) bytecnt_eop;`
327			`// end`
328			`// else if (eop_ex == 1'b 0 )`
329			`// begin`
330			`// tmod_reg <= #(thold) {2{1'b 0}};`
331			`// end`
332			`done_reg <= done_gen;`
333			`end`
334			`end`
335			`// ------------------------`
336			`// capture GMII data bytes`
337			`// ------------------------`
338			`always @(posedge tx_clk or posedge reset)`
339			`begin : process_6`
340			`if (reset == 1'b 1)`
341			`begin`
342			`data8 <= {8{1'b 0}};`
343			`end`
344			`else`
345			`begin`
346			`if (sop_gen == 1'b 1 & rx_dv == 1'b 1)`
347			`begin`
348			`// first byte`
349			`data8 <= {rxd[7:0]};`
350			`end`
351			`else if (rx_dv == 1'b 1 )`
352			`begin`
353			`// during frame`
354			`data8 <= {rxd[7:0]};`
355			`end`
356			`end`
357			`end`
358
359			`// ------------------------`
360			`// state machine`
361			`// ------------------------`
362			`always @(posedge clk or posedge reset)`
363			`begin : process_7`
364			`if (reset == 1'b 1)`
365			`begin`
366			`state <= stm_typ_s_idle;`
367			`count <= 8;`
368			`end`
369			`else`
370			`begin`
371			`if (state == stm_typ_s_ipg)`
372			`begin`
373			`count <= count + 3'b 100;`
374			`end`
375			`else`
376			`begin`
377			`count <= 8;`
378			`end`
379			`case (state)`
380			`stm_typ_s_idle:`
381			`begin`
382			`if (done_gen == 1'b 0) // has the generator been triggered ?`
383			`begin`
384			`state <= stm_typ_s_data;`
385			`end`
386			`else`
387			`begin`
388			`state <= stm_typ_s_idle;`
389			`end`
390			`end`
391			`stm_typ_s_data:`
392			`begin`
393			`if (eop_int == 1'b 0 & enable_int == 1'b 1)`
394			`begin`
395			`state <= stm_typ_s_data;`
396			`end`
397			`else if (eop_int == 1'b 0 & enable_int == 1'b 0 )`
398			`begin`
399			`state <= stm_typ_s_wait;`
400			`end`
401			`else if (eop_int == 1'b 1 )`
402			`begin`
403			`if (ipg_len_i < 4 & start == 1'b 1)`
404			`begin`
405			`state <= stm_typ_s_ipg0; // no IPG`
406			`end`
407			`else if (ipg_len_i < 8 )`
408			`begin`
409			`state <= stm_typ_s_idle;`
410			`end`
411			`else`
412			`begin`
413			`state <= stm_typ_s_ipg;`
414			`end`
415			`end`
416			`else`
417			`begin`
418			`state <= stm_typ_s_data;`
419			`end`
420			`end`
421			`stm_typ_s_ipg:`
422			`begin`
423			`if (count < ipg_len_i)`
424			`begin`
425			`state <= stm_typ_s_ipg;`
426			`end`
427			`else`
428			`begin`
429			`state <= stm_typ_s_idle;`
430			`end`
431			`end`
432			`stm_typ_s_ipg0:`
433			`begin`
434			`state <= stm_typ_s_data;`
435			`end`
436			`stm_typ_s_wait:`
437			`begin`
438			`if (enable_int == 1'b 1)`
439			`begin`
440			`state <= stm_typ_s_data;`
441			`end`
442			`else`
443			`begin`
444			`state <= stm_typ_s_wait;`
445			`end`
446			`end`
447			`default:`
448			`begin`
449			`state <= stm_typ_s_idle;`
450			`end`
451			`endcase`
452			`end`
453			`end`
454
455
456
457			`always @(posedge clk or posedge reset)`
458			`begin`
459			`if (reset == 1'b 1)`
460			`begin`
461			`dout_temp <= {8{1'b 0}};`
462			`dval_temp <= {{1'b 0}};`
463			`derror_temp<= {{1'b 0}};`
464			`sop_temp <= {{1'b 0}};`
465			`eop_temp <= {{1'b 0}};`
466			`done_temp <= 1'b 0;`
467
468
469			`end`
470			`else`
471			`begin`
472			`dout_temp <= #(thold) dout_reg;`
473			`dval_temp <= #(thold) dval_reg;`
474			`derror_temp <= #(thold) derror_reg;`
475			`sop_temp <= #(thold) sop_ex;`
476			`eop_temp <= #(thold) eop_ex;`
477			`done_temp <= #(thold) done_reg;`
478			`end`
479			`end`
480
481			`generate if (ZERO_LATENCY == 1)`
482			`begin`
483			`timing_adapter_8 tb_adapter (`
484
485			`// Interface: clk`
486			`.clk(clk), //input`
487			`.reset(reset), //input`
488			`// Interface: in`
489			`.in_ready(enable_int), //output`
490			`.in_valid(dval_temp), //input`
491			`.in_data(dout_temp), //input`
492			`.in_startofpacket(sop_temp), //input`
493			`.in_endofpacket(eop_temp), //input`
494			`.in_error({derror_temp}), //input`
495			`// Interface: out`
496			`.out_ready(enable), //input`
497			`.out_valid(dval), //output`
498			`.out_data(dout), //output`
499			`.out_startofpacket(sop), //output`
500			`.out_endofpacket(eop), //output`
501			`.out_error({derror}) //output`
502
503			`);`
504
505			`assign done = done_temp;`
506			`end`
507			`else`
508			`begin`
509			`always @(posedge clk or posedge reset)`
510			`begin`
511			`if (reset == 1'b 1)`
512			`enable_reg <= 1'b 0;`
513			`else`
514			`enable_reg <= enable;`
515			`end`
516			`assign enable_int = enable_reg;`
517			`assign dout = dout_temp;`
518			`assign dval = dval_temp;`
519			`assign derror = derror_temp;`
520			`assign sop = sop_temp;`
521			`assign eop = eop_temp;`
522			`assign done = done_temp;`
523			`end`
524			`endgenerate`
525
526
527			`// Generator`
528			`// ---------`
529			`ethgenerator gen1g (`
530			`.reset(reset),`
531			`.rx_clk(tx_clk),`
532			`.enable(1'b1),`
533			`.rxd(rxd),`
534			`.rx_dv(rx_dv),`
535			`.rx_er(rx_er),`
536			`.sop(sop_gen),`
537			`.eop(eop_gen),`
538			`.mac_reverse(mac_reverse),`
539			`.dst(dst),`
540			`.src(src),`
541			`.prmble_len(prmble_len),`
542			`.pquant(pquant),`
543			`.vlan_ctl(vlan_ctl),`
544			`.len(len),`
545			`.frmtype(frmtype),`
546			`.cntstart(cntstart),`
547			`.cntstep(cntstep),`
548			`.ipg_len(16'h 4),`
549			`.payload_err(payload_err),`
550			`.prmbl_err(prmbl_err),`
551			`.crc_err(crc_err),`
552			`.vlan_en(vlan_en),`
553			`.stack_vlan(stack_vlan),`
554			`.pause_gen(pause_gen),`
555			`.pad_en(pad_en),`
556			`.phy_err(phy_err),`
557			`.end_err(end_err),`
558			`.data_only(data_only),`
559			`.runt_gen(1'b0) ,`
560			`.long_pause(1'b0),`
561			`.carrier_sense(1'b0),`
562			`.false_carrier(1'b0),`
563			`.carrier_extend(1'b0),`
564			`.carrier_extend_error(1'b0),`
565			`.start(start_gen),`
566			`.done(done_gen));`
567
568			`defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;`
569			`defparam gen1g.thold = 0.1;`
570
571
572			`endmodule // module top_ethgenerator_8`
573