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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: top_ethmon32.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/top_ethmon32.v,v $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : SKNg/TTChong
//
// Project     : Triple Speed Ethernet - 10/100/1000 MAC 
//
// Description : (Simulation only)
//
// Ethernet Traffic Monitor/Decoder for 32 bit MAC Atlantic client interface
// Instantiates ethmonitor_32 (ethmon_32.v)
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
`timescale 1 ns / 10 ps  // timescale for following modules
 
 
module top_ethmonitor32 (
 
   reset,
   clk,
   din,
   dval,
   derror,
   sop,
   eop,
   tmod,
   dst,
   src,
   prmble_len,
   pquant,
   vlan_ctl,
   len,
   frmtype,
   payload,
   payload_vld,
   is_vlan,
   is_stack_vlan,
   is_pause,
   crc_err,
   prmbl_err,
   len_err,
   payload_err,
   frame_err,
   pause_op_err,
   pause_dst_err,
   mac_err,
   end_err,
   jumbo_en,
   data_only,
   frm_rcvd);
 
parameter ENABLE_SHIFT16 = 1'b 0;
parameter BIG_ENDIAN = 1'b1;
 
 
 
input   reset; //  active high
input   clk;
input   [31:0] din;
input   dval;
input   derror;
input   sop; //  pulse with first word
input   eop; //  pulse with last word (tmod valid)
input   [1:0] tmod; //  last word modulo
output   [47:0] dst; //  destination address
output   [47:0] src; //  source address
output   [13:0] prmble_len; //  length of preamble
output   [15:0] pquant; //  Pause Quanta value
output   [15:0] vlan_ctl; //  VLAN control info
output   [15:0] len; //  Length of payload
output   [15:0] frmtype; //  if non-null: type field instead length
output   [7:0] payload;
output   payload_vld;
output   is_vlan;
output   is_stack_vlan;
output   is_pause;
output   crc_err;
output   prmbl_err;
output   len_err;
output   payload_err;
output   frame_err;
output   pause_op_err;
output   pause_dst_err;
output   mac_err;
output   end_err;
input   jumbo_en;
input   data_only;
output   frm_rcvd;
reg     [47:0] dst;
reg     [47:0] src;
reg     [13:0] prmble_len;
reg     [15:0] pquant;
reg     [15:0] vlan_ctl;
reg     [15:0] len;
reg     [15:0] frmtype;
wire    [7:0] payload;
//  Indicators
wire    payload_vld;
reg     is_vlan;
reg     is_stack_vlan;
reg     is_pause;
reg     crc_err;
reg     prmbl_err;
reg     len_err;
reg     payload_err;
reg     frame_err;
reg     pause_op_err;
reg     pause_dst_err;
reg     mac_err;
//  Control
reg     end_err;
wire    frm_rcvd;
wire    frm_rcvd_i; //  from gen
reg     frm_rcvd_d; //  delayed for handshake
reg     frm_rcvd_ex; //  external
//  GMII Monitor signals
reg     tx_clk; //  8 times the XGMII
wire    [7:0] txd;
wire    tx_dv;
wire    tx_er;
//  internal
reg     fast_clk;
integer fast_clk_cnt;
reg     fast_clk_gate;
reg     clk_d;
//  captured word data 
reg     [31:0] din_int;
reg     dval_int;
reg     derror_int;
reg     sop_int; //  pulse with first word             
reg     eop_int; //  pulse with last word (tmod valid) 
reg     [1:0] tmod_int; //  last word modulo
//  shift registers to feed GMII Monitor
reg     eop_int_d;
reg     eop_done;
reg     [31:0] txd_shift;
reg     [3:0] txdv_shift;
//  internal 
wire    [47:0] l_dst; //  destination address
wire    [47:0] l_src; //  source address
wire    [13:0] l_prmble_len; //  length of preamble
wire    [15:0] l_pquant; //  Pause Quanta value
wire    [15:0] l_vlan_ctl; //  VLAN control info
wire    [15:0] l_len; //  Length of payload
wire    [15:0] l_frmtype; //  if non-null: type field instead length
wire    l_is_vlan;
wire    l_is_stack_vlan;
wire    l_is_pause;
wire    l_crc_err;
wire    l_prmbl_err;
wire    l_len_err;
wire    l_payload_err;
wire    l_frame_err;
wire    l_pause_op_err;
wire    l_pause_dst_err;
wire    l_mac_err;
wire    l_end_err;
 
 
reg   [31:0] din_reg;
reg   dval_reg;
reg   derror_reg;
reg   sop_reg; //  pulse with first word
reg   eop_reg; //  pulse with last word (tmod valid)
reg   [1:0] tmod_reg; //  last word modulo
 
//  Capture word data input
//  ----------------------------------
 
always @(posedge clk or posedge reset)
   begin : process_1
   if (reset == 1'b 1)
      begin
      din_int <= {32{1'b 0}};
      dval_int <= 1'b 0;
      derror_int <= 1'b 0;
      sop_int <= 1'b 0;
      eop_int <= 1'b 0;
      tmod_int <= {2{1'b 0}};
      frm_rcvd_ex <= 1'b 0;
      eop_int_d <= 1'b 0;
      end
   else
      begin
      din_int <= din_reg;
      dval_int <= dval_reg;
      derror_int <= derror_reg;
      sop_int <= sop_reg;
      eop_int <= eop_reg;
      tmod_int <= tmod_reg;
      frm_rcvd_ex <= frm_rcvd_d;
      eop_int_d <= eop_int & dval_int;
 
      end
   end
//  Results in word clock domain
//  ----------------------------------
assign frm_rcvd = frm_rcvd_ex;
always @(posedge clk or posedge reset)
   begin : process_2
   if (reset == 1'b 1)
      begin
      dst <= {48{1'b 0}};
      src <= {48{1'b 0}};
      prmble_len <= 0;
      pquant <= {16{1'b 0}};
      vlan_ctl <= {16{1'b 0}};
      len <= {16{1'b 0}};
      frmtype <= {16{1'b 0}};
      is_vlan <= 1'b 0;
      is_stack_vlan <= 1'b 0;
      is_pause <= 1'b 0;
      crc_err <= 1'b 0;
      prmbl_err <= 1'b 0;
      len_err <= 1'b 0;
      payload_err <= 1'b 0;
      frame_err <= 1'b 0;
      pause_op_err <= 1'b 0;
      pause_dst_err <= 1'b 0;
      mac_err <= 1'b 0;
      end_err <= 1'b 0;
      end
   else
      begin
 
        if(dval_int == 1'b 1) begin
                dst <= l_dst;
                src <= l_src;
                prmble_len <= l_prmble_len;
                is_vlan <= l_is_vlan;
                is_stack_vlan <= l_is_stack_vlan;
                is_pause <= l_is_pause;
                pause_op_err <= l_pause_op_err;
                pause_dst_err <= l_pause_dst_err;
                pquant <= l_pquant;
                vlan_ctl <= l_vlan_ctl;
                prmbl_err <= l_prmbl_err;
                frame_err <= l_frame_err;
                mac_err <= l_mac_err;
                end_err <= l_end_err;
        end
 
      len <= l_len;
      frmtype <= l_frmtype;
      crc_err <= l_crc_err;
      len_err <= l_len_err;
      payload_err <= l_payload_err;
      end
   end
//  create fast clock synchronized to clk rising edge
//  -------------------------------------------------
always
   begin : process_3
   fast_clk <= 1'b 0;
   #( 0.4 );
   fast_clk <= 1'b 1;
   #( 0.4 );
   end
 
always @(negedge fast_clk or posedge reset)
   begin : process_4
   if (reset == 1'b 1)
      begin
      fast_clk_gate <= 1'b 0;
      fast_clk_cnt <= 3;
      clk_d <= 1'b 0;
      frm_rcvd_d <= 1'b 0;
      txd_shift <= {32{1'b 0}};
      txdv_shift <= {4{1'b 0}};
      eop_done <= 1'b 0;    //  remember when we added 2 extra cycles after EOP
      end
   else
      begin
//  work on neg edge
      clk_d <= clk;
      if (clk_d == 1'b 1 & clk == 1'b 0 &
    fast_clk_cnt > 2 & dval_int == 1'b 1)
         begin
//  wait for neg edge
         fast_clk_cnt <= 0;
         fast_clk_gate <= 1'b 1;
//  load shift registers
         txd_shift <= din_int;
         if (eop_int == 1'b 1 & dval_int == 1'b 1)
            begin
            case (tmod_int)
            2'b 00:
               begin
               txdv_shift <= 4'b 1111;
               end
            2'b 01:
               begin
               txdv_shift <= 4'b 0001;
               end
            2'b 10:
               begin
               txdv_shift <= 4'b 0011;
               end
            2'b 11:
               begin
               txdv_shift <= 4'b 0111;
               end
            default:
               begin
               txdv_shift <= 4'b 0000;
               end
            endcase
            end
         else if (dval_int == 1'b 1 )
            begin
            txdv_shift <= 4'b 1111;
            end
         end
      else if (fast_clk_cnt < 3 )
         begin
         fast_clk_cnt <= fast_clk_cnt + 1'b 1;
         txd_shift <= {8'h 00, txd_shift[31:8]};    //  LSByte first
         txdv_shift <= {1'b 0, txdv_shift[3:1]};
         fast_clk_gate <= 1'b 1;
         end
      else if (fast_clk_cnt < 7 & eop_int_d == 1'b 1 & eop_done == 1'b 0 )
         begin
//  give 2 more at end of frame to generate the frm_rcvd
         txdv_shift <= 4'b 0000;
         fast_clk_cnt <= fast_clk_cnt + 1'b 1;
         fast_clk_gate <= 1'b 1;
         end
      else
         begin
         fast_clk_gate <= 1'b 0;
         end
//  indicate when we finished the old frame (giving extra cycles after last bytes) 
//  to block eop_int_d indication in case b2b frames are received
      if (fast_clk_cnt == 7 & eop_int_d == 1'b 1)
         begin
         eop_done <= 1'b 1;
         end
      else if (eop_int_d == 1'b 0 )
         begin
         eop_done <= 1'b 0;
         end
//  capture frame received indication and sync it to word clock (handshake)
      if (frm_rcvd_i == 1'b 1)
         begin
         frm_rcvd_d <= 1'b 1;
         end
      else if (frm_rcvd_ex == 1'b 1 )
         begin
         frm_rcvd_d <= 1'b 0;
         end
      end
   end
 
//  DDR process to generate gated clock
always @(fast_clk or reset)
   begin : process_5
   if (reset == 1'b 1)
      begin
      tx_clk <= 1'b 0;
      end
   else if ( fast_clk == 1'b 1 )
      begin
      if (fast_clk_gate == 1'b 1)
         begin
         tx_clk <= 1'b 1;
         end
      end
   else if ( fast_clk == 1'b 0 )
      begin
      tx_clk <= 1'b 0;
      end
   end
 
//  Use shifted word data to generate GMII signals
//  ----------------------------------------------------------
assign txd = txd_shift[7:0];
assign tx_dv = txdv_shift[0];
assign tx_er = derror_int;
 
 
 
// endian adapter from Little endian to Big endian
 
// input   [31:0] din; 
// input   dval; 
// input   derror; 
// input   sop; //  pulse with first word
// input   eop; //  pulse with last word (tmod valid)
// input   [1:0] tmod; //  last word modulo
 
always @(posedge clk or posedge reset)
 begin
   if (reset == 1'b 1)
      begin
          din_reg   <= {32{1'b 0}};
          dval_reg  <= {{1'b 0}};
          derror_reg<= {{1'b 0}};
          sop_reg   <= {{1'b 0}}; //  pulse with first word
          eop_reg   <= {{1'b 0}}; //  pulse with last word (tmod valid)
          tmod_reg  <= {2{1'b 0}}; //  last word modulo
      end
   else
    begin
        if (BIG_ENDIAN ==1'b1)
         begin
             din_reg   <= {din[7:0],din[15:8],din[23:16],din[31:24]};
             dval_reg  <= dval;
             derror_reg<= derror;
             sop_reg   <= sop; //  pulse with first word
             eop_reg   <= eop; //  pulse with last word (tmod valid)
 
             case (tmod)
               2'b00:  tmod_reg <= 2'b00;
               2'b01:  tmod_reg <= 2'b11;
               2'b10:  tmod_reg <= 2'b10;
               2'b11:  tmod_reg <= 2'b01;
               default:tmod_reg <= {{1'b 0}};
             endcase
 
         end
        else
         begin
             din_reg           <= din;
             dval_reg          <= dval;
             derror_reg        <= derror;
             sop_reg           <= sop;
             eop_reg           <= eop;
             tmod_reg          <= tmod;
         end
    end
 end
 
 
 
//  Monitor
//  ---------
ethmonitor_32 mon1g (.reset(reset),
          .tx_clk(tx_clk),
          .txd(txd),
          .tx_dv(tx_dv),
          .tx_er(tx_er),
          .dst(l_dst),
          .src(l_src),
          .prmble_len(l_prmble_len),
          .pquant(l_pquant),
          .vlan_ctl(l_vlan_ctl),
          .len(l_len),
          .frmtype(l_frmtype),
          .payload(payload),
          .payload_vld(payload_vld),
          .is_vlan(l_is_vlan),
          .is_stack_vlan(l_is_stack_vlan),
          .is_pause(l_is_pause),
          .crc_err(l_crc_err),
          .prmbl_err(l_prmbl_err),
          .len_err(l_len_err),
          .payload_err(l_payload_err),
          .frame_err(l_frame_err),
          .pause_op_err(l_pause_op_err),
          .pause_dst_err(l_pause_dst_err),
          .mac_err(l_mac_err),
          .end_err(l_end_err),
          .jumbo_en(jumbo_en),
          .data_only(data_only),
          .frm_rcvd(frm_rcvd_i));
 
defparam mon1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;
 
endmodule // module ethmonitor32
 

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [top_ethmon32.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: top_ethmon32.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/top_ethmon32.v,v $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : SKNg/TTChong`
13			`//`
14			`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
15			`//`
16			`// Description : (Simulation only)`
17			`//`
18			`// Ethernet Traffic Monitor/Decoder for 32 bit MAC Atlantic client interface`
19			`// Instantiates ethmonitor_32 (ethmon_32.v)`
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2006 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`timescale 1 ns / 10 ps // timescale for following modules
29
30
31			`module top_ethmonitor32 (`
32
33			`reset,`
34			`clk,`
35			`din,`
36			`dval,`
37			`derror,`
38			`sop,`
39			`eop,`
40			`tmod,`
41			`dst,`
42			`src,`
43			`prmble_len,`
44			`pquant,`
45			`vlan_ctl,`
46			`len,`
47			`frmtype,`
48			`payload,`
49			`payload_vld,`
50			`is_vlan,`
51			`is_stack_vlan,`
52			`is_pause,`
53			`crc_err,`
54			`prmbl_err,`
55			`len_err,`
56			`payload_err,`
57			`frame_err,`
58			`pause_op_err,`
59			`pause_dst_err,`
60			`mac_err,`
61			`end_err,`
62			`jumbo_en,`
63			`data_only,`
64			`frm_rcvd);`
65
66			`parameter ENABLE_SHIFT16 = 1'b 0;`
67			`parameter BIG_ENDIAN = 1'b1;`
68
69
70
71			`input reset; // active high`
72			`input clk;`
73			`input [31:0] din;`
74			`input dval;`
75			`input derror;`
76			`input sop; // pulse with first word`
77			`input eop; // pulse with last word (tmod valid)`
78			`input [1:0] tmod; // last word modulo`
79			`output [47:0] dst; // destination address`
80			`output [47:0] src; // source address`
81			`output [13:0] prmble_len; // length of preamble`
82			`output [15:0] pquant; // Pause Quanta value`
83			`output [15:0] vlan_ctl; // VLAN control info`
84			`output [15:0] len; // Length of payload`
85			`output [15:0] frmtype; // if non-null: type field instead length`
86			`output [7:0] payload;`
87			`output payload_vld;`
88			`output is_vlan;`
89			`output is_stack_vlan;`
90			`output is_pause;`
91			`output crc_err;`
92			`output prmbl_err;`
93			`output len_err;`
94			`output payload_err;`
95			`output frame_err;`
96			`output pause_op_err;`
97			`output pause_dst_err;`
98			`output mac_err;`
99			`output end_err;`
100			`input jumbo_en;`
101			`input data_only;`
102			`output frm_rcvd;`
103			`reg [47:0] dst;`
104			`reg [47:0] src;`
105			`reg [13:0] prmble_len;`
106			`reg [15:0] pquant;`
107			`reg [15:0] vlan_ctl;`
108			`reg [15:0] len;`
109			`reg [15:0] frmtype;`
110			`wire [7:0] payload;`
111			`// Indicators`
112			`wire payload_vld;`
113			`reg is_vlan;`
114			`reg is_stack_vlan;`
115			`reg is_pause;`
116			`reg crc_err;`
117			`reg prmbl_err;`
118			`reg len_err;`
119			`reg payload_err;`
120			`reg frame_err;`
121			`reg pause_op_err;`
122			`reg pause_dst_err;`
123			`reg mac_err;`
124			`// Control`
125			`reg end_err;`
126			`wire frm_rcvd;`
127			`wire frm_rcvd_i; // from gen`
128			`reg frm_rcvd_d; // delayed for handshake`
129			`reg frm_rcvd_ex; // external`
130			`// GMII Monitor signals`
131			`reg tx_clk; // 8 times the XGMII`
132			`wire [7:0] txd;`
133			`wire tx_dv;`
134			`wire tx_er;`
135			`// internal`
136			`reg fast_clk;`
137			`integer fast_clk_cnt;`
138			`reg fast_clk_gate;`
139			`reg clk_d;`
140			`// captured word data`
141			`reg [31:0] din_int;`
142			`reg dval_int;`
143			`reg derror_int;`
144			`reg sop_int; // pulse with first word`
145			`reg eop_int; // pulse with last word (tmod valid)`
146			`reg [1:0] tmod_int; // last word modulo`
147			`// shift registers to feed GMII Monitor`
148			`reg eop_int_d;`
149			`reg eop_done;`
150			`reg [31:0] txd_shift;`
151			`reg [3:0] txdv_shift;`
152			`// internal`
153			`wire [47:0] l_dst; // destination address`
154			`wire [47:0] l_src; // source address`
155			`wire [13:0] l_prmble_len; // length of preamble`
156			`wire [15:0] l_pquant; // Pause Quanta value`
157			`wire [15:0] l_vlan_ctl; // VLAN control info`
158			`wire [15:0] l_len; // Length of payload`
159			`wire [15:0] l_frmtype; // if non-null: type field instead length`
160			`wire l_is_vlan;`
161			`wire l_is_stack_vlan;`
162			`wire l_is_pause;`
163			`wire l_crc_err;`
164			`wire l_prmbl_err;`
165			`wire l_len_err;`
166			`wire l_payload_err;`
167			`wire l_frame_err;`
168			`wire l_pause_op_err;`
169			`wire l_pause_dst_err;`
170			`wire l_mac_err;`
171			`wire l_end_err;`
172
173
174			`reg [31:0] din_reg;`
175			`reg dval_reg;`
176			`reg derror_reg;`
177			`reg sop_reg; // pulse with first word`
178			`reg eop_reg; // pulse with last word (tmod valid)`
179			`reg [1:0] tmod_reg; // last word modulo`
180
181			`// Capture word data input`
182			`// ----------------------------------`
183
184			`always @(posedge clk or posedge reset)`
185			`begin : process_1`
186			`if (reset == 1'b 1)`
187			`begin`
188			`din_int <= {32{1'b 0}};`
189			`dval_int <= 1'b 0;`
190			`derror_int <= 1'b 0;`
191			`sop_int <= 1'b 0;`
192			`eop_int <= 1'b 0;`
193			`tmod_int <= {2{1'b 0}};`
194			`frm_rcvd_ex <= 1'b 0;`
195			`eop_int_d <= 1'b 0;`
196			`end`
197			`else`
198			`begin`
199			`din_int <= din_reg;`
200			`dval_int <= dval_reg;`
201			`derror_int <= derror_reg;`
202			`sop_int <= sop_reg;`
203			`eop_int <= eop_reg;`
204			`tmod_int <= tmod_reg;`
205			`frm_rcvd_ex <= frm_rcvd_d;`
206			`eop_int_d <= eop_int & dval_int;`
207
208			`end`
209			`end`
210			`// Results in word clock domain`
211			`// ----------------------------------`
212			`assign frm_rcvd = frm_rcvd_ex;`
213			`always @(posedge clk or posedge reset)`
214			`begin : process_2`
215			`if (reset == 1'b 1)`
216			`begin`
217			`dst <= {48{1'b 0}};`
218			`src <= {48{1'b 0}};`
219			`prmble_len <= 0;`
220			`pquant <= {16{1'b 0}};`
221			`vlan_ctl <= {16{1'b 0}};`
222			`len <= {16{1'b 0}};`
223			`frmtype <= {16{1'b 0}};`
224			`is_vlan <= 1'b 0;`
225			`is_stack_vlan <= 1'b 0;`
226			`is_pause <= 1'b 0;`
227			`crc_err <= 1'b 0;`
228			`prmbl_err <= 1'b 0;`
229			`len_err <= 1'b 0;`
230			`payload_err <= 1'b 0;`
231			`frame_err <= 1'b 0;`
232			`pause_op_err <= 1'b 0;`
233			`pause_dst_err <= 1'b 0;`
234			`mac_err <= 1'b 0;`
235			`end_err <= 1'b 0;`
236			`end`
237			`else`
238			`begin`
239
240			`if(dval_int == 1'b 1) begin`
241			`dst <= l_dst;`
242			`src <= l_src;`
243			`prmble_len <= l_prmble_len;`
244			`is_vlan <= l_is_vlan;`
245			`is_stack_vlan <= l_is_stack_vlan;`
246			`is_pause <= l_is_pause;`
247			`pause_op_err <= l_pause_op_err;`
248			`pause_dst_err <= l_pause_dst_err;`
249			`pquant <= l_pquant;`
250			`vlan_ctl <= l_vlan_ctl;`
251			`prmbl_err <= l_prmbl_err;`
252			`frame_err <= l_frame_err;`
253			`mac_err <= l_mac_err;`
254			`end_err <= l_end_err;`
255			`end`
256
257			`len <= l_len;`
258			`frmtype <= l_frmtype;`
259			`crc_err <= l_crc_err;`
260			`len_err <= l_len_err;`
261			`payload_err <= l_payload_err;`
262			`end`
263			`end`
264			`// create fast clock synchronized to clk rising edge`
265			`// -------------------------------------------------`
266			`always`
267			`begin : process_3`
268			`fast_clk <= 1'b 0;`
269			`#( 0.4 );`
270			`fast_clk <= 1'b 1;`
271			`#( 0.4 );`
272			`end`
273
274			`always @(negedge fast_clk or posedge reset)`
275			`begin : process_4`
276			`if (reset == 1'b 1)`
277			`begin`
278			`fast_clk_gate <= 1'b 0;`
279			`fast_clk_cnt <= 3;`
280			`clk_d <= 1'b 0;`
281			`frm_rcvd_d <= 1'b 0;`
282			`txd_shift <= {32{1'b 0}};`
283			`txdv_shift <= {4{1'b 0}};`
284			`eop_done <= 1'b 0; // remember when we added 2 extra cycles after EOP`
285			`end`
286			`else`
287			`begin`
288			`// work on neg edge`
289			`clk_d <= clk;`
290			`if (clk_d == 1'b 1 & clk == 1'b 0 &`
291			`fast_clk_cnt > 2 & dval_int == 1'b 1)`
292			`begin`
293			`// wait for neg edge`
294			`fast_clk_cnt <= 0;`
295			`fast_clk_gate <= 1'b 1;`
296			`// load shift registers`
297			`txd_shift <= din_int;`
298			`if (eop_int == 1'b 1 & dval_int == 1'b 1)`
299			`begin`
300			`case (tmod_int)`
301			`2'b 00:`
302			`begin`
303			`txdv_shift <= 4'b 1111;`
304			`end`
305			`2'b 01:`
306			`begin`
307			`txdv_shift <= 4'b 0001;`
308			`end`
309			`2'b 10:`
310			`begin`
311			`txdv_shift <= 4'b 0011;`
312			`end`
313			`2'b 11:`
314			`begin`
315			`txdv_shift <= 4'b 0111;`
316			`end`
317			`default:`
318			`begin`
319			`txdv_shift <= 4'b 0000;`
320			`end`
321			`endcase`
322			`end`
323			`else if (dval_int == 1'b 1 )`
324			`begin`
325			`txdv_shift <= 4'b 1111;`
326			`end`
327			`end`
328			`else if (fast_clk_cnt < 3 )`
329			`begin`
330			`fast_clk_cnt <= fast_clk_cnt + 1'b 1;`
331			`txd_shift <= {8'h 00, txd_shift[31:8]}; // LSByte first`
332			`txdv_shift <= {1'b 0, txdv_shift[3:1]};`
333			`fast_clk_gate <= 1'b 1;`
334			`end`
335			`else if (fast_clk_cnt < 7 & eop_int_d == 1'b 1 & eop_done == 1'b 0 )`
336			`begin`
337			`// give 2 more at end of frame to generate the frm_rcvd`
338			`txdv_shift <= 4'b 0000;`
339			`fast_clk_cnt <= fast_clk_cnt + 1'b 1;`
340			`fast_clk_gate <= 1'b 1;`
341			`end`
342			`else`
343			`begin`
344			`fast_clk_gate <= 1'b 0;`
345			`end`
346			`// indicate when we finished the old frame (giving extra cycles after last bytes)`
347			`// to block eop_int_d indication in case b2b frames are received`
348			`if (fast_clk_cnt == 7 & eop_int_d == 1'b 1)`
349			`begin`
350			`eop_done <= 1'b 1;`
351			`end`
352			`else if (eop_int_d == 1'b 0 )`
353			`begin`
354			`eop_done <= 1'b 0;`
355			`end`
356			`// capture frame received indication and sync it to word clock (handshake)`
357			`if (frm_rcvd_i == 1'b 1)`
358			`begin`
359			`frm_rcvd_d <= 1'b 1;`
360			`end`
361			`else if (frm_rcvd_ex == 1'b 1 )`
362			`begin`
363			`frm_rcvd_d <= 1'b 0;`
364			`end`
365			`end`
366			`end`
367
368			`// DDR process to generate gated clock`
369			`always @(fast_clk or reset)`
370			`begin : process_5`
371			`if (reset == 1'b 1)`
372			`begin`
373			`tx_clk <= 1'b 0;`
374			`end`
375			`else if ( fast_clk == 1'b 1 )`
376			`begin`
377			`if (fast_clk_gate == 1'b 1)`
378			`begin`
379			`tx_clk <= 1'b 1;`
380			`end`
381			`end`
382			`else if ( fast_clk == 1'b 0 )`
383			`begin`
384			`tx_clk <= 1'b 0;`
385			`end`
386			`end`
387
388			`// Use shifted word data to generate GMII signals`
389			`// ----------------------------------------------------------`
390			`assign txd = txd_shift[7:0];`
391			`assign tx_dv = txdv_shift[0];`
392			`assign tx_er = derror_int;`
393
394
395
396			`// endian adapter from Little endian to Big endian`
397
398			`// input [31:0] din;`
399			`// input dval;`
400			`// input derror;`
401			`// input sop; // pulse with first word`
402			`// input eop; // pulse with last word (tmod valid)`
403			`// input [1:0] tmod; // last word modulo`
404
405			`always @(posedge clk or posedge reset)`
406			`begin`
407			`if (reset == 1'b 1)`
408			`begin`
409			`din_reg <= {32{1'b 0}};`
410			`dval_reg <= {{1'b 0}};`
411			`derror_reg<= {{1'b 0}};`
412			`sop_reg <= {{1'b 0}}; // pulse with first word`
413			`eop_reg <= {{1'b 0}}; // pulse with last word (tmod valid)`
414			`tmod_reg <= {2{1'b 0}}; // last word modulo`
415			`end`
416			`else`
417			`begin`
418			`if (BIG_ENDIAN ==1'b1)`
419			`begin`
420			`din_reg <= {din[7:0],din[15:8],din[23:16],din[31:24]};`
421			`dval_reg <= dval;`
422			`derror_reg<= derror;`
423			`sop_reg <= sop; // pulse with first word`
424			`eop_reg <= eop; // pulse with last word (tmod valid)`
425
426			`case (tmod)`
427			`2'b00: tmod_reg <= 2'b00;`
428			`2'b01: tmod_reg <= 2'b11;`
429			`2'b10: tmod_reg <= 2'b10;`
430			`2'b11: tmod_reg <= 2'b01;`
431			`default:tmod_reg <= {{1'b 0}};`
432			`endcase`
433
434			`end`
435			`else`
436			`begin`
437			`din_reg <= din;`
438			`dval_reg <= dval;`
439			`derror_reg <= derror;`
440			`sop_reg <= sop;`
441			`eop_reg <= eop;`
442			`tmod_reg <= tmod;`
443			`end`
444			`end`
445			`end`
446
447
448
449			`// Monitor`
450			`// ---------`
451			`ethmonitor_32 mon1g (.reset(reset),`
452			`.tx_clk(tx_clk),`
453			`.txd(txd),`
454			`.tx_dv(tx_dv),`
455			`.tx_er(tx_er),`
456			`.dst(l_dst),`
457			`.src(l_src),`
458			`.prmble_len(l_prmble_len),`
459			`.pquant(l_pquant),`
460			`.vlan_ctl(l_vlan_ctl),`
461			`.len(l_len),`
462			`.frmtype(l_frmtype),`
463			`.payload(payload),`
464			`.payload_vld(payload_vld),`
465			`.is_vlan(l_is_vlan),`
466			`.is_stack_vlan(l_is_stack_vlan),`
467			`.is_pause(l_is_pause),`
468			`.crc_err(l_crc_err),`
469			`.prmbl_err(l_prmbl_err),`
470			`.len_err(l_len_err),`
471			`.payload_err(l_payload_err),`
472			`.frame_err(l_frame_err),`
473			`.pause_op_err(l_pause_op_err),`
474			`.pause_dst_err(l_pause_dst_err),`
475			`.mac_err(l_mac_err),`
476			`.end_err(l_end_err),`
477			`.jumbo_en(jumbo_en),`
478			`.data_only(data_only),`
479			`.frm_rcvd(frm_rcvd_i));`
480
481			`defparam mon1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;`
482
483			`endmodule // module ethmonitor32`
484